From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com, leo.yan@linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>, Peter Ziljstra <peterz@infradead.org>, alexander.shishkin@linux.intel.com, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, jolsa@redhat.com, Mathieu Poirier <mathieu.poirer@linaro.org> Subject: [PATCH v4 01/19] perf: aux: Add flags for the buffer format Date: Thu, 25 Feb 2021 19:35:25 +0000 [thread overview] Message-ID: <20210225193543.2920532-2-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210225193543.2920532-1-suzuki.poulose@arm.com> Allocate a byte for advertising the PMU specific format type of the given AUX record. A PMU could end up providing hardware trace data in multiple format in a single session. e.g, The format of hardware buffer produced by CoreSight ETM PMU depends on the type of the "sink" device used for collection for an event (Traditional TMC-ETR/Bs with formatting or TRBEs without any formatting). # Boring story of why this is needed. Goto The_End_of_Story for skipping. CoreSight ETM trace allows instruction level tracing of Arm CPUs. The ETM generates the CPU excecution trace and pumps it into CoreSight AMBA Trace Bus and is collected by a different CoreSight component (traditionally CoreSight TMC-ETR /ETB/ETF), called "sink". Important to note that there is no guarantee that every CPU has a dedicated sink. Thus multiple ETMs could pump the trace data into the same "sink" and thus they apply additional formatting of the trace data for the user to decode it properly and attribute the trace data to the corresponding ETM. However, with the introduction of Arm Trace buffer Extensions (TRBE), we now have a dedicated per-CPU architected sink for collecting the trace. Since the TRBE is always per-CPU, it doesn't apply any formatting of the trace. The support for this driver is under review [1]. Now a system could have a per-cpu TRBE and one or more shared TMC-ETRs on the system. A user could choose a "specific" sink for a perf session (e.g, a TMC-ETR) or the driver could automatically select the nearest sink for a given ETM. It is possible that some ETMs could end up using TMC-ETR (e.g, if the TRBE is not usable on the CPU) while the others using TRBE in a single perf session. Thus we now have "formatted" trace collected from TMC-ETR and "unformatted" trace collected from TRBE. However, we don't get into a situation where a single event could end up using TMC-ETR & TRBE. i.e, any AUX buffer is guaranteed to be either RAW or FORMATTED, but not a mix of both. As for perf decoding, we need to know the type of the data in the individual AUX buffers, so that it can set up the "OpenCSD" (library for decoding CoreSight trace) decoder instance appropriately. Thus the perf.data file must conatin the hints for the tool to decode the data correctly. Since this is a runtime variable, and perf tool doesn't have a control on what sink gets used (in case of automatic sink selection), we need this information made available from the PMU driver for each AUX record. # The_End_of_Story Cc: Peter Ziljstra <peterz@infradead.org> Cc: alexander.shishkin@linux.intel.com Cc: mingo@redhat.com Cc: will@kernel.org Cc: mark.rutland@arm.com Cc: mike.leach@linaro.org Cc: acme@kernel.org Cc: jolsa@redhat.com Cc: Mathieu Poirier <mathieu.poirer@linaro.org> Reviewed by: Mike Leach <mike.leach@linaro.org> Acked-by: Peter Ziljstra <peterz@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- include/uapi/linux/perf_event.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index ad15e40d7f5d..f006eeab6f0e 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1156,10 +1156,11 @@ enum perf_callchain_context { /** * PERF_RECORD_AUX::flags bits */ -#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ -#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ -#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ -#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ +#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ +#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ +#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ +#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ +#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ #define PERF_FLAG_FD_NO_GROUP (1UL << 0) #define PERF_FLAG_FD_OUTPUT (1UL << 1) -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, mathieu.poirier@linaro.org, anshuman.khandual@arm.com, Peter Ziljstra <peterz@infradead.org>, jolsa@redhat.com, Suzuki K Poulose <suzuki.poulose@arm.com>, linux-kernel@vger.kernel.org, acme@kernel.org, alexander.shishkin@linux.intel.com, mingo@redhat.com, leo.yan@linaro.org, Mathieu Poirier <mathieu.poirer@linaro.org>, will@kernel.org, mike.leach@linaro.org Subject: [PATCH v4 01/19] perf: aux: Add flags for the buffer format Date: Thu, 25 Feb 2021 19:35:25 +0000 [thread overview] Message-ID: <20210225193543.2920532-2-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210225193543.2920532-1-suzuki.poulose@arm.com> Allocate a byte for advertising the PMU specific format type of the given AUX record. A PMU could end up providing hardware trace data in multiple format in a single session. e.g, The format of hardware buffer produced by CoreSight ETM PMU depends on the type of the "sink" device used for collection for an event (Traditional TMC-ETR/Bs with formatting or TRBEs without any formatting). # Boring story of why this is needed. Goto The_End_of_Story for skipping. CoreSight ETM trace allows instruction level tracing of Arm CPUs. The ETM generates the CPU excecution trace and pumps it into CoreSight AMBA Trace Bus and is collected by a different CoreSight component (traditionally CoreSight TMC-ETR /ETB/ETF), called "sink". Important to note that there is no guarantee that every CPU has a dedicated sink. Thus multiple ETMs could pump the trace data into the same "sink" and thus they apply additional formatting of the trace data for the user to decode it properly and attribute the trace data to the corresponding ETM. However, with the introduction of Arm Trace buffer Extensions (TRBE), we now have a dedicated per-CPU architected sink for collecting the trace. Since the TRBE is always per-CPU, it doesn't apply any formatting of the trace. The support for this driver is under review [1]. Now a system could have a per-cpu TRBE and one or more shared TMC-ETRs on the system. A user could choose a "specific" sink for a perf session (e.g, a TMC-ETR) or the driver could automatically select the nearest sink for a given ETM. It is possible that some ETMs could end up using TMC-ETR (e.g, if the TRBE is not usable on the CPU) while the others using TRBE in a single perf session. Thus we now have "formatted" trace collected from TMC-ETR and "unformatted" trace collected from TRBE. However, we don't get into a situation where a single event could end up using TMC-ETR & TRBE. i.e, any AUX buffer is guaranteed to be either RAW or FORMATTED, but not a mix of both. As for perf decoding, we need to know the type of the data in the individual AUX buffers, so that it can set up the "OpenCSD" (library for decoding CoreSight trace) decoder instance appropriately. Thus the perf.data file must conatin the hints for the tool to decode the data correctly. Since this is a runtime variable, and perf tool doesn't have a control on what sink gets used (in case of automatic sink selection), we need this information made available from the PMU driver for each AUX record. # The_End_of_Story Cc: Peter Ziljstra <peterz@infradead.org> Cc: alexander.shishkin@linux.intel.com Cc: mingo@redhat.com Cc: will@kernel.org Cc: mark.rutland@arm.com Cc: mike.leach@linaro.org Cc: acme@kernel.org Cc: jolsa@redhat.com Cc: Mathieu Poirier <mathieu.poirer@linaro.org> Reviewed by: Mike Leach <mike.leach@linaro.org> Acked-by: Peter Ziljstra <peterz@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- include/uapi/linux/perf_event.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index ad15e40d7f5d..f006eeab6f0e 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1156,10 +1156,11 @@ enum perf_callchain_context { /** * PERF_RECORD_AUX::flags bits */ -#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ -#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ -#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ -#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ +#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ +#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ +#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ +#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ +#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ #define PERF_FLAG_FD_NO_GROUP (1UL << 0) #define PERF_FLAG_FD_OUTPUT (1UL << 1) -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-25 19:40 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-25 19:35 [PATCH v4 00/19] arm64: coresight: Add support for ETE and TRBE Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose [this message] 2021-02-25 19:35 ` [PATCH v4 01/19] perf: aux: Add flags for the buffer format Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 02/19] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-16 17:04 ` Mathieu Poirier 2021-03-16 17:04 ` Mathieu Poirier 2021-03-22 12:29 ` Suzuki K Poulose 2021-03-22 12:29 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 03/19] kvm: arm64: Hide system instruction access to Trace registers Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-22 22:21 ` Suzuki K Poulose 2021-03-22 22:21 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 04/19] kvm: arm64: nvhe: Save the SPE context early Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-01 16:32 ` Alexandru Elisei 2021-03-01 16:32 ` Alexandru Elisei 2021-03-02 10:01 ` Suzuki K Poulose 2021-03-02 10:01 ` Suzuki K Poulose 2021-03-02 10:13 ` Marc Zyngier 2021-03-02 10:13 ` Marc Zyngier 2021-03-02 11:00 ` Alexandru Elisei 2021-03-02 11:00 ` Alexandru Elisei 2021-02-25 19:35 ` [PATCH v4 05/19] kvm: arm64: Disable guest access to trace filter controls Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-22 22:24 ` Suzuki K Poulose 2021-03-22 22:24 ` Suzuki K Poulose 2021-03-23 9:16 ` Marc Zyngier 2021-03-23 9:16 ` Marc Zyngier 2021-03-23 9:44 ` Suzuki K Poulose 2021-03-23 9:44 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 06/19] arm64: Add support for trace synchronization barrier Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 07/19] arm64: Add TRBE definitions Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-16 17:46 ` Mathieu Poirier 2021-03-16 17:46 ` Mathieu Poirier 2021-02-25 19:35 ` [PATCH v4 08/19] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-16 17:49 ` Mathieu Poirier 2021-03-16 17:49 ` Mathieu Poirier 2021-02-25 19:35 ` [PATCH v4 09/19] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-08 17:25 ` Mike Leach 2021-03-08 17:25 ` Mike Leach 2021-03-16 19:30 ` Mathieu Poirier 2021-03-16 19:30 ` Mathieu Poirier 2021-03-17 10:44 ` Suzuki K Poulose 2021-03-17 10:44 ` Suzuki K Poulose 2021-03-17 17:09 ` Mathieu Poirier 2021-03-17 17:09 ` Mathieu Poirier 2021-03-22 21:28 ` Mathieu Poirier 2021-03-22 21:28 ` Mathieu Poirier 2021-02-25 19:35 ` [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-08 17:25 ` Mike Leach 2021-03-08 17:25 ` Mike Leach 2021-03-16 20:23 ` Mathieu Poirier 2021-03-16 20:23 ` Mathieu Poirier 2021-03-17 10:47 ` Suzuki K Poulose 2021-03-17 10:47 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 11/19] coresight: Do not scan for graph if none is present Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 12/19] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 13/19] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 22:33 ` kernel test robot 2021-02-25 22:33 ` kernel test robot 2021-02-25 22:33 ` kernel test robot 2021-02-26 6:25 ` kernel test robot 2021-02-26 6:25 ` kernel test robot 2021-02-25 19:35 ` [PATCH v4 14/19] coresight: ete: Add support for ETE tracing Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 15/19] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-06 21:06 ` Rob Herring 2021-03-06 21:06 ` Rob Herring 2021-03-08 17:25 ` Mike Leach 2021-03-08 17:25 ` Mike Leach 2021-03-22 16:53 ` Suzuki K Poulose 2021-03-22 16:53 ` Suzuki K Poulose 2021-03-22 17:28 ` Rob Herring 2021-03-22 17:28 ` Rob Herring 2021-03-22 22:49 ` Suzuki K Poulose 2021-03-22 22:49 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 16/19] coresight: etm-perf: Handle stale output handles Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-25 19:35 ` [PATCH v4 17/19] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-02-26 6:34 ` kernel test robot 2021-02-26 6:34 ` kernel test robot 2021-02-26 6:34 ` kernel test robot 2021-03-01 13:54 ` Suzuki K Poulose 2021-03-01 13:54 ` Suzuki K Poulose 2021-03-01 13:54 ` Suzuki K Poulose 2021-03-02 10:21 ` Anshuman Khandual 2021-03-02 10:21 ` Anshuman Khandual 2021-03-02 10:21 ` Anshuman Khandual 2021-03-01 14:08 ` [PATCH v4.1 " Suzuki K Poulose 2021-03-01 14:08 ` Suzuki K Poulose 2021-03-08 17:26 ` [PATCH v4 " Mike Leach 2021-03-08 17:26 ` Mike Leach 2021-03-22 16:57 ` Suzuki K Poulose 2021-03-22 16:57 ` Suzuki K Poulose 2021-03-17 19:31 ` Mathieu Poirier 2021-03-17 19:31 ` Mathieu Poirier 2021-02-25 19:35 ` [PATCH v4 18/19] coresight: sink: Add TRBE driver Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose 2021-03-08 17:26 ` Mike Leach 2021-03-08 17:26 ` Mike Leach 2021-03-19 10:30 ` Suzuki K Poulose 2021-03-19 10:30 ` Suzuki K Poulose 2021-03-19 11:55 ` Mike Leach 2021-03-19 11:55 ` Mike Leach 2021-03-22 21:24 ` Mathieu Poirier 2021-03-22 21:24 ` Mathieu Poirier 2021-03-22 23:00 ` Suzuki K Poulose 2021-03-22 23:00 ` Suzuki K Poulose 2021-03-18 18:08 ` Mathieu Poirier 2021-03-18 18:08 ` Mathieu Poirier 2021-03-19 10:34 ` Suzuki K Poulose 2021-03-19 10:34 ` Suzuki K Poulose 2021-03-19 14:47 ` Mathieu Poirier 2021-03-19 14:47 ` Mathieu Poirier 2021-03-19 17:58 ` Mathieu Poirier 2021-03-19 17:58 ` Mathieu Poirier 2021-03-22 21:20 ` Mathieu Poirier 2021-03-22 21:20 ` Mathieu Poirier 2021-02-25 19:35 ` [PATCH v4 19/19] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose 2021-02-25 19:35 ` Suzuki K Poulose
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210225193543.2920532-2-suzuki.poulose@arm.com \ --to=suzuki.poulose@arm.com \ --cc=acme@kernel.org \ --cc=alexander.shishkin@linux.intel.com \ --cc=anshuman.khandual@arm.com \ --cc=jolsa@redhat.com \ --cc=leo.yan@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=mathieu.poirer@linaro.org \ --cc=mathieu.poirier@linaro.org \ --cc=mike.leach@linaro.org \ --cc=mingo@redhat.com \ --cc=peterz@infradead.org \ --cc=will@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.