From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: matthew.brost@intel.com, tvrtko.ursulin@intel.com, daniele.ceraolospurio@intel.com, jason.ekstrand@intel.com, jon.bloomfield@intel.com, daniel.vetter@intel.com, john.c.harrison@intel.com Subject: [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Date: Thu, 6 May 2021 12:13:41 -0700 [thread overview] Message-ID: <20210506191451.77768-28-matthew.brost@intel.com> (raw) In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> From: Michal Wajdeczko <michal.wajdeczko@intel.com> Format of the CTB messages has changed: - support for multiple formats - message fence is now part of the header - reuse of unified HXG message formats Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com> --- .../gt/uc/abi/guc_communication_ctb_abi.h | 56 +++++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 193 +++++++----------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 +- 3 files changed, 134 insertions(+), 117 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h index 127b256a662c..92660726c094 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h @@ -60,6 +60,62 @@ struct guc_ct_buffer_desc { } __packed; static_assert(sizeof(struct guc_ct_buffer_desc) == 64); +/** + * DOC: CTB Message + * + * +---+-------+--------------------------------------------------------------+ + * | | Bits | Description | + * +===+=======+==============================================================+ + * | 0 | 31:16 | **FENCE** - message identifier | + * | +-------+--------------------------------------------------------------+ + * | | 15:12 | **FORMAT** - format of the CTB message | + * | | | - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_ | + * | +-------+--------------------------------------------------------------+ + * | | 11:8 | **RESERVED** | + * | +-------+--------------------------------------------------------------+ + * | | 7:0 | **NUM_DWORDS** - length of the CTB message (w/o header) | + * +---+-------+--------------------------------------------------------------+ + * | 1 | 31:0 | optional (depends on FORMAT) | + * +---+-------+ | + * |...| | | + * +---+-------+ | + * | n | 31:0 | | + * +---+-------+--------------------------------------------------------------+ + */ + +#define GUC_CTB_MSG_MIN_LEN 1u +#define GUC_CTB_MSG_MAX_LEN 256u +#define GUC_CTB_MSG_0_FENCE (0xffff << 16) +#define GUC_CTB_MSG_0_FORMAT (0xf << 12) +#define GUC_CTB_FORMAT_HXG 0u +#define GUC_CTB_MSG_0_RESERVED (0xf << 8) +#define GUC_CTB_MSG_0_NUM_DWORDS (0xff << 0) + +/** + * DOC: CTB HXG Message + * + * +---+-------+--------------------------------------------------------------+ + * | | Bits | Description | + * +===+=======+==============================================================+ + * | 0 | 31:16 | FENCE | + * | +-------+--------------------------------------------------------------+ + * | | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ | + * | +-------+--------------------------------------------------------------+ + * | | 11:8 | RESERVED = MBZ | + * | +-------+--------------------------------------------------------------+ + * | | 7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message | + * +---+-------+--------------------------------------------------------------+ + * | 1 | 31:0 | +--------------------------------------------------------+ | + * +---+-------+ | | | + * |...| | | Embedded `HXG Message`_ | | + * +---+-------+ | | | + * | n | 31:0 | +--------------------------------------------------------+ | + * +---+-------+--------------------------------------------------------------+ + */ + +#define GUC_CTB_HXG_MSG_MIN_LEN (GUC_CTB_MSG_MIN_LEN + GUC_HXG_MSG_MIN_LEN) +#define GUC_CTB_HXG_MSG_MAX_LEN GUC_CTB_MSG_MAX_LEN + /** * DOC: CTB based communication * diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index e25b49a45107..217ab3ebd1af 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -343,24 +343,6 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct) return ++ct->requests.last_fence; } -/** - * DOC: CTB Host to GuC request - * - * Format of the CTB Host to GuC request message is as follows:: - * - * +------------+---------+---------+---------+---------+ - * | msg[0] | [1] | [2] | ... | [n-1] | - * +------------+---------+---------+---------+---------+ - * | MESSAGE | MESSAGE PAYLOAD | - * + HEADER +---------+---------+---------+---------+ - * | | 0 | 1 | ... | n | - * +============+=========+=========+=========+=========+ - * | len >= 1 | FENCE | request specific data | - * +------+-----+---------+---------+---------+---------+ - * - * ^-----------------len-------------------^ - */ - static int ct_write(struct intel_guc_ct *ct, const u32 *action, u32 len /* in dwords */, @@ -373,6 +355,7 @@ static int ct_write(struct intel_guc_ct *ct, u32 size = ctb->size; u32 used; u32 header; + u32 hxg; u32 *cmds = ctb->cmds; unsigned int i; @@ -403,22 +386,24 @@ static int ct_write(struct intel_guc_ct *ct, return -ENOSPC; /* - * Write the message. The format is the following: - * DW0: header (including action code) - * DW1: fence - * DW2+: action data + * dw0: CT header (including fence) + * dw1: HXG header */ - header = (len << GUC_CT_MSG_LEN_SHIFT) | - GUC_CT_MSG_SEND_STATUS | - (action[0] << GUC_CT_MSG_ACTION_SHIFT); + header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, GUC_CTB_FORMAT_HXG) | + FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) | + FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence); + + hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | + FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION | + GUC_HXG_REQUEST_MSG_0_DATA0, action[0]); - CT_DEBUG(ct, "writing %*ph %*ph %*ph\n", - 4, &header, 4, &fence, 4 * (len - 1), &action[1]); + CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); cmds[tail] = header; tail = (tail + 1) % size; - cmds[tail] = fence; + cmds[tail] = hxg; tail = (tail + 1) % size; for (i = 1; i < len; i++) { @@ -574,21 +559,6 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len, return ret; } -static inline unsigned int ct_header_get_len(u32 header) -{ - return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK; -} - -static inline unsigned int ct_header_get_action(u32 header) -{ - return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK; -} - -static inline bool ct_header_is_response(u32 header) -{ - return !!(header & GUC_CT_MSG_IS_RESPONSE); -} - static struct ct_incoming_msg *ct_alloc_msg(u32 num_dwords) { struct ct_incoming_msg *msg; @@ -651,7 +621,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) head = (head + 1) % size; /* message len with header */ - len = ct_header_get_len(header) + 1; + len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN; if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, @@ -694,55 +664,24 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) return -EPIPE; } -/** - * DOC: CTB GuC to Host response - * - * Format of the CTB GuC to Host response message is as follows:: - * - * +------------+---------+---------+---------+---------+---------+ - * | msg[0] | [1] | [2] | [3] | ... | [n-1] | - * +------------+---------+---------+---------+---------+---------+ - * | MESSAGE | MESSAGE PAYLOAD | - * + HEADER +---------+---------+---------+---------+---------+ - * | | 0 | 1 | 2 | ... | n | - * +============+=========+=========+=========+=========+=========+ - * | len >= 2 | FENCE | STATUS | response specific data | - * +------+-----+---------+---------+---------+---------+---------+ - * - * ^-----------------------len-----------------------^ - */ - static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *response) { - u32 header = response->msg[0]; - u32 len = ct_header_get_len(header); - u32 fence; - u32 status; - u32 datalen; + u32 len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, response->msg[0]); + u32 fence = FIELD_GET(GUC_CTB_MSG_0_FENCE, response->msg[0]); + const u32 *hxg = &response->msg[GUC_CTB_MSG_MIN_LEN]; + const u32 *data = &hxg[GUC_HXG_MSG_MIN_LEN]; + u32 datalen = len - GUC_HXG_MSG_MIN_LEN; struct ct_request *req; unsigned long flags; bool found = false; int err = 0; - GEM_BUG_ON(!ct_header_is_response(header)); + GEM_BUG_ON(len < GUC_HXG_MSG_MIN_LEN); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, hxg[0]) != GUC_HXG_ORIGIN_GUC); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_SUCCESS && + FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_FAILURE); - /* Response payload shall at least include fence and status */ - if (unlikely(len < 2)) { - CT_ERROR(ct, "Corrupted response (len %u)\n", len); - return -EPROTO; - } - - fence = response->msg[1]; - status = response->msg[2]; - datalen = len - 2; - - /* Format of the status dword follows HXG header */ - if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, status) != GUC_HXG_ORIGIN_GUC)) { - CT_ERROR(ct, "Corrupted response (status %#x)\n", status); - return -EPROTO; - } - - CT_DEBUG(ct, "response fence %u status %#x\n", fence, status); + CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]); spin_lock_irqsave(&ct->requests.lock, flags); list_for_each_entry(req, &ct->requests.pending, link) { @@ -758,9 +697,9 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r err = -EMSGSIZE; } if (datalen) - memcpy(req->response_buf, response->msg + 3, 4 * datalen); + memcpy(req->response_buf, data, 4 * datalen); req->response_len = datalen; - WRITE_ONCE(req->status, status); + WRITE_ONCE(req->status, hxg[0]); found = true; break; } @@ -781,14 +720,15 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *request) { struct intel_guc *guc = ct_to_guc(ct); - u32 header, action, len; + const u32 *hxg; const u32 *payload; + u32 action, len; int ret; - header = request->msg[0]; - payload = &request->msg[1]; - action = ct_header_get_action(header); - len = ct_header_get_len(header); + hxg = &request->msg[GUC_CTB_MSG_MIN_LEN]; + payload = &hxg[GUC_HXG_MSG_MIN_LEN]; + action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]); + len = request->size - GUC_CTB_HXG_MSG_MIN_LEN; CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload); @@ -850,29 +790,12 @@ static void ct_incoming_request_worker_func(struct work_struct *w) queue_work(system_unbound_wq, &ct->requests.worker); } -/** - * DOC: CTB GuC to Host request - * - * Format of the CTB GuC to Host request message is as follows:: - * - * +------------+---------+---------+---------+---------+---------+ - * | msg[0] | [1] | [2] | [3] | ... | [n-1] | - * +------------+---------+---------+---------+---------+---------+ - * | MESSAGE | MESSAGE PAYLOAD | - * + HEADER +---------+---------+---------+---------+---------+ - * | | 0 | 1 | 2 | ... | n | - * +============+=========+=========+=========+=========+=========+ - * | len | request specific data | - * +------+-----+---------+---------+---------+---------+---------+ - * - * ^-----------------------len-----------------------^ - */ - -static int ct_handle_request(struct intel_guc_ct *ct, struct ct_incoming_msg *request) +static int ct_handle_event(struct intel_guc_ct *ct, struct ct_incoming_msg *request) { + const u32 *hxg = &request->msg[GUC_CTB_MSG_MIN_LEN]; unsigned long flags; - GEM_BUG_ON(ct_header_is_response(request->msg[0])); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_EVENT); spin_lock_irqsave(&ct->requests.lock, flags); list_add_tail(&request->link, &ct->requests.incoming); @@ -882,15 +805,53 @@ static int ct_handle_request(struct intel_guc_ct *ct, struct ct_incoming_msg *re return 0; } -static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg) +static int ct_handle_hxg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg) { - u32 header = msg->msg[0]; + u32 origin, type; + u32 *hxg; int err; - if (ct_header_is_response(header)) + if (unlikely(msg->size < GUC_CTB_HXG_MSG_MIN_LEN)) + return -EBADMSG; + + hxg = &msg->msg[GUC_CTB_MSG_MIN_LEN]; + + origin = FIELD_GET(GUC_HXG_MSG_0_ORIGIN, hxg[0]); + if (unlikely(origin != GUC_HXG_ORIGIN_GUC)) { + err = -EPROTO; + goto failed; + } + + type = FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]); + switch (type) { + case GUC_HXG_TYPE_EVENT: + err = ct_handle_event(ct, msg); + break; + case GUC_HXG_TYPE_RESPONSE_SUCCESS: + case GUC_HXG_TYPE_RESPONSE_FAILURE: err = ct_handle_response(ct, msg); + break; + default: + err = -EOPNOTSUPP; + } + + if (unlikely(err)) { +failed: + CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n", + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg); + } + return err; +} + +static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg) +{ + u32 format = FIELD_GET(GUC_CTB_MSG_0_FORMAT, msg->msg[0]); + int err; + + if (format == GUC_CTB_FORMAT_HXG) + err = ct_handle_hxg(ct, msg); else - err = ct_handle_request(ct, msg); + err = -EOPNOTSUPP; if (unlikely(err)) { CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n", diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index 905202caaad3..1ae2dde6db93 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -61,7 +61,7 @@ struct intel_guc_ct { struct tasklet_struct receive_tasklet; struct { - u32 last_fence; /* last fence used to send request */ + u16 last_fence; /* last fence used to send request */ spinlock_t lock; /* protects pending requests list */ struct list_head pending; /* requests waiting for response */ -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Date: Thu, 6 May 2021 12:13:41 -0700 [thread overview] Message-ID: <20210506191451.77768-28-matthew.brost@intel.com> (raw) In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> From: Michal Wajdeczko <michal.wajdeczko@intel.com> Format of the CTB messages has changed: - support for multiple formats - message fence is now part of the header - reuse of unified HXG message formats Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com> --- .../gt/uc/abi/guc_communication_ctb_abi.h | 56 +++++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 193 +++++++----------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 +- 3 files changed, 134 insertions(+), 117 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h index 127b256a662c..92660726c094 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h @@ -60,6 +60,62 @@ struct guc_ct_buffer_desc { } __packed; static_assert(sizeof(struct guc_ct_buffer_desc) == 64); +/** + * DOC: CTB Message + * + * +---+-------+--------------------------------------------------------------+ + * | | Bits | Description | + * +===+=======+==============================================================+ + * | 0 | 31:16 | **FENCE** - message identifier | + * | +-------+--------------------------------------------------------------+ + * | | 15:12 | **FORMAT** - format of the CTB message | + * | | | - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_ | + * | +-------+--------------------------------------------------------------+ + * | | 11:8 | **RESERVED** | + * | +-------+--------------------------------------------------------------+ + * | | 7:0 | **NUM_DWORDS** - length of the CTB message (w/o header) | + * +---+-------+--------------------------------------------------------------+ + * | 1 | 31:0 | optional (depends on FORMAT) | + * +---+-------+ | + * |...| | | + * +---+-------+ | + * | n | 31:0 | | + * +---+-------+--------------------------------------------------------------+ + */ + +#define GUC_CTB_MSG_MIN_LEN 1u +#define GUC_CTB_MSG_MAX_LEN 256u +#define GUC_CTB_MSG_0_FENCE (0xffff << 16) +#define GUC_CTB_MSG_0_FORMAT (0xf << 12) +#define GUC_CTB_FORMAT_HXG 0u +#define GUC_CTB_MSG_0_RESERVED (0xf << 8) +#define GUC_CTB_MSG_0_NUM_DWORDS (0xff << 0) + +/** + * DOC: CTB HXG Message + * + * +---+-------+--------------------------------------------------------------+ + * | | Bits | Description | + * +===+=======+==============================================================+ + * | 0 | 31:16 | FENCE | + * | +-------+--------------------------------------------------------------+ + * | | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ | + * | +-------+--------------------------------------------------------------+ + * | | 11:8 | RESERVED = MBZ | + * | +-------+--------------------------------------------------------------+ + * | | 7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message | + * +---+-------+--------------------------------------------------------------+ + * | 1 | 31:0 | +--------------------------------------------------------+ | + * +---+-------+ | | | + * |...| | | Embedded `HXG Message`_ | | + * +---+-------+ | | | + * | n | 31:0 | +--------------------------------------------------------+ | + * +---+-------+--------------------------------------------------------------+ + */ + +#define GUC_CTB_HXG_MSG_MIN_LEN (GUC_CTB_MSG_MIN_LEN + GUC_HXG_MSG_MIN_LEN) +#define GUC_CTB_HXG_MSG_MAX_LEN GUC_CTB_MSG_MAX_LEN + /** * DOC: CTB based communication * diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index e25b49a45107..217ab3ebd1af 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -343,24 +343,6 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct) return ++ct->requests.last_fence; } -/** - * DOC: CTB Host to GuC request - * - * Format of the CTB Host to GuC request message is as follows:: - * - * +------------+---------+---------+---------+---------+ - * | msg[0] | [1] | [2] | ... | [n-1] | - * +------------+---------+---------+---------+---------+ - * | MESSAGE | MESSAGE PAYLOAD | - * + HEADER +---------+---------+---------+---------+ - * | | 0 | 1 | ... | n | - * +============+=========+=========+=========+=========+ - * | len >= 1 | FENCE | request specific data | - * +------+-----+---------+---------+---------+---------+ - * - * ^-----------------len-------------------^ - */ - static int ct_write(struct intel_guc_ct *ct, const u32 *action, u32 len /* in dwords */, @@ -373,6 +355,7 @@ static int ct_write(struct intel_guc_ct *ct, u32 size = ctb->size; u32 used; u32 header; + u32 hxg; u32 *cmds = ctb->cmds; unsigned int i; @@ -403,22 +386,24 @@ static int ct_write(struct intel_guc_ct *ct, return -ENOSPC; /* - * Write the message. The format is the following: - * DW0: header (including action code) - * DW1: fence - * DW2+: action data + * dw0: CT header (including fence) + * dw1: HXG header */ - header = (len << GUC_CT_MSG_LEN_SHIFT) | - GUC_CT_MSG_SEND_STATUS | - (action[0] << GUC_CT_MSG_ACTION_SHIFT); + header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, GUC_CTB_FORMAT_HXG) | + FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) | + FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence); + + hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | + FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION | + GUC_HXG_REQUEST_MSG_0_DATA0, action[0]); - CT_DEBUG(ct, "writing %*ph %*ph %*ph\n", - 4, &header, 4, &fence, 4 * (len - 1), &action[1]); + CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", + tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); cmds[tail] = header; tail = (tail + 1) % size; - cmds[tail] = fence; + cmds[tail] = hxg; tail = (tail + 1) % size; for (i = 1; i < len; i++) { @@ -574,21 +559,6 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len, return ret; } -static inline unsigned int ct_header_get_len(u32 header) -{ - return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK; -} - -static inline unsigned int ct_header_get_action(u32 header) -{ - return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK; -} - -static inline bool ct_header_is_response(u32 header) -{ - return !!(header & GUC_CT_MSG_IS_RESPONSE); -} - static struct ct_incoming_msg *ct_alloc_msg(u32 num_dwords) { struct ct_incoming_msg *msg; @@ -651,7 +621,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) head = (head + 1) % size; /* message len with header */ - len = ct_header_get_len(header) + 1; + len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN; if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, @@ -694,55 +664,24 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) return -EPIPE; } -/** - * DOC: CTB GuC to Host response - * - * Format of the CTB GuC to Host response message is as follows:: - * - * +------------+---------+---------+---------+---------+---------+ - * | msg[0] | [1] | [2] | [3] | ... | [n-1] | - * +------------+---------+---------+---------+---------+---------+ - * | MESSAGE | MESSAGE PAYLOAD | - * + HEADER +---------+---------+---------+---------+---------+ - * | | 0 | 1 | 2 | ... | n | - * +============+=========+=========+=========+=========+=========+ - * | len >= 2 | FENCE | STATUS | response specific data | - * +------+-----+---------+---------+---------+---------+---------+ - * - * ^-----------------------len-----------------------^ - */ - static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *response) { - u32 header = response->msg[0]; - u32 len = ct_header_get_len(header); - u32 fence; - u32 status; - u32 datalen; + u32 len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, response->msg[0]); + u32 fence = FIELD_GET(GUC_CTB_MSG_0_FENCE, response->msg[0]); + const u32 *hxg = &response->msg[GUC_CTB_MSG_MIN_LEN]; + const u32 *data = &hxg[GUC_HXG_MSG_MIN_LEN]; + u32 datalen = len - GUC_HXG_MSG_MIN_LEN; struct ct_request *req; unsigned long flags; bool found = false; int err = 0; - GEM_BUG_ON(!ct_header_is_response(header)); + GEM_BUG_ON(len < GUC_HXG_MSG_MIN_LEN); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, hxg[0]) != GUC_HXG_ORIGIN_GUC); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_SUCCESS && + FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_RESPONSE_FAILURE); - /* Response payload shall at least include fence and status */ - if (unlikely(len < 2)) { - CT_ERROR(ct, "Corrupted response (len %u)\n", len); - return -EPROTO; - } - - fence = response->msg[1]; - status = response->msg[2]; - datalen = len - 2; - - /* Format of the status dword follows HXG header */ - if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, status) != GUC_HXG_ORIGIN_GUC)) { - CT_ERROR(ct, "Corrupted response (status %#x)\n", status); - return -EPROTO; - } - - CT_DEBUG(ct, "response fence %u status %#x\n", fence, status); + CT_DEBUG(ct, "response fence %u status %#x\n", fence, hxg[0]); spin_lock_irqsave(&ct->requests.lock, flags); list_for_each_entry(req, &ct->requests.pending, link) { @@ -758,9 +697,9 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r err = -EMSGSIZE; } if (datalen) - memcpy(req->response_buf, response->msg + 3, 4 * datalen); + memcpy(req->response_buf, data, 4 * datalen); req->response_len = datalen; - WRITE_ONCE(req->status, status); + WRITE_ONCE(req->status, hxg[0]); found = true; break; } @@ -781,14 +720,15 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *request) { struct intel_guc *guc = ct_to_guc(ct); - u32 header, action, len; + const u32 *hxg; const u32 *payload; + u32 action, len; int ret; - header = request->msg[0]; - payload = &request->msg[1]; - action = ct_header_get_action(header); - len = ct_header_get_len(header); + hxg = &request->msg[GUC_CTB_MSG_MIN_LEN]; + payload = &hxg[GUC_HXG_MSG_MIN_LEN]; + action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, hxg[0]); + len = request->size - GUC_CTB_HXG_MSG_MIN_LEN; CT_DEBUG(ct, "request %x %*ph\n", action, 4 * len, payload); @@ -850,29 +790,12 @@ static void ct_incoming_request_worker_func(struct work_struct *w) queue_work(system_unbound_wq, &ct->requests.worker); } -/** - * DOC: CTB GuC to Host request - * - * Format of the CTB GuC to Host request message is as follows:: - * - * +------------+---------+---------+---------+---------+---------+ - * | msg[0] | [1] | [2] | [3] | ... | [n-1] | - * +------------+---------+---------+---------+---------+---------+ - * | MESSAGE | MESSAGE PAYLOAD | - * + HEADER +---------+---------+---------+---------+---------+ - * | | 0 | 1 | 2 | ... | n | - * +============+=========+=========+=========+=========+=========+ - * | len | request specific data | - * +------+-----+---------+---------+---------+---------+---------+ - * - * ^-----------------------len-----------------------^ - */ - -static int ct_handle_request(struct intel_guc_ct *ct, struct ct_incoming_msg *request) +static int ct_handle_event(struct intel_guc_ct *ct, struct ct_incoming_msg *request) { + const u32 *hxg = &request->msg[GUC_CTB_MSG_MIN_LEN]; unsigned long flags; - GEM_BUG_ON(ct_header_is_response(request->msg[0])); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]) != GUC_HXG_TYPE_EVENT); spin_lock_irqsave(&ct->requests.lock, flags); list_add_tail(&request->link, &ct->requests.incoming); @@ -882,15 +805,53 @@ static int ct_handle_request(struct intel_guc_ct *ct, struct ct_incoming_msg *re return 0; } -static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg) +static int ct_handle_hxg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg) { - u32 header = msg->msg[0]; + u32 origin, type; + u32 *hxg; int err; - if (ct_header_is_response(header)) + if (unlikely(msg->size < GUC_CTB_HXG_MSG_MIN_LEN)) + return -EBADMSG; + + hxg = &msg->msg[GUC_CTB_MSG_MIN_LEN]; + + origin = FIELD_GET(GUC_HXG_MSG_0_ORIGIN, hxg[0]); + if (unlikely(origin != GUC_HXG_ORIGIN_GUC)) { + err = -EPROTO; + goto failed; + } + + type = FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg[0]); + switch (type) { + case GUC_HXG_TYPE_EVENT: + err = ct_handle_event(ct, msg); + break; + case GUC_HXG_TYPE_RESPONSE_SUCCESS: + case GUC_HXG_TYPE_RESPONSE_FAILURE: err = ct_handle_response(ct, msg); + break; + default: + err = -EOPNOTSUPP; + } + + if (unlikely(err)) { +failed: + CT_ERROR(ct, "Failed to handle HXG message (%pe) %*ph\n", + ERR_PTR(err), 4 * GUC_HXG_MSG_MIN_LEN, hxg); + } + return err; +} + +static void ct_handle_msg(struct intel_guc_ct *ct, struct ct_incoming_msg *msg) +{ + u32 format = FIELD_GET(GUC_CTB_MSG_0_FORMAT, msg->msg[0]); + int err; + + if (format == GUC_CTB_FORMAT_HXG) + err = ct_handle_hxg(ct, msg); else - err = ct_handle_request(ct, msg); + err = -EOPNOTSUPP; if (unlikely(err)) { CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n", diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index 905202caaad3..1ae2dde6db93 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -61,7 +61,7 @@ struct intel_guc_ct { struct tasklet_struct receive_tasklet; struct { - u32 last_fence; /* last fence used to send request */ + u16 last_fence; /* last fence used to send request */ spinlock_t lock; /* protects pending requests list */ struct list_head pending; /* requests waiting for response */ -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-06 18:58 UTC|newest] Thread overview: 504+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-06 19:13 [RFC PATCH 00/97] Basic GuC submission support in the i915 Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2021-05-06 19:13 ` [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 0:25 ` Matthew Brost 2021-05-19 0:25 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 3:10 ` Matthew Brost 2021-05-19 3:10 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 3:31 ` Matthew Brost 2021-05-19 3:31 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:45 ` Tvrtko Ursulin 2021-05-25 8:45 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-20 16:47 ` Matthew Brost 2021-05-20 16:47 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 10:30 ` Michal Wajdeczko 2021-05-24 10:30 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 0:31 ` Matthew Brost 2021-05-25 0:31 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 10:48 ` Michal Wajdeczko 2021-05-24 10:48 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 0:36 ` Matthew Brost 2021-05-25 0:36 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 23:52 ` Michał Winiarski 2021-05-24 23:52 ` [Intel-gfx] " Michał Winiarski 2021-05-06 19:13 ` [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:38 ` Matthew Brost 2021-05-25 2:38 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 0:42 ` Matthew Brost 2021-05-25 0:42 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:47 ` Matthew Brost 2021-05-25 2:47 ` [Intel-gfx] " Matthew Brost 2021-05-25 12:48 ` Michal Wajdeczko 2021-05-25 12:48 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:53 ` Matthew Brost 2021-05-25 2:53 ` [Intel-gfx] " Matthew Brost 2021-05-25 13:07 ` Michal Wajdeczko 2021-05-25 13:07 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 16:56 ` Matthew Brost 2021-05-25 16:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 3:15 ` Matthew Brost 2021-05-25 3:15 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:56 ` Matthew Brost 2021-05-25 2:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:08 ` Matthew Brost 2021-05-25 18:08 ` [Intel-gfx] " Matthew Brost 2021-05-25 19:37 ` Michal Wajdeczko 2021-05-25 19:37 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 3:21 ` Matthew Brost 2021-05-25 3:21 ` [Intel-gfx] " Matthew Brost 2021-05-25 13:10 ` Michal Wajdeczko 2021-05-25 3:21 ` Matthew Brost 2021-05-25 3:21 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 16:14 ` Matthew Brost 2021-05-25 16:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:15 ` Matthew Brost 2021-05-25 18:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 19:43 ` Michal Wajdeczko 2021-05-25 19:43 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:25 ` Matthew Brost 2021-05-25 18:25 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:16 ` Daniel Vetter 2021-05-11 15:16 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:59 ` Matthew Brost 2021-05-11 17:59 ` [Intel-gfx] " Matthew Brost 2021-05-11 22:11 ` Michal Wajdeczko 2021-05-11 22:11 ` [Intel-gfx] " Michal Wajdeczko 2021-05-12 8:40 ` Daniel Vetter 2021-05-12 8:40 ` [Intel-gfx] " Daniel Vetter 2021-05-06 19:13 ` [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 22/97] drm/i915/guc: Update CTB response status Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 1:15 ` Matthew Brost 2021-05-25 1:15 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-27 19:44 ` Matthew Brost 2021-05-27 19:44 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` Matthew Brost [this message] 2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 1:01 ` Matthew Brost 2021-05-25 1:01 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2 Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 11:00 ` Michal Wajdeczko 2021-05-24 11:00 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-26 20:28 ` Matthew Brost 2021-05-26 20:28 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:18 ` Daniel Vetter 2021-05-11 15:18 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:56 ` Matthew Brost 2021-05-11 17:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 33/97] drm/i915: Engine relative MMIO Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:05 ` Tvrtko Ursulin 2021-05-25 9:05 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-26 20:41 ` Matthew Brost 2021-05-26 20:41 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 11:59 ` Michal Wajdeczko 2021-05-24 11:59 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:32 ` Matthew Brost 2021-05-25 17:32 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 12:21 ` Michal Wajdeczko 2021-05-24 12:21 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:30 ` Matthew Brost 2021-05-25 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:21 ` Tvrtko Ursulin 2021-05-25 9:21 ` Tvrtko Ursulin 2021-05-25 17:21 ` Matthew Brost 2021-05-25 17:21 ` Matthew Brost 2021-05-26 8:57 ` Tvrtko Ursulin 2021-05-26 8:57 ` Tvrtko Ursulin 2021-05-26 18:10 ` Matthew Brost 2021-05-26 18:10 ` Matthew Brost 2021-05-27 10:02 ` Tvrtko Ursulin 2021-05-27 10:02 ` Tvrtko Ursulin 2021-05-27 14:35 ` Matthew Brost 2021-05-27 14:35 ` Matthew Brost 2021-05-27 15:11 ` Tvrtko Ursulin 2021-05-27 15:11 ` Tvrtko Ursulin 2021-06-07 17:31 ` Matthew Brost 2021-06-07 17:31 ` Matthew Brost 2021-06-08 8:39 ` Tvrtko Ursulin 2021-06-08 8:39 ` Tvrtko Ursulin 2021-06-08 8:46 ` Daniel Vetter 2021-06-08 8:46 ` Daniel Vetter 2021-06-09 23:10 ` Matthew Brost 2021-06-09 23:10 ` Matthew Brost 2021-06-10 15:27 ` Daniel Vetter 2021-06-10 15:27 ` Daniel Vetter 2021-06-24 16:38 ` Matthew Brost 2021-06-24 16:38 ` Matthew Brost 2021-06-24 17:25 ` Daniel Vetter 2021-06-24 17:25 ` Daniel Vetter 2021-06-09 13:58 ` Michal Wajdeczko 2021-06-09 13:58 ` Michal Wajdeczko 2021-06-09 23:05 ` Matthew Brost 2021-06-09 23:05 ` Matthew Brost 2021-06-09 14:14 ` Michal Wajdeczko 2021-06-09 14:14 ` Michal Wajdeczko 2021-06-09 23:13 ` Matthew Brost 2021-06-09 23:13 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 37/97] drm/i915/guc: Add stall timer to " Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 12:58 ` Michal Wajdeczko 2021-05-24 12:58 ` [Intel-gfx] " Michal Wajdeczko 2021-05-24 18:35 ` Matthew Brost 2021-05-24 18:35 ` [Intel-gfx] " Matthew Brost 2021-05-25 14:15 ` Michal Wajdeczko 2021-05-25 14:15 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 16:54 ` Matthew Brost 2021-05-25 16:54 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:31 ` Michal Wajdeczko 2021-05-24 13:31 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:39 ` Matthew Brost 2021-05-25 17:39 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:43 ` Michal Wajdeczko 2021-05-24 13:43 ` Michal Wajdeczko 2021-05-24 18:40 ` Matthew Brost 2021-05-24 18:40 ` Matthew Brost 2021-05-25 9:24 ` Tvrtko Ursulin 2021-05-25 9:24 ` Tvrtko Ursulin 2021-05-25 17:15 ` Matthew Brost 2021-05-25 17:15 ` Matthew Brost 2021-05-26 9:30 ` Tvrtko Ursulin 2021-05-26 9:30 ` Tvrtko Ursulin 2021-05-26 18:20 ` Matthew Brost 2021-05-26 18:20 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:45 ` Michal Wajdeczko 2021-05-24 13:45 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:26 ` Daniel Vetter 2021-05-11 15:26 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:01 ` Matthew Brost 2021-05-11 17:01 ` [Intel-gfx] " Matthew Brost 2021-05-11 17:43 ` Daniel Vetter 2021-05-11 17:43 ` [Intel-gfx] " Daniel Vetter 2021-05-11 19:34 ` Matthew Brost 2021-05-11 19:34 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:43 ` Tvrtko Ursulin 2021-05-25 9:43 ` Tvrtko Ursulin 2021-05-25 17:10 ` Matthew Brost 2021-05-25 17:10 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-29 20:32 ` Michal Wajdeczko 2021-05-29 20:32 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:14 ` [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:37 ` Daniel Vetter 2021-05-11 15:37 ` [Intel-gfx] " Daniel Vetter 2021-05-11 16:31 ` Matthew Brost 2021-05-11 16:31 ` [Intel-gfx] " Matthew Brost 2021-05-26 10:26 ` Tvrtko Ursulin 2021-05-26 10:26 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:52 ` Tvrtko Ursulin 2021-05-25 9:52 ` Tvrtko Ursulin 2021-05-25 17:01 ` Matthew Brost 2021-05-25 17:01 ` Matthew Brost 2021-05-26 9:25 ` Tvrtko Ursulin 2021-05-26 9:25 ` Tvrtko Ursulin 2021-05-26 18:15 ` Matthew Brost 2021-05-26 18:15 ` Matthew Brost 2021-05-27 8:41 ` Tvrtko Ursulin 2021-05-27 8:41 ` Tvrtko Ursulin 2021-05-27 14:38 ` Matthew Brost 2021-05-27 14:38 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-07 5:56 ` kernel test robot 2021-05-25 10:06 ` Tvrtko Ursulin 2021-05-25 10:06 ` Tvrtko Ursulin 2021-05-25 17:07 ` Matthew Brost 2021-05-25 17:07 ` Matthew Brost 2021-05-26 9:21 ` Tvrtko Ursulin 2021-05-26 9:21 ` Tvrtko Ursulin 2021-05-26 18:18 ` Matthew Brost 2021-05-26 18:18 ` Matthew Brost 2021-05-27 9:02 ` Tvrtko Ursulin 2021-05-27 9:02 ` Tvrtko Ursulin 2021-05-27 14:37 ` Matthew Brost 2021-05-27 14:37 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 57/97] drm/i915/guc: Add several request trace points Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 58/97] drm/i915: Add intel_context tracing Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 60/97] drm/i915: Track 'serial' counts for " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-25 10:16 ` Tvrtko Ursulin 2021-05-25 10:16 ` Tvrtko Ursulin 2021-05-25 17:52 ` Matthew Brost 2021-05-25 17:52 ` Matthew Brost 2021-05-26 8:40 ` Tvrtko Ursulin 2021-05-26 8:40 ` Tvrtko Ursulin 2021-05-26 18:45 ` John Harrison 2021-05-26 18:45 ` John Harrison 2021-05-27 8:53 ` Tvrtko Ursulin 2021-05-27 8:53 ` Tvrtko Ursulin 2021-05-27 17:01 ` John Harrison 2021-05-27 17:01 ` John Harrison 2021-06-01 9:31 ` Tvrtko Ursulin 2021-06-01 9:31 ` Tvrtko Ursulin 2021-06-02 1:20 ` John Harrison 2021-06-02 1:20 ` John Harrison 2021-06-02 12:04 ` Tvrtko Ursulin 2021-06-02 12:04 ` Tvrtko Ursulin 2021-06-02 12:09 ` Tvrtko Ursulin 2021-06-02 12:09 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 12:18 ` Tvrtko Ursulin 2021-06-02 12:18 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 13:31 ` Tvrtko Ursulin 2021-06-02 13:31 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 14:33 ` Tvrtko Ursulin 2021-06-02 14:33 ` Tvrtko Ursulin 2021-06-04 3:17 ` Matthew Brost 2021-06-04 3:17 ` Matthew Brost 2021-06-04 8:16 ` Daniel Vetter 2021-06-04 8:16 ` Daniel Vetter 2021-06-04 18:02 ` Matthew Brost 2021-06-04 18:02 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 14:36 ` Tvrtko Ursulin 2021-06-02 14:36 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 8:16 ` [drm/i915/guc] 07336fb545: WARNING:at_drivers/gpu/drm/i915/gt/uc/intel_uc.c:#__uc_sanitize[i915] kernel test robot 2021-05-11 8:16 ` kernel test robot 2021-05-11 8:16 ` [Intel-gfx] " kernel test robot 2021-05-11 8:16 ` kernel test robot 2021-05-06 19:14 ` [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 16:25 ` Daniel Vetter 2021-05-11 16:25 ` Daniel Vetter 2021-05-06 19:14 ` [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 16:28 ` Daniel Vetter 2021-05-11 16:28 ` Daniel Vetter 2021-05-11 17:12 ` Matthew Brost 2021-05-11 17:12 ` Matthew Brost 2021-05-11 17:45 ` Daniel Vetter 2021-05-11 17:45 ` Daniel Vetter 2021-05-06 19:14 ` [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-07 6:06 ` kernel test robot 2021-05-06 19:14 ` [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 88/97] drm/i915/guc: Support request cancellation Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-09 17:12 ` [RFC PATCH 00/97] Basic GuC submission support in the i915 Martin Peres 2021-05-09 17:12 ` [Intel-gfx] " Martin Peres 2021-05-09 23:11 ` Jason Ekstrand 2021-05-09 23:11 ` [Intel-gfx] " Jason Ekstrand 2021-05-10 13:55 ` Martin Peres 2021-05-10 13:55 ` [Intel-gfx] " Martin Peres 2021-05-10 16:25 ` Jason Ekstrand 2021-05-10 16:25 ` [Intel-gfx] " Jason Ekstrand 2021-05-11 8:01 ` Martin Peres 2021-05-11 8:01 ` [Intel-gfx] " Martin Peres 2021-05-10 16:33 ` Daniel Vetter 2021-05-10 16:33 ` [Intel-gfx] " Daniel Vetter 2021-05-10 18:30 ` Francisco Jerez 2021-05-10 18:30 ` Francisco Jerez 2021-05-11 8:06 ` Martin Peres 2021-05-11 8:06 ` [Intel-gfx] " Martin Peres 2021-05-11 15:26 ` Bloomfield, Jon 2021-05-11 15:26 ` [Intel-gfx] " Bloomfield, Jon 2021-05-11 16:39 ` Matthew Brost 2021-05-11 16:39 ` [Intel-gfx] " Matthew Brost 2021-05-12 6:26 ` Martin Peres 2021-05-12 6:26 ` [Intel-gfx] " Martin Peres 2021-05-14 16:31 ` Jason Ekstrand 2021-05-14 16:31 ` [Intel-gfx] " Jason Ekstrand 2021-05-25 15:37 ` Alex Deucher 2021-05-25 15:37 ` [Intel-gfx] " Alex Deucher 2021-05-11 2:58 ` Dixit, Ashutosh 2021-05-11 2:58 ` [Intel-gfx] " Dixit, Ashutosh 2021-05-11 7:47 ` Martin Peres 2021-05-11 7:47 ` [Intel-gfx] " Martin Peres 2021-05-14 11:11 ` Tvrtko Ursulin 2021-05-14 11:11 ` Tvrtko Ursulin 2021-05-14 16:36 ` Jason Ekstrand 2021-05-14 16:36 ` Jason Ekstrand 2021-05-14 16:46 ` Matthew Brost 2021-05-14 16:46 ` Matthew Brost 2021-05-14 16:41 ` Matthew Brost 2021-05-14 16:41 ` Matthew Brost 2021-05-25 10:32 ` Tvrtko Ursulin 2021-05-25 10:32 ` Tvrtko Ursulin 2021-05-25 16:45 ` Matthew Brost 2021-05-25 16:45 ` Matthew Brost 2021-06-02 15:27 ` Tvrtko Ursulin 2021-06-02 15:27 ` Tvrtko Ursulin 2021-06-02 18:57 ` Daniel Vetter 2021-06-02 18:57 ` Daniel Vetter 2021-06-03 3:41 ` Matthew Brost 2021-06-03 3:41 ` Matthew Brost 2021-06-03 4:47 ` Daniel Vetter 2021-06-03 4:47 ` Daniel Vetter 2021-06-03 9:49 ` Tvrtko Ursulin 2021-06-03 9:49 ` Tvrtko Ursulin 2021-06-03 10:52 ` Tvrtko Ursulin 2021-06-03 10:52 ` Tvrtko Ursulin 2021-06-03 4:10 ` Matthew Brost 2021-06-03 4:10 ` Matthew Brost 2021-06-03 8:51 ` Tvrtko Ursulin 2021-06-03 8:51 ` Tvrtko Ursulin 2021-06-03 16:34 ` Matthew Brost 2021-06-03 16:34 ` Matthew Brost
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