From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniel.vetter@ffwll.ch> Subject: [PATCH 12/22] drm/i915/guc: Don't touch guc_state.sched_state without a lock Date: Mon, 16 Aug 2021 06:51:29 -0700 [thread overview] Message-ID: <20210816135139.10060-13-matthew.brost@intel.com> (raw) In-Reply-To: <20210816135139.10060-1-matthew.brost@intel.com> Before we did some clever tricks to not use the a lock when touching guc_state.sched_state in certain cases. Don't do that, enforce the use of the lock. Part of this is removing a dead code path from guc_lrc_desc_pin where a context could be deregistered when the aforementioned function was called from the submission path. Remove this dead code and add a GEM_BUG_ON if this path is ever attempted to be used. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 57 ++++++++++--------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 89126be26786..8d45585773f3 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -150,11 +150,22 @@ static inline void clr_context_registered(struct intel_context *ce) #define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT) static inline void init_sched_state(struct intel_context *ce) { - /* Only should be called from guc_lrc_desc_pin() */ + lockdep_assert_held(&ce->guc_state.lock); atomic_set(&ce->guc_sched_state_no_lock, 0); ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK; } +static inline bool sched_state_is_init(struct intel_context *ce) +{ + /* + * XXX: Kernel contexts can have SCHED_STATE_NO_LOCK_REGISTERED after + * suspend. + */ + return !(atomic_read(&ce->guc_sched_state_no_lock) & + ~SCHED_STATE_NO_LOCK_REGISTERED) && + !(ce->guc_state.sched_state &= ~SCHED_STATE_BLOCKED_MASK); +} + static inline bool context_wait_for_deregister_to_register(struct intel_context *ce) { @@ -165,7 +176,7 @@ context_wait_for_deregister_to_register(struct intel_context *ce) static inline void set_context_wait_for_deregister_to_register(struct intel_context *ce) { - /* Only should be called from guc_lrc_desc_pin() without lock */ + lockdep_assert_held(&ce->guc_state.lock); ce->guc_state.sched_state |= SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER; } @@ -599,9 +610,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc) bool pending_disable, pending_enable, deregister, destroyed, banned; xa_for_each(&guc->context_lookup, index, ce) { - /* Flush context */ spin_lock_irqsave(&ce->guc_state.lock, flags); - spin_unlock_irqrestore(&ce->guc_state.lock, flags); /* * Once we are at this point submission_disabled() is guaranteed @@ -617,6 +626,8 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc) banned = context_banned(ce); init_sched_state(ce); + spin_unlock_irqrestore(&ce->guc_state.lock, flags); + if (pending_enable || destroyed || deregister) { atomic_dec(&guc->outstanding_submission_g2h); if (deregister) @@ -1318,6 +1329,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) int ret = 0; GEM_BUG_ON(!engine->mask); + GEM_BUG_ON(!sched_state_is_init(ce)); /* * Ensure LRC + CT vmas are is same region as write barrier is done @@ -1346,7 +1358,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) desc->priority = ce->guc_prio; desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD; guc_context_policy_init(engine, desc); - init_sched_state(ce); /* * The context_lookup xarray is used to determine if the hardware @@ -1357,26 +1368,23 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) * registering this context. */ if (context_registered) { + bool disabled; + unsigned long flags; + trace_intel_context_steal_guc_id(ce); - if (!loop) { + GEM_BUG_ON(!loop); + + /* Seal race with Reset */ + spin_lock_irqsave(&ce->guc_state.lock, flags); + disabled = submission_disabled(guc); + if (likely(!disabled)) { set_context_wait_for_deregister_to_register(ce); intel_context_get(ce); - } else { - bool disabled; - unsigned long flags; - - /* Seal race with Reset */ - spin_lock_irqsave(&ce->guc_state.lock, flags); - disabled = submission_disabled(guc); - if (likely(!disabled)) { - set_context_wait_for_deregister_to_register(ce); - intel_context_get(ce); - } - spin_unlock_irqrestore(&ce->guc_state.lock, flags); - if (unlikely(disabled)) { - reset_lrc_desc(guc, desc_idx); - return 0; /* Will get registered later */ - } + } + spin_unlock_irqrestore(&ce->guc_state.lock, flags); + if (unlikely(disabled)) { + reset_lrc_desc(guc, desc_idx); + return 0; /* Will get registered later */ } /* @@ -1385,10 +1393,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) */ with_intel_runtime_pm(runtime_pm, wakeref) ret = deregister_context(ce, ce->guc_id, loop); - if (unlikely(ret == -EBUSY)) { - clr_context_wait_for_deregister_to_register(ce); - intel_context_put(ce); - } else if (unlikely(ret == -ENODEV)) { + if (unlikely(ret == -ENODEV)) { ret = 0; /* Will get registered later */ } } else { -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniel.vetter@ffwll.ch> Subject: [Intel-gfx] [PATCH 12/22] drm/i915/guc: Don't touch guc_state.sched_state without a lock Date: Mon, 16 Aug 2021 06:51:29 -0700 [thread overview] Message-ID: <20210816135139.10060-13-matthew.brost@intel.com> (raw) In-Reply-To: <20210816135139.10060-1-matthew.brost@intel.com> Before we did some clever tricks to not use the a lock when touching guc_state.sched_state in certain cases. Don't do that, enforce the use of the lock. Part of this is removing a dead code path from guc_lrc_desc_pin where a context could be deregistered when the aforementioned function was called from the submission path. Remove this dead code and add a GEM_BUG_ON if this path is ever attempted to be used. Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 57 ++++++++++--------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 89126be26786..8d45585773f3 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -150,11 +150,22 @@ static inline void clr_context_registered(struct intel_context *ce) #define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT) static inline void init_sched_state(struct intel_context *ce) { - /* Only should be called from guc_lrc_desc_pin() */ + lockdep_assert_held(&ce->guc_state.lock); atomic_set(&ce->guc_sched_state_no_lock, 0); ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK; } +static inline bool sched_state_is_init(struct intel_context *ce) +{ + /* + * XXX: Kernel contexts can have SCHED_STATE_NO_LOCK_REGISTERED after + * suspend. + */ + return !(atomic_read(&ce->guc_sched_state_no_lock) & + ~SCHED_STATE_NO_LOCK_REGISTERED) && + !(ce->guc_state.sched_state &= ~SCHED_STATE_BLOCKED_MASK); +} + static inline bool context_wait_for_deregister_to_register(struct intel_context *ce) { @@ -165,7 +176,7 @@ context_wait_for_deregister_to_register(struct intel_context *ce) static inline void set_context_wait_for_deregister_to_register(struct intel_context *ce) { - /* Only should be called from guc_lrc_desc_pin() without lock */ + lockdep_assert_held(&ce->guc_state.lock); ce->guc_state.sched_state |= SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER; } @@ -599,9 +610,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc) bool pending_disable, pending_enable, deregister, destroyed, banned; xa_for_each(&guc->context_lookup, index, ce) { - /* Flush context */ spin_lock_irqsave(&ce->guc_state.lock, flags); - spin_unlock_irqrestore(&ce->guc_state.lock, flags); /* * Once we are at this point submission_disabled() is guaranteed @@ -617,6 +626,8 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc) banned = context_banned(ce); init_sched_state(ce); + spin_unlock_irqrestore(&ce->guc_state.lock, flags); + if (pending_enable || destroyed || deregister) { atomic_dec(&guc->outstanding_submission_g2h); if (deregister) @@ -1318,6 +1329,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) int ret = 0; GEM_BUG_ON(!engine->mask); + GEM_BUG_ON(!sched_state_is_init(ce)); /* * Ensure LRC + CT vmas are is same region as write barrier is done @@ -1346,7 +1358,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) desc->priority = ce->guc_prio; desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD; guc_context_policy_init(engine, desc); - init_sched_state(ce); /* * The context_lookup xarray is used to determine if the hardware @@ -1357,26 +1368,23 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) * registering this context. */ if (context_registered) { + bool disabled; + unsigned long flags; + trace_intel_context_steal_guc_id(ce); - if (!loop) { + GEM_BUG_ON(!loop); + + /* Seal race with Reset */ + spin_lock_irqsave(&ce->guc_state.lock, flags); + disabled = submission_disabled(guc); + if (likely(!disabled)) { set_context_wait_for_deregister_to_register(ce); intel_context_get(ce); - } else { - bool disabled; - unsigned long flags; - - /* Seal race with Reset */ - spin_lock_irqsave(&ce->guc_state.lock, flags); - disabled = submission_disabled(guc); - if (likely(!disabled)) { - set_context_wait_for_deregister_to_register(ce); - intel_context_get(ce); - } - spin_unlock_irqrestore(&ce->guc_state.lock, flags); - if (unlikely(disabled)) { - reset_lrc_desc(guc, desc_idx); - return 0; /* Will get registered later */ - } + } + spin_unlock_irqrestore(&ce->guc_state.lock, flags); + if (unlikely(disabled)) { + reset_lrc_desc(guc, desc_idx); + return 0; /* Will get registered later */ } /* @@ -1385,10 +1393,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop) */ with_intel_runtime_pm(runtime_pm, wakeref) ret = deregister_context(ce, ce->guc_id, loop); - if (unlikely(ret == -EBUSY)) { - clr_context_wait_for_deregister_to_register(ce); - intel_context_put(ce); - } else if (unlikely(ret == -ENODEV)) { + if (unlikely(ret == -ENODEV)) { ret = 0; /* Will get registered later */ } } else { -- 2.32.0
next prev parent reply other threads:[~2021-08-16 13:57 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-16 13:51 [PATCH 00/22] Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 01/22] drm/i915/guc: Fix blocked context accounting Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 02/22] drm/i915/guc: Fix outstanding G2H accounting Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 9:39 ` Daniel Vetter 2021-08-17 9:39 ` [Intel-gfx] " Daniel Vetter 2021-08-17 18:17 ` Matthew Brost 2021-08-17 18:17 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 03/22] drm/i915/guc: Unwind context requests in reverse order Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 04/22] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 05/22] drm/i915/guc: Workaround reset G2H is received after schedule done G2H Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 9:32 ` Daniel Vetter 2021-08-17 9:32 ` [Intel-gfx] " Daniel Vetter 2021-08-17 15:03 ` Matthew Brost 2021-08-17 15:03 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 06/22] drm/i915/execlists: Do not propagate errors to dependent fences Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 9:21 ` Daniel Vetter 2021-08-17 9:21 ` [Intel-gfx] " Daniel Vetter 2021-08-17 15:08 ` Matthew Brost 2021-08-17 15:08 ` [Intel-gfx] " Matthew Brost 2021-08-17 15:49 ` Daniel Vetter 2021-08-17 15:49 ` [Intel-gfx] " Daniel Vetter 2021-08-16 13:51 ` [PATCH 07/22] drm/i915/selftests: Add a cancel request selftest that triggers a reset Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 08/22] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 9:47 ` Daniel Vetter 2021-08-17 9:47 ` [Intel-gfx] " Daniel Vetter 2021-08-17 9:57 ` Daniel Vetter 2021-08-17 9:57 ` [Intel-gfx] " Daniel Vetter 2021-08-17 16:44 ` Matthew Brost 2021-08-17 16:44 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 09/22] drm/i915/selftests: Fix memory corruption in live_lrc_isolation Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 10/22] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 11/22] drm/i915/guc: Take context ref when cancelling request Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` Matthew Brost [this message] 2021-08-16 13:51 ` [Intel-gfx] [PATCH 12/22] drm/i915/guc: Don't touch guc_state.sched_state without a lock Matthew Brost 2021-08-17 7:21 ` kernel test robot 2021-08-17 7:21 ` kernel test robot 2021-08-17 7:21 ` [Intel-gfx] " kernel test robot 2021-08-16 13:51 ` [PATCH 13/22] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 14/22] drm/i915: Allocate error capture in atomic context Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 10:06 ` Daniel Vetter 2021-08-17 10:06 ` [Intel-gfx] " Daniel Vetter 2021-08-17 16:12 ` Matthew Brost 2021-08-17 16:12 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 15/22] drm/i915/guc: Flush G2H work queue during reset Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 10:06 ` Daniel Vetter 2021-08-16 13:51 ` [PATCH 16/22] drm/i915/guc: Release submit fence from an IRQ Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 10:08 ` Daniel Vetter 2021-08-17 10:08 ` [Intel-gfx] " Daniel Vetter 2021-08-16 13:51 ` [PATCH 17/22] drm/i915/guc: Move guc_blocked fence to struct guc_state Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 10:10 ` Daniel Vetter 2021-08-17 10:10 ` [Intel-gfx] " Daniel Vetter 2021-08-16 13:51 ` [PATCH 18/22] drm/i915/guc: Rework and simplify locking Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 10:15 ` Daniel Vetter 2021-08-17 10:15 ` [Intel-gfx] " Daniel Vetter 2021-08-17 15:30 ` Matthew Brost 2021-08-17 15:30 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 19/22] drm/i915/guc: Proper xarray usage for contexts_lookup Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 10:27 ` Daniel Vetter 2021-08-17 15:26 ` Matthew Brost 2021-08-17 17:13 ` Daniel Vetter 2021-08-17 17:13 ` Matthew Brost 2021-08-16 13:51 ` [PATCH 20/22] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 21/22] drm/i915/guc: Move GuC priority fields in context under guc_active Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-16 13:51 ` [PATCH 22/22] drm/i915/guc: Add GuC kernel doc Matthew Brost 2021-08-16 13:51 ` [Intel-gfx] " Matthew Brost 2021-08-17 11:11 ` Daniel Vetter 2021-08-17 11:11 ` [Intel-gfx] " Daniel Vetter 2021-08-17 16:36 ` Matthew Brost 2021-08-17 16:36 ` [Intel-gfx] " Matthew Brost 2021-08-17 17:20 ` Daniel Vetter 2021-08-17 17:20 ` [Intel-gfx] " Daniel Vetter 2021-08-17 17:27 ` Michal Wajdeczko 2021-08-17 17:27 ` [Intel-gfx] " Michal Wajdeczko 2021-08-17 17:34 ` Daniel Vetter 2021-08-17 17:34 ` [Intel-gfx] " Daniel Vetter 2021-08-17 20:41 ` Michal Wajdeczko 2021-08-17 20:41 ` [Intel-gfx] " Michal Wajdeczko 2021-08-17 21:49 ` Daniel Vetter 2021-08-17 21:49 ` [Intel-gfx] " Daniel Vetter 2021-08-17 12:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev2) Patchwork 2021-08-17 12:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-08-17 13:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-08-17 14:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210816135139.10060-13-matthew.brost@intel.com \ --to=matthew.brost@intel.com \ --cc=daniel.vetter@ffwll.ch \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.