From: Ramalingam C <ramalingam.c@intel.com> To: dri-devel <dri-devel@lists.freedesktop.org>, intel-gfx <intel-gfx@lists.freedesktop.org> Cc: Daniel Vetter <daniel@ffwll.ch>, Matthew Auld <matthew.auld@intel.com>, Hellstrom Thomas <thomas.hellstrom@intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Abdiel Janulgue <abdiel.janulgue@linux.intel.com>, Ramalingam C <ramalingam.c@intel.com> Subject: [PATCH v3 09/17] drm/i915/lmem: Enable lmem for platforms with Flat CCS Date: Thu, 28 Oct 2021 02:53:31 +0530 [thread overview] Message-ID: <20211027212339.29259-10-ramalingam.c@intel.com> (raw) In-Reply-To: <20211027212339.29259-1-ramalingam.c@intel.com> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> A portion of device memory is reserved for Flat CCS so usable device memory will be reduced by size of Flat CCS. Size of Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”. So to get effective device memory we need to subtract total device memory by Flat CCS memory size. Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 1cb1948ac959..fd82ebee8724 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -900,6 +900,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg) return intel_uncore_read_fw(gt->uncore, reg); } +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg) +{ + int type; + u8 sliceid, subsliceid; + + for (type = 0; type < NUM_STEERING_TYPES; type++) { + if (intel_gt_reg_needs_read_steering(gt, reg, type)) { + intel_gt_get_valid_steering(gt, type, &sliceid, + &subsliceid); + return intel_uncore_read_with_mcr_steering(gt->uncore, + reg, + sliceid, + subsliceid); + } + } + + return intel_uncore_read(gt->uncore, reg); +} + void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p) { diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 74e771871a9b..24b78398a587 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -84,6 +84,7 @@ static inline bool intel_gt_needs_read_steering(struct intel_gt *gt, } u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg); +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg); void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p); diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 073d28d96669..d1f88beb26fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -201,8 +201,26 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) if (!IS_DGFX(i915)) return ERR_PTR(-ENODEV); - /* Stolen starts from GSMBASE on DG1 */ - lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); + if (HAS_FLAT_CCS(i915)) { + u64 tile_stolen, flat_ccs_base_addr_reg, flat_ccs_base; + + lmem_size = pci_resource_len(pdev, 2); + flat_ccs_base_addr_reg = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR); + flat_ccs_base = (flat_ccs_base_addr_reg >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K; + tile_stolen = lmem_size - flat_ccs_base; + + /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */ + if (tile_stolen == lmem_size) + DRM_ERROR("CCS_BASE_ADDR register did not have expected value\n"); + + lmem_size -= tile_stolen; + } else { + /* Stolen starts from GSMBASE without CCS */ + lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE); + if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) + return ERR_PTR(-ENODEV); + } + io_start = pci_resource_start(pdev, 2); if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7c97bc352497..5a415345b8e5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12467,6 +12467,9 @@ enum skl_power_gate { #define GEN12_GSMBASE _MMIO(0x108100) #define GEN12_DSMBASE _MMIO(0x1080C0) +#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910) +#define XEHPSDV_CCS_BASE_SHIFT 8 + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com> To: dri-devel <dri-devel@lists.freedesktop.org>, intel-gfx <intel-gfx@lists.freedesktop.org> Cc: Daniel Vetter <daniel@ffwll.ch>, Matthew Auld <matthew.auld@intel.com>, Hellstrom Thomas <thomas.hellstrom@intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Abdiel Janulgue <abdiel.janulgue@linux.intel.com>, Ramalingam C <ramalingam.c@intel.com> Subject: [Intel-gfx] [PATCH v3 09/17] drm/i915/lmem: Enable lmem for platforms with Flat CCS Date: Thu, 28 Oct 2021 02:53:31 +0530 [thread overview] Message-ID: <20211027212339.29259-10-ramalingam.c@intel.com> (raw) In-Reply-To: <20211027212339.29259-1-ramalingam.c@intel.com> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> A portion of device memory is reserved for Flat CCS so usable device memory will be reduced by size of Flat CCS. Size of Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”. So to get effective device memory we need to subtract total device memory by Flat CCS memory size. Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 1cb1948ac959..fd82ebee8724 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -900,6 +900,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg) return intel_uncore_read_fw(gt->uncore, reg); } +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg) +{ + int type; + u8 sliceid, subsliceid; + + for (type = 0; type < NUM_STEERING_TYPES; type++) { + if (intel_gt_reg_needs_read_steering(gt, reg, type)) { + intel_gt_get_valid_steering(gt, type, &sliceid, + &subsliceid); + return intel_uncore_read_with_mcr_steering(gt->uncore, + reg, + sliceid, + subsliceid); + } + } + + return intel_uncore_read(gt->uncore, reg); +} + void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p) { diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 74e771871a9b..24b78398a587 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -84,6 +84,7 @@ static inline bool intel_gt_needs_read_steering(struct intel_gt *gt, } u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg); +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg); void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p); diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 073d28d96669..d1f88beb26fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -201,8 +201,26 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) if (!IS_DGFX(i915)) return ERR_PTR(-ENODEV); - /* Stolen starts from GSMBASE on DG1 */ - lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); + if (HAS_FLAT_CCS(i915)) { + u64 tile_stolen, flat_ccs_base_addr_reg, flat_ccs_base; + + lmem_size = pci_resource_len(pdev, 2); + flat_ccs_base_addr_reg = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR); + flat_ccs_base = (flat_ccs_base_addr_reg >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K; + tile_stolen = lmem_size - flat_ccs_base; + + /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */ + if (tile_stolen == lmem_size) + DRM_ERROR("CCS_BASE_ADDR register did not have expected value\n"); + + lmem_size -= tile_stolen; + } else { + /* Stolen starts from GSMBASE without CCS */ + lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE); + if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) + return ERR_PTR(-ENODEV); + } + io_start = pci_resource_start(pdev, 2); if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7c97bc352497..5a415345b8e5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12467,6 +12467,9 @@ enum skl_power_gate { #define GEN12_GSMBASE _MMIO(0x108100) #define GEN12_DSMBASE _MMIO(0x1080C0) +#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910) +#define XEHPSDV_CCS_BASE_SHIFT 8 + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ -- 2.20.1
next prev parent reply other threads:[~2021-10-27 21:21 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-27 21:23 [PATCH v3 00/17] drm/i915/dg2: Enabling 64k page size and flat ccs Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 01/17] drm/i915: Add has_64k_pages flag Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 02/17] drm/i915/xehpsdv: set min page-size to 64K Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 03/17] drm/i915/xehpsdv: enforce min GTT alignment Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 04/17] drm/i915: enforce min page size for scratch Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 05/17] drm/i915/gtt/xehpsdv: move scratch page to system memory Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 06/17] drm/i915/xehpsdv: support 64K GTT pages Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 07/17] drm/i915/xehpsdv: implement memory coloring Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 08/17] drm/i915/xehpsdv: Add has_flat_ccs to device info Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` Ramalingam C [this message] 2021-10-27 21:23 ` [Intel-gfx] [PATCH v3 09/17] drm/i915/lmem: Enable lmem for platforms with Flat CCS Ramalingam C 2021-10-27 21:23 ` [PATCH v3 10/17] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 11/17] drm/i915/dg2: Prune the Y Tiling modifiers Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 12/17] drm/i915/dg2: Tile 4 plane format support Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-28 7:04 ` Lisovskiy, Stanislav 2021-10-28 7:04 ` [Intel-gfx] " Lisovskiy, Stanislav 2021-10-27 21:23 ` [PATCH v3 13/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-12-07 23:51 ` [Intel-gfx] [Mesa-dev] " Nanley Chery 2021-12-07 23:51 ` Nanley Chery 2021-12-09 19:41 ` [Intel-gfx] " Nanley Chery 2021-12-09 19:41 ` Nanley Chery 2021-12-14 0:23 ` Ramalingam C 2021-12-14 0:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 14/17] drm/i915/dg2: Plane handling for Flat CCS " Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 15/17] drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 16/17] drm/i915/Flat-CCS: Document on Flat-CCS memory compression Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:23 ` [PATCH v3 17/17] Doc/gpu/rfc/i915: i915 DG2 uAPI Ramalingam C 2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C 2021-10-27 21:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Enabling 64k page size and flat ccs (rev3) Patchwork 2021-10-27 21:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-10-27 22:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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