From: Ramalingam C <ramalingam.c@intel.com>
To: dri-devel <dri-devel@lists.freedesktop.org>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel@ffwll.ch>,
Matthew Auld <matthew.auld@intel.com>,
Hellstrom Thomas <thomas.hellstrom@intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Ramalingam C <ramalingam.c@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH v3 02/17] drm/i915/xehpsdv: set min page-size to 64K
Date: Thu, 28 Oct 2021 02:53:24 +0530 [thread overview]
Message-ID: <20211027212339.29259-3-ramalingam.c@intel.com> (raw)
In-Reply-To: <20211027212339.29259-1-ramalingam.c@intel.com>
From: Matthew Auld <matthew.auld@intel.com>
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ddd37ccb1362..f52a06f05fc7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -778,6 +778,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
struct intel_uncore *uncore = &i915->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
u64 lmem_base;
@@ -789,8 +790,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
lmem_size = pci_resource_len(pdev, 2) - lmem_base;
io_start = pci_resource_start(pdev, 2) + lmem_base;
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
+
mem = intel_memory_region_create(i915, lmem_base, lmem_size,
- I915_GTT_PAGE_SIZE_4K, io_start,
+ min_page_size, io_start,
type, instance,
&i915_region_stolen_lmem_ops);
if (IS_ERR(mem))
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index afb35d2e5c73..073d28d96669 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -193,6 +193,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
int err;
@@ -207,10 +208,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
return ERR_PTR(-ENODEV);
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
mem = intel_memory_region_create(i915,
0,
lmem_size,
- I915_GTT_PAGE_SIZE_4K,
+ min_page_size,
io_start,
INTEL_MEMORY_LOCAL,
0,
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com>
To: dri-devel <dri-devel@lists.freedesktop.org>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel@ffwll.ch>,
Matthew Auld <matthew.auld@intel.com>,
Hellstrom Thomas <thomas.hellstrom@intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Ramalingam C <ramalingam.c@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v3 02/17] drm/i915/xehpsdv: set min page-size to 64K
Date: Thu, 28 Oct 2021 02:53:24 +0530 [thread overview]
Message-ID: <20211027212339.29259-3-ramalingam.c@intel.com> (raw)
In-Reply-To: <20211027212339.29259-1-ramalingam.c@intel.com>
From: Matthew Auld <matthew.auld@intel.com>
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ddd37ccb1362..f52a06f05fc7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -778,6 +778,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
struct intel_uncore *uncore = &i915->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
u64 lmem_base;
@@ -789,8 +790,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
lmem_size = pci_resource_len(pdev, 2) - lmem_base;
io_start = pci_resource_start(pdev, 2) + lmem_base;
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
+
mem = intel_memory_region_create(i915, lmem_base, lmem_size,
- I915_GTT_PAGE_SIZE_4K, io_start,
+ min_page_size, io_start,
type, instance,
&i915_region_stolen_lmem_ops);
if (IS_ERR(mem))
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index afb35d2e5c73..073d28d96669 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -193,6 +193,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
int err;
@@ -207,10 +208,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
return ERR_PTR(-ENODEV);
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
mem = intel_memory_region_create(i915,
0,
lmem_size,
- I915_GTT_PAGE_SIZE_4K,
+ min_page_size,
io_start,
INTEL_MEMORY_LOCAL,
0,
--
2.20.1
next prev parent reply other threads:[~2021-10-27 21:21 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 21:23 [PATCH v3 00/17] drm/i915/dg2: Enabling 64k page size and flat ccs Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 01/17] drm/i915: Add has_64k_pages flag Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` Ramalingam C [this message]
2021-10-27 21:23 ` [Intel-gfx] [PATCH v3 02/17] drm/i915/xehpsdv: set min page-size to 64K Ramalingam C
2021-10-27 21:23 ` [PATCH v3 03/17] drm/i915/xehpsdv: enforce min GTT alignment Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 04/17] drm/i915: enforce min page size for scratch Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 05/17] drm/i915/gtt/xehpsdv: move scratch page to system memory Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 06/17] drm/i915/xehpsdv: support 64K GTT pages Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 07/17] drm/i915/xehpsdv: implement memory coloring Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 08/17] drm/i915/xehpsdv: Add has_flat_ccs to device info Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 09/17] drm/i915/lmem: Enable lmem for platforms with Flat CCS Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 10/17] drm/i915/gt: Clear compress metadata for Xe_HP platforms Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 11/17] drm/i915/dg2: Prune the Y Tiling modifiers Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 12/17] drm/i915/dg2: Tile 4 plane format support Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-28 7:04 ` Lisovskiy, Stanislav
2021-10-28 7:04 ` [Intel-gfx] " Lisovskiy, Stanislav
2021-10-27 21:23 ` [PATCH v3 13/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-12-07 23:51 ` [Intel-gfx] [Mesa-dev] " Nanley Chery
2021-12-07 23:51 ` Nanley Chery
2021-12-09 19:41 ` [Intel-gfx] " Nanley Chery
2021-12-09 19:41 ` Nanley Chery
2021-12-14 0:23 ` Ramalingam C
2021-12-14 0:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 14/17] drm/i915/dg2: Plane handling for Flat CCS " Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 15/17] drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 16/17] drm/i915/Flat-CCS: Document on Flat-CCS memory compression Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:23 ` [PATCH v3 17/17] Doc/gpu/rfc/i915: i915 DG2 uAPI Ramalingam C
2021-10-27 21:23 ` [Intel-gfx] " Ramalingam C
2021-10-27 21:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Enabling 64k page size and flat ccs (rev3) Patchwork
2021-10-27 21:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-27 22:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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