From: <conor.dooley@microchip.com>
To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>,
<robh+dt@kernel.org>, <jassisinghbrar@gmail.com>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <a.zummo@towertech.it>,
<alexandre.belloni@bootlin.com>, <broonie@kernel.org>,
<gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
<u.kleine-koenig@pengutronix.de>, <lee.jones@linaro.org>,
<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>,
<linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org>
Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>,
<bin.meng@windriver.com>, <heiko@sntech.de>,
<lewis.hanly@microchip.com>, <conor.dooley@microchip.com>,
<daire.mcnamara@microchip.com>, <ivan.griffin@microchip.com>,
<atishp@rivosinc.com>
Subject: [PATCH v4 13/14] riscv: dts: microchip: add new peripherals to icicle kit device tree
Date: Mon, 17 Jan 2022 11:07:54 +0000 [thread overview]
Message-ID: <20220117110755.3433142-14-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220117110755.3433142-1-conor.dooley@microchip.com>
From: Conor Dooley <conor.dooley@microchip.com>
Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:
2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 168 ++++++++++++++++++
2 files changed, 221 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index dc5f351b10c4..cd2fe80fa81a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@ &mmc {
sd-uhs-sdr104;
};
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -103,6 +123,39 @@ phy0: ethernet-phy@8 {
};
};
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
&core_pwm0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 5e7aaaf42cde..a3ed06ab6392 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -266,6 +266,66 @@ mmc: mmc@20008000 {
status = "disabled";
};
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ clocks = <&clkcfg CLK_SPI0>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <55>;
+ clocks = <&clkcfg CLK_SPI1>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ qspi: spi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <85>;
+ clocks = <&clkcfg CLK_QSPI>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clocks = <&clkcfg CLK_I2C0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ clocks = <&clkcfg CLK_I2C1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
@@ -291,5 +351,113 @@ mac1: ethernet@20112000 {
clock-names = "pclk", "hclk";
status = "disabled";
};
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>, <81>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-names = "dma","mc";
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ microchip,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+
+ rng: rng {
+ compatible = "microchip,mpfs-rng";
+ };
+
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
+ };
};
};
--
2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: <conor.dooley@microchip.com>
To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>,
<robh+dt@kernel.org>, <jassisinghbrar@gmail.com>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <a.zummo@towertech.it>,
<alexandre.belloni@bootlin.com>, <broonie@kernel.org>,
<gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
<u.kleine-koenig@pengutronix.de>, <lee.jones@linaro.org>,
<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>,
<linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org>
Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>,
<bin.meng@windriver.com>, <heiko@sntech.de>,
<lewis.hanly@microchip.com>, <conor.dooley@microchip.com>,
<daire.mcnamara@microchip.com>, <ivan.griffin@microchip.com>,
<atishp@rivosinc.com>
Subject: [PATCH v4 13/14] riscv: dts: microchip: add new peripherals to icicle kit device tree
Date: Mon, 17 Jan 2022 11:07:54 +0000 [thread overview]
Message-ID: <20220117110755.3433142-14-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220117110755.3433142-1-conor.dooley@microchip.com>
From: Conor Dooley <conor.dooley@microchip.com>
Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:
2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 168 ++++++++++++++++++
2 files changed, 221 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index dc5f351b10c4..cd2fe80fa81a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@ &mmc {
sd-uhs-sdr104;
};
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -103,6 +123,39 @@ phy0: ethernet-phy@8 {
};
};
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
&core_pwm0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 5e7aaaf42cde..a3ed06ab6392 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -266,6 +266,66 @@ mmc: mmc@20008000 {
status = "disabled";
};
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ clocks = <&clkcfg CLK_SPI0>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <55>;
+ clocks = <&clkcfg CLK_SPI1>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ qspi: spi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <85>;
+ clocks = <&clkcfg CLK_QSPI>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clocks = <&clkcfg CLK_I2C0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ clocks = <&clkcfg CLK_I2C1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
@@ -291,5 +351,113 @@ mac1: ethernet@20112000 {
clock-names = "pclk", "hclk";
status = "disabled";
};
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>, <81>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-names = "dma","mc";
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ microchip,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+
+ rng: rng {
+ compatible = "microchip,mpfs-rng";
+ };
+
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
+ };
};
};
--
2.32.0
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next prev parent reply other threads:[~2022-01-17 11:07 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-17 11:07 [PATCH v4 00/14] Update the Icicle Kit device tree conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-17 11:07 ` [PATCH v4 01/14] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-17 11:07 ` [PATCH v4 02/14] dt-bindings: soc/microchip: add services as children of sys ctrlr conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-17 11:07 ` [PATCH v4 03/14] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-19 3:10 ` Rob Herring
2022-01-19 3:10 ` Rob Herring
2022-01-20 8:30 ` Geert Uytterhoeven
2022-01-20 8:30 ` Geert Uytterhoeven
2022-01-20 13:42 ` Conor.Dooley
2022-01-20 13:42 ` Conor.Dooley
2022-01-20 14:56 ` Geert Uytterhoeven
2022-01-20 14:56 ` Geert Uytterhoeven
2022-01-20 15:42 ` conor dooley
2022-01-20 15:42 ` conor dooley
2022-01-17 11:07 ` [PATCH v4 04/14] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-19 3:12 ` Rob Herring
2022-01-19 3:12 ` Rob Herring
2022-01-19 10:47 ` Conor.Dooley
2022-01-19 10:47 ` Conor.Dooley
2022-01-17 11:07 ` [PATCH v4 05/14] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-19 3:12 ` Rob Herring
2022-01-19 3:12 ` Rob Herring
2022-01-17 11:07 ` [PATCH v4 06/14] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-19 3:13 ` Rob Herring
2022-01-19 3:13 ` Rob Herring
2022-01-17 11:07 ` [PATCH v4 07/14] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-19 3:13 ` Rob Herring
2022-01-19 3:13 ` Rob Herring
2022-01-17 11:07 ` [PATCH v4 08/14] dt-bindings: pwm: add microchip corepwm binding conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-19 3:14 ` Rob Herring
2022-01-19 3:14 ` Rob Herring
2022-01-17 11:07 ` [PATCH v4 09/14] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-17 11:07 ` [PATCH v4 10/14] riscv: dts: microchip: add fpga fabric section to " conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-17 11:07 ` [PATCH v4 11/14] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-18 11:14 ` Conor.Dooley
2022-01-18 11:14 ` Conor.Dooley
2022-01-17 11:07 ` [PATCH v4 12/14] riscv: dts: microchip: update peripherals in " conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-17 11:07 ` conor.dooley [this message]
2022-01-17 11:07 ` [PATCH v4 13/14] riscv: dts: microchip: add new peripherals to " conor.dooley
2022-01-17 11:07 ` [PATCH v4 14/14] MAINTAINERS: update riscv/microchip entry conor.dooley
2022-01-17 11:07 ` conor.dooley
2022-01-25 10:21 ` (subset) [PATCH v4 00/14] Update the Icicle Kit device tree Mark Brown
2022-01-25 10:21 ` Mark Brown
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