From: Jocelyn Falempe <jfalempe@redhat.com> To: dri-devel@lists.freedesktop.org Cc: michel@daenzer.net, lyude@redhat.com, tzimmermann@suse.de, Jocelyn Falempe <jfalempe@redhat.com>, stable@vger.kernel.org Subject: [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Date: Tue, 8 Mar 2022 18:11:11 +0100 [thread overview] Message-ID: <20220308171111.220557-1-jfalempe@redhat.com> (raw) commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL setup into compute and update functions") introduced a regression for g200wb and g200ew. The PLLs are not set up properly, and VGA screen stays black, or displays "out of range" message. MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with MGA1064_PIX_PLLC_N/M/P which have different addresses. Patch tested on a Dell T310 with g200wb Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4 Cc: stable@vger.kernel.org Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> --- drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c index e9ae22b4f813..52be08b744ad 100644 --- a/drivers/gpu/drm/mgag200/mgag200_pll.c +++ b/drivers/gpu/drm/mgag200/mgag200_pll.c @@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl udelay(50); /* program pixel pll register */ - WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn); - WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm); - WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp); + WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn); + WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm); + WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp); udelay(50); -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Jocelyn Falempe <jfalempe@redhat.com> To: dri-devel@lists.freedesktop.org Cc: stable@vger.kernel.org, michel@daenzer.net, Jocelyn Falempe <jfalempe@redhat.com>, tzimmermann@suse.de Subject: [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Date: Tue, 8 Mar 2022 18:11:11 +0100 [thread overview] Message-ID: <20220308171111.220557-1-jfalempe@redhat.com> (raw) commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL setup into compute and update functions") introduced a regression for g200wb and g200ew. The PLLs are not set up properly, and VGA screen stays black, or displays "out of range" message. MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with MGA1064_PIX_PLLC_N/M/P which have different addresses. Patch tested on a Dell T310 with g200wb Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4 Cc: stable@vger.kernel.org Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> --- drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c index e9ae22b4f813..52be08b744ad 100644 --- a/drivers/gpu/drm/mgag200/mgag200_pll.c +++ b/drivers/gpu/drm/mgag200/mgag200_pll.c @@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl udelay(50); /* program pixel pll register */ - WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn); - WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm); - WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp); + WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn); + WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm); + WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp); udelay(50); -- 2.35.1
next reply other threads:[~2022-03-08 17:12 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-08 17:11 Jocelyn Falempe [this message] 2022-03-08 17:11 ` [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Jocelyn Falempe 2022-03-08 17:31 ` Greg KH 2022-03-08 17:31 ` Greg KH 2022-03-08 17:36 ` Jocelyn Falempe 2022-03-08 17:36 ` Jocelyn Falempe 2022-03-08 17:43 ` [PATCH v2] " Jocelyn Falempe 2022-03-08 17:43 ` Jocelyn Falempe 2022-03-13 19:39 ` Thomas Zimmermann 2022-03-13 19:39 ` Thomas Zimmermann
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