From: Thomas Zimmermann <tzimmermann@suse.de> To: Jocelyn Falempe <jfalempe@redhat.com>, dri-devel@lists.freedesktop.org Cc: stable@vger.kernel.org, michel@daenzer.net Subject: Re: [PATCH v2] drm/mgag200: Fix PLL setup for g200wb and g200ew Date: Sun, 13 Mar 2022 20:39:30 +0100 [thread overview] Message-ID: <50a09e18-34f6-2f74-66eb-f632591f5ff6@suse.de> (raw) In-Reply-To: <20220308174321.225606-1-jfalempe@redhat.com> [-- Attachment #1.1: Type: text/plain, Size: 1931 bytes --] Hi Am 08.03.22 um 18:43 schrieb Jocelyn Falempe: > commit f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and > update functions") introduced a regression for g200wb and g200ew. > The PLLs are not set up properly, and VGA screen stays > black, or displays "out of range" message. > > MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with > MGA1064_PIX_PLLC_N/M/P which have different addresses. > > Patch tested on a Dell T310 with g200wb > > Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions") > Cc: stable@vger.kernel.org > Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> Thank you so much. I've added the patch to drm-misc-fixes. One small nit: next time, please include a little change log that says what each version of the patch changes; even if it's only the style of the commit message. Best regards Thomas > --- > drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c > index e9ae22b4f813..52be08b744ad 100644 > --- a/drivers/gpu/drm/mgag200/mgag200_pll.c > +++ b/drivers/gpu/drm/mgag200/mgag200_pll.c > @@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl > udelay(50); > > /* program pixel pll register */ > - WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn); > - WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm); > - WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp); > + WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn); > + WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm); > + WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp); > > udelay(50); > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 840 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Zimmermann <tzimmermann@suse.de> To: Jocelyn Falempe <jfalempe@redhat.com>, dri-devel@lists.freedesktop.org Cc: michel@daenzer.net, stable@vger.kernel.org Subject: Re: [PATCH v2] drm/mgag200: Fix PLL setup for g200wb and g200ew Date: Sun, 13 Mar 2022 20:39:30 +0100 [thread overview] Message-ID: <50a09e18-34f6-2f74-66eb-f632591f5ff6@suse.de> (raw) In-Reply-To: <20220308174321.225606-1-jfalempe@redhat.com> [-- Attachment #1.1: Type: text/plain, Size: 1931 bytes --] Hi Am 08.03.22 um 18:43 schrieb Jocelyn Falempe: > commit f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and > update functions") introduced a regression for g200wb and g200ew. > The PLLs are not set up properly, and VGA screen stays > black, or displays "out of range" message. > > MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with > MGA1064_PIX_PLLC_N/M/P which have different addresses. > > Patch tested on a Dell T310 with g200wb > > Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions") > Cc: stable@vger.kernel.org > Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> Thank you so much. I've added the patch to drm-misc-fixes. One small nit: next time, please include a little change log that says what each version of the patch changes; even if it's only the style of the commit message. Best regards Thomas > --- > drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c > index e9ae22b4f813..52be08b744ad 100644 > --- a/drivers/gpu/drm/mgag200/mgag200_pll.c > +++ b/drivers/gpu/drm/mgag200/mgag200_pll.c > @@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl > udelay(50); > > /* program pixel pll register */ > - WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn); > - WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm); > - WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp); > + WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn); > + WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm); > + WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp); > > udelay(50); > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 840 bytes --]
next prev parent reply other threads:[~2022-03-13 19:39 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-08 17:11 [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Jocelyn Falempe 2022-03-08 17:11 ` Jocelyn Falempe 2022-03-08 17:31 ` Greg KH 2022-03-08 17:31 ` Greg KH 2022-03-08 17:36 ` Jocelyn Falempe 2022-03-08 17:36 ` Jocelyn Falempe 2022-03-08 17:43 ` [PATCH v2] " Jocelyn Falempe 2022-03-08 17:43 ` Jocelyn Falempe 2022-03-13 19:39 ` Thomas Zimmermann [this message] 2022-03-13 19:39 ` Thomas Zimmermann
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