From: Abel Vesa <abel.vesa@linaro.org> To: "Andy Gross" <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Rob Herring" <robh@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "vkoul@kernel.org" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Manivannan Sadhasivam" <mani@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-phy@lists.infradead.org Subject: [PATCH v5 00/12] sm8550: Add PCIe HC and PHY support Date: Tue, 24 Jan 2023 14:47:02 +0200 [thread overview] Message-ID: <20230124124714.3087948-1-abel.vesa@linaro.org> (raw) For changelogs please look at each patch individually. Abel Vesa (12): dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 phy: qcom-qmp: pcs: Add v6 register offsets phy: qcom-qmp: pcs: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6 register offsets phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add SM8550 PCIe support arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 30 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 37 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 203 +++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 25 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 369 +++++++++++++++++- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 16 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 + .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 ++ .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 6 + 13 files changed, 846 insertions(+), 17 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@linaro.org> To: "Andy Gross" <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Rob Herring" <robh@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "vkoul@kernel.org" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Manivannan Sadhasivam" <mani@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-phy@lists.infradead.org Subject: [PATCH v5 00/12] sm8550: Add PCIe HC and PHY support Date: Tue, 24 Jan 2023 14:47:02 +0200 [thread overview] Message-ID: <20230124124714.3087948-1-abel.vesa@linaro.org> (raw) For changelogs please look at each patch individually. Abel Vesa (12): dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 phy: qcom-qmp: pcs: Add v6 register offsets phy: qcom-qmp: pcs: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6 register offsets phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add SM8550 PCIe support arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 30 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 37 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 203 +++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 25 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 369 +++++++++++++++++- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 16 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 + .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 ++ .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 6 + 13 files changed, 846 insertions(+), 17 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h -- 2.34.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next reply other threads:[~2023-01-24 12:47 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-24 12:47 Abel Vesa [this message] 2023-01-24 12:47 ` [PATCH v5 00/12] sm8550: Add PCIe HC and PHY support Abel Vesa 2023-01-24 12:47 ` [PATCH v5 01/12] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-26 11:03 ` Krzysztof Kozlowski 2023-01-26 11:03 ` Krzysztof Kozlowski 2023-01-24 12:47 ` [PATCH v5 02/12] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 03/12] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 04/12] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 05/12] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 06/12] phy: qcom-qmp: qserdes-txrx: " Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 07/12] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 08/12] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-26 11:05 ` Krzysztof Kozlowski 2023-01-26 11:05 ` Krzysztof Kozlowski 2023-01-24 12:47 ` [PATCH v5 10/12] PCI: qcom: Add SM8550 PCIe support Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes Abel Vesa 2023-01-24 12:47 ` Abel Vesa 2023-01-24 12:47 ` [PATCH v5 12/12] arm64: dts: qcom: sm8550-mtp: " Abel Vesa 2023-01-24 12:47 ` Abel Vesa
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230124124714.3087948-1-abel.vesa@linaro.org \ --to=abel.vesa@linaro.org \ --cc=agross@kernel.org \ --cc=andersson@kernel.org \ --cc=bhelgaas@google.com \ --cc=devicetree@vger.kernel.org \ --cc=kishon@kernel.org \ --cc=konrad.dybcio@linaro.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=kw@linux.com \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=linux-phy@lists.infradead.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=mani@kernel.org \ --cc=p.zabel@pengutronix.de \ --cc=robh@kernel.org \ --cc=vkoul@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.