From: Konrad Dybcio <konrad.dybcio@linaro.org> To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: freedreno@lists.freedesktop.org, Akhil P Oommen <quic_akhilpo@quicinc.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, dri-devel@lists.freedesktop.org, Douglas Anderson <dianders@chromium.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, marijn.suijten@somainline.org, Sean Paul <sean@poorly.run>, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] drm/msm/a6xx: Extend UBWC config Date: Thu, 26 Jan 2023 16:16:06 +0100 [thread overview] Message-ID: <20230126151618.225127-3-konrad.dybcio@linaro.org> (raw) In-Reply-To: <20230126151618.225127-1-konrad.dybcio@linaro.org> Port setting min_access_length, ubwc_mode and upper_bit from downstream. Values were validated using downstream device trees for SM8[123]50 and left default (as per downstream) elsewhere. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c5f5d0bb3fdc..ad5d791b804c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,17 +786,22 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; + u32 lower_bit = 1; + u32 upper_bit = 0; u32 amsbc = 0; u32 rgb565_predicator = 0; u32 uavflagprd_inv = 0; + u32 min_acc_len = 0; + u32 ubwc_mode = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; - if (adreno_is_a640_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu)) { amsbc = 1; + lower_bit = 2; + } if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ @@ -807,18 +812,23 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | upper_bit << 10 | amsbc << 4 | + min_acc_len << 3 | lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, upper_bit << 4 | + min_acc_len << 3 | lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, upper_bit << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | lower_bit << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) -- 2.39.1
WARNING: multiple messages have this Message-ID (diff)
From: Konrad Dybcio <konrad.dybcio@linaro.org> To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Akhil P Oommen <quic_akhilpo@quicinc.com>, Chia-I Wu <olvaffe@gmail.com>, Douglas Anderson <dianders@chromium.org>, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] drm/msm/a6xx: Extend UBWC config Date: Thu, 26 Jan 2023 16:16:06 +0100 [thread overview] Message-ID: <20230126151618.225127-3-konrad.dybcio@linaro.org> (raw) In-Reply-To: <20230126151618.225127-1-konrad.dybcio@linaro.org> Port setting min_access_length, ubwc_mode and upper_bit from downstream. Values were validated using downstream device trees for SM8[123]50 and left default (as per downstream) elsewhere. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c5f5d0bb3fdc..ad5d791b804c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,17 +786,22 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; + u32 lower_bit = 1; + u32 upper_bit = 0; u32 amsbc = 0; u32 rgb565_predicator = 0; u32 uavflagprd_inv = 0; + u32 min_acc_len = 0; + u32 ubwc_mode = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; - if (adreno_is_a640_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu)) { amsbc = 1; + lower_bit = 2; + } if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ @@ -807,18 +812,23 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | upper_bit << 10 | amsbc << 4 | + min_acc_len << 3 | lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, upper_bit << 4 | + min_acc_len << 3 | lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, upper_bit << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + lower_bit << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | lower_bit << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) -- 2.39.1
next prev parent reply other threads:[~2023-01-26 15:17 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-26 15:16 [PATCH 00/14] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio 2023-01-26 15:16 ` [PATCH 01/14] drm/msm/a6xx: De-staticize sptprac en/disable functions Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio [this message] 2023-01-26 15:16 ` [PATCH 02/14] drm/msm/a6xx: Extend UBWC config Konrad Dybcio 2023-02-01 9:30 ` Akhil P Oommen 2023-02-01 9:30 ` Akhil P Oommen 2023-02-01 10:51 ` Konrad Dybcio 2023-02-01 10:51 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 03/14] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 04/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-02-06 18:30 ` Konrad Dybcio 2023-02-06 18:30 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 07/14] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 08/14] drm/msm/a6xx: Add A610 support Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 09/14] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-02-08 18:21 ` [Freedreno] " Jordan Crouse 2023-02-08 18:21 ` Jordan Crouse 2023-02-14 11:25 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 10/14] drm/msm/a6xx: Fix up A6XX protected registers Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 11/14] drm/msm/a6xx: Enable optional icc voting from OPP tables Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 12/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 13/14] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio 2023-01-27 14:19 ` Dmitry Baryshkov 2023-01-27 14:19 ` Dmitry Baryshkov 2023-01-27 14:20 ` Konrad Dybcio 2023-01-27 14:20 ` Konrad Dybcio 2023-01-27 14:22 ` Konrad Dybcio 2023-01-27 14:22 ` Konrad Dybcio 2023-01-26 15:16 ` [PATCH 14/14] drm/msm/a6xx: Add A610 " Konrad Dybcio 2023-01-26 15:16 ` Konrad Dybcio
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