From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com>, Conor Dooley <conor.dooley@microchip.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v5 04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Date: Sun, 29 Jan 2023 01:28:47 +0800 [thread overview] Message-ID: <20230128172856.3814-5-jszhang@kernel.org> (raw) In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org> riscv_cpufeature_patch_func() currently only scans a limited set of cpufeatures, explicitly defined with macros. Extend it to probe for all ISA extensions. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/include/asm/errata_list.h | 9 ++-- arch/riscv/kernel/cpufeature.c | 64 ++++------------------------ 2 files changed, 11 insertions(+), 62 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 4180312d2a70..274c6f889602 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -7,6 +7,7 @@ #include <asm/alternative.h> #include <asm/csr.h> +#include <asm/hwcap.h> #include <asm/vendorid_list.h> #ifdef CONFIG_ERRATA_SIFIVE @@ -22,10 +23,6 @@ #define ERRATA_THEAD_NUMBER 3 #endif -#define CPUFEATURE_SVPBMT 0 -#define CPUFEATURE_ZICBOM 1 -#define CPUFEATURE_NUMBER 2 - #ifdef __ASSEMBLY__ #define ALT_INSN_FAULT(x) \ @@ -55,7 +52,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ - CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ + RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ : "=r"(_val) \ @@ -129,7 +126,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59e20cad1b3d..6193f401f0c5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -276,59 +276,11 @@ void __init riscv_fill_hwcap(void) } #ifdef CONFIG_RISCV_ALTERNATIVE -static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) - return false; - - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - return riscv_isa_extension_available(NULL, SVPBMT); -} - -static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) - return false; - - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - if (!riscv_isa_extension_available(NULL, ZICBOM)) - return false; - - return true; -} - -/* - * Probe presence of individual extensions. - * - * This code may also be executed before kernel relocation, so we cannot use - * addresses generated by the address-of operator as they won't be valid in - * this context. - * Tests, unless otherwise required, are to be added in alphabetical order. - */ -static u32 __init_or_module cpufeature_probe(unsigned int stage) -{ - u32 cpu_req_feature = 0; - - if (cpufeature_probe_svpbmt(stage)) - cpu_req_feature |= BIT(CPUFEATURE_SVPBMT); - - if (cpufeature_probe_zicbom(stage)) - cpu_req_feature |= BIT(CPUFEATURE_ZICBOM); - - return cpu_req_feature; -} - void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) { - u32 cpu_req_feature = cpufeature_probe(stage); struct alt_entry *alt; - u32 tmp; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -336,18 +288,18 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, for (alt = begin; alt < end; alt++) { if (alt->vendor_id != 0) continue; - if (alt->errata_id >= CPUFEATURE_NUMBER) { - WARN(1, "This feature id:%d is not in kernel cpufeature list", + if (alt->errata_id >= RISCV_ISA_EXT_MAX) { + WARN(1, "This extension id:%d is not in ISA extension list", alt->errata_id); continue; } - tmp = (1U << alt->errata_id); - if (cpu_req_feature & tmp) { - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, - alt->old_ptr - alt->alt_ptr); - } + if (!__riscv_isa_extension_available(NULL, alt->errata_id)) + continue; + + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, + alt->old_ptr - alt->alt_ptr); } } #endif -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com>, Conor Dooley <conor.dooley@microchip.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v5 04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Date: Sun, 29 Jan 2023 01:28:47 +0800 [thread overview] Message-ID: <20230128172856.3814-5-jszhang@kernel.org> (raw) In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org> riscv_cpufeature_patch_func() currently only scans a limited set of cpufeatures, explicitly defined with macros. Extend it to probe for all ISA extensions. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/include/asm/errata_list.h | 9 ++-- arch/riscv/kernel/cpufeature.c | 64 ++++------------------------ 2 files changed, 11 insertions(+), 62 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 4180312d2a70..274c6f889602 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -7,6 +7,7 @@ #include <asm/alternative.h> #include <asm/csr.h> +#include <asm/hwcap.h> #include <asm/vendorid_list.h> #ifdef CONFIG_ERRATA_SIFIVE @@ -22,10 +23,6 @@ #define ERRATA_THEAD_NUMBER 3 #endif -#define CPUFEATURE_SVPBMT 0 -#define CPUFEATURE_ZICBOM 1 -#define CPUFEATURE_NUMBER 2 - #ifdef __ASSEMBLY__ #define ALT_INSN_FAULT(x) \ @@ -55,7 +52,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ - CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ + RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ : "=r"(_val) \ @@ -129,7 +126,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59e20cad1b3d..6193f401f0c5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -276,59 +276,11 @@ void __init riscv_fill_hwcap(void) } #ifdef CONFIG_RISCV_ALTERNATIVE -static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) - return false; - - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - return riscv_isa_extension_available(NULL, SVPBMT); -} - -static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) - return false; - - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) - return false; - - if (!riscv_isa_extension_available(NULL, ZICBOM)) - return false; - - return true; -} - -/* - * Probe presence of individual extensions. - * - * This code may also be executed before kernel relocation, so we cannot use - * addresses generated by the address-of operator as they won't be valid in - * this context. - * Tests, unless otherwise required, are to be added in alphabetical order. - */ -static u32 __init_or_module cpufeature_probe(unsigned int stage) -{ - u32 cpu_req_feature = 0; - - if (cpufeature_probe_svpbmt(stage)) - cpu_req_feature |= BIT(CPUFEATURE_SVPBMT); - - if (cpufeature_probe_zicbom(stage)) - cpu_req_feature |= BIT(CPUFEATURE_ZICBOM); - - return cpu_req_feature; -} - void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) { - u32 cpu_req_feature = cpufeature_probe(stage); struct alt_entry *alt; - u32 tmp; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -336,18 +288,18 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, for (alt = begin; alt < end; alt++) { if (alt->vendor_id != 0) continue; - if (alt->errata_id >= CPUFEATURE_NUMBER) { - WARN(1, "This feature id:%d is not in kernel cpufeature list", + if (alt->errata_id >= RISCV_ISA_EXT_MAX) { + WARN(1, "This extension id:%d is not in ISA extension list", alt->errata_id); continue; } - tmp = (1U << alt->errata_id); - if (cpu_req_feature & tmp) { - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, - alt->old_ptr - alt->alt_ptr); - } + if (!__riscv_isa_extension_available(NULL, alt->errata_id)) + continue; + + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, + alt->old_ptr - alt->alt_ptr); } } #endif -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-28 17:40 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-28 17:28 [PATCH v5 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 01/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 02/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 03/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang [this message] 2023-01-28 17:28 ` [PATCH v5 04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 05/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-03-22 12:01 ` Jason A. Donenfeld 2023-03-22 12:01 ` Jason A. Donenfeld 2023-03-22 12:09 ` [PATCH] riscv: require alternatives framework when selecting FPU support Jason A. Donenfeld 2023-03-22 12:09 ` Jason A. Donenfeld 2023-03-22 12:46 ` Andrew Jones 2023-03-22 12:46 ` Andrew Jones 2023-03-22 15:17 ` Conor Dooley 2023-03-22 15:17 ` Conor Dooley 2023-03-22 19:26 ` Andrew Jones 2023-03-22 19:26 ` Andrew Jones 2023-03-22 19:44 ` Conor Dooley 2023-03-22 19:44 ` Conor Dooley 2023-03-22 20:05 ` Conor Dooley 2023-03-22 20:05 ` Conor Dooley 2023-03-22 20:19 ` Jason A. Donenfeld 2023-03-22 20:19 ` Jason A. Donenfeld 2023-03-23 14:49 ` Conor Dooley 2023-03-23 14:49 ` Conor Dooley 2023-03-23 15:56 ` Jason A. Donenfeld 2023-03-23 15:56 ` Jason A. Donenfeld 2023-03-23 22:19 ` Conor Dooley 2023-03-23 22:19 ` Conor Dooley 2023-01-28 17:28 ` [PATCH v5 07/13] riscv: module: move find_section to module.h Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 08/13] riscv: module: Add ADD16 and SUB16 rela types Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 09/13] riscv: switch to relative alternative entries Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-01-28 17:28 ` [PATCH v5 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang 2023-01-28 17:28 ` Jisheng Zhang 2023-02-02 23:39 ` [PATCH v5 00/13] riscv: improve boot time isa extensions handling Palmer Dabbelt 2023-02-02 23:39 ` Palmer Dabbelt 2023-02-02 23:40 ` patchwork-bot+linux-riscv 2023-02-02 23:40 ` patchwork-bot+linux-riscv 2023-02-12 15:43 ` Guenter Roeck 2023-02-12 15:43 ` Guenter Roeck 2023-02-12 15:59 ` Conor Dooley 2023-02-12 15:59 ` Conor Dooley 2023-02-12 16:33 ` Conor Dooley 2023-02-12 16:33 ` Conor Dooley 2023-02-12 17:06 ` Conor Dooley 2023-02-12 17:06 ` Conor Dooley 2023-02-12 18:06 ` Conor Dooley 2023-02-12 18:06 ` Conor Dooley 2023-02-12 18:14 ` Guenter Roeck 2023-02-12 18:14 ` Guenter Roeck 2023-02-12 18:20 ` Conor Dooley 2023-02-12 18:20 ` Conor Dooley 2023-02-12 18:38 ` Guenter Roeck 2023-02-12 18:38 ` Guenter Roeck 2023-02-12 18:45 ` Conor Dooley 2023-02-12 18:45 ` Conor Dooley 2023-02-12 20:27 ` Guenter Roeck 2023-02-12 20:27 ` Guenter Roeck 2023-02-12 20:39 ` Conor Dooley 2023-02-12 20:39 ` Conor Dooley 2023-02-12 22:21 ` Guenter Roeck 2023-02-12 22:21 ` Guenter Roeck
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