From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v4 11/14] RISC-V: Set minimum priv version for Zfh to 1.11
Date: Tue, 31 Jan 2023 19:01:55 +0100 [thread overview]
Message-ID: <20230131180158.2471047-12-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
There are no differences for floating point instructions in priv version 1.11
and 1.12. There is also no dependency for Zfh to priv version 1.12.
Therefore allow Zfh to be enabled for priv version 1.11.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5679e2cb83..3078556f1b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -77,7 +77,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
- ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
+ ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
--
2.39.1
next prev parent reply other threads:[~2023-01-31 18:07 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-31 18:01 [PATCH v4 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-31 18:23 ` Richard Henderson
2023-01-31 20:09 ` Christoph Müllner
2023-01-31 18:01 ` [PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-31 18:01 ` Christoph Muellner [this message]
2023-01-31 18:01 ` [PATCH v4 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner
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