From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v4 06/14] RISC-V: Adding XTheadCondMov ISA extension
Date: Tue, 31 Jan 2023 19:01:50 +0100 [thread overview]
Message-ID: <20230131180158.2471047-7-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Fix invalid use of register from dest_gpr()
- Use single decoder for XThead extensions
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++
target/riscv/translate.c | 2 +-
target/riscv/xthead.decode | 4 +++
5 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c541924214..13b065bc68 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
+ ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
@@ -1097,6 +1098,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
+ DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 876eaebd0e..a313e025e7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -477,6 +477,7 @@ struct RISCVCPUConfig {
bool ext_xtheadbb;
bool ext_xtheadbs;
bool ext_xtheadcmo;
+ bool ext_xtheadcondmov;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index bc1605445d..089b51f468 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -40,6 +40,12 @@
} \
} while (0)
+#define REQUIRE_XTHEADCONDMOV(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadcondmov) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADSYNC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadsync) { \
return false; \
@@ -264,6 +270,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+/* XTheadCondMov */
+
+static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv old = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+/* th.mveqz: "if (rs2 == 0) rd = rs1;" */
+static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a)
+{
+ REQUIRE_XTHEADCONDMOV(ctx);
+ return gen_th_condmove(ctx, a, TCG_COND_EQ);
+}
+
+/* th.mvnez: "if (rs2 != 0) rd = rs1;" */
+static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
+{
+ REQUIRE_XTHEADCONDMOV(ctx);
+ return gen_th_condmove(ctx, a, TCG_COND_NE);
+}
+
/* XTheadSync */
static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 880324e617..4f4c09cd68 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -134,7 +134,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
{
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
- ctx->cfg_ptr->ext_xtheadsync;
+ ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index 8494805611..a8ebd8a18b 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011
th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
th_l2cache_iall 0000000 10110 00000 000 00000 0001011
+# XTheadCondMov
+th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r
+th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r
+
# XTheadSync
th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
th_sync 0000000 11000 00000 000 00000 0001011
--
2.39.1
next prev parent reply other threads:[~2023-01-31 18:03 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-31 18:01 [PATCH v4 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-31 18:01 ` Christoph Muellner [this message]
2023-01-31 18:01 ` [PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-31 18:23 ` Richard Henderson
2023-01-31 20:09 ` Christoph Müllner
2023-01-31 18:01 ` [PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner
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