From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions
Date: Tue, 31 Jan 2023 19:01:51 +0100 [thread overview]
Message-ID: <20230131180158.2471047-8-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use single decoder for XThead extensions
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++
target/riscv/translate.c | 3 +-
target/riscv/xthead.decode | 8 +++
5 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13b065bc68..88da4de14d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
+ ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
@@ -1099,6 +1100,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
+ DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a313e025e7..830b20558c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -478,6 +478,7 @@ struct RISCVCPUConfig {
bool ext_xtheadbs;
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
+ bool ext_xtheadmac;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index 089b51f468..31a4034927 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -46,6 +46,12 @@
} \
} while (0)
+#define REQUIRE_XTHEADMAC(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadmac) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADSYNC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadsync) { \
return false; \
@@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
return gen_th_condmove(ctx, a, TCG_COND_NE);
}
+/* XTheadMac */
+
+static bool gen_th_mac(DisasContext *ctx, arg_r *a,
+ void (*accumulate_func)(TCGv, TCGv, TCGv),
+ void (*extend_operand_func)(TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv tmp = tcg_temp_new();
+
+ if (extend_operand_func) {
+ TCGv tmp2 = tcg_temp_new();
+ extend_operand_func(tmp, src1);
+ extend_operand_func(tmp2, src2);
+ tcg_gen_mul_tl(tmp, tmp, tmp2);
+ tcg_temp_free(tmp2);
+ } else {
+ tcg_gen_mul_tl(tmp, src1, src2);
+ }
+
+ accumulate_func(dest, src0, tmp);
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free(tmp);
+
+ return true;
+}
+
+/* th.mula: "rd = rd + rs1 * rs2" */
+static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL);
+}
+
+/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */
+static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl);
+}
+
+/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */
+static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ REQUIRE_64BIT(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL);
+}
+
+/* th.muls: "rd = rd - rs1 * rs2" */
+static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
+}
+
+/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */
+static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl);
+}
+
+/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */
+static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
+{
+ REQUIRE_XTHEADMAC(ctx);
+ REQUIRE_64BIT(ctx);
+ ctx->ol = MXL_RV32;
+ return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
+}
+
/* XTheadSync */
static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4f4c09cd68..e5a57a8516 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
{
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
- ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync;
+ ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
+ ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index a8ebd8a18b..696de6cecf 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011
th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r
th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r
+# XTheadMac
+th_mula 00100 00 ..... ..... 001 ..... 0001011 @r
+th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r
+th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r
+th_muls 00100 01 ..... ..... 001 ..... 0001011 @r
+th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r
+th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r
+
# XTheadSync
th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
th_sync 0000000 11000 00000 000 00000 0001011
--
2.39.1
next prev parent reply other threads:[~2023-01-31 18:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-31 18:01 [PATCH v4 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-31 18:01 ` Christoph Muellner [this message]
2023-01-31 18:01 ` [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-31 18:23 ` Richard Henderson
2023-01-31 20:09 ` Christoph Müllner
2023-01-31 18:01 ` [PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner
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