From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension
Date: Tue, 31 Jan 2023 19:01:57 +0100 [thread overview]
Message-ID: <20230131180158.2471047-14-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++
target/riscv/translate.c | 6 +--
target/riscv/xthead.decode | 4 ++
5 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8cbc5c9c1b..0dd2f0c753 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -116,6 +116,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
+ ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv),
ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
@@ -1134,6 +1135,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
+ DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 60478f4a9c..7128438d8e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -480,6 +480,7 @@ struct RISCVCPUConfig {
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
bool ext_xtheadfmemidx;
+ bool ext_xtheadfmv;
bool ext_xtheadmac;
bool ext_xtheadmemidx;
bool ext_xtheadmempair;
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index 0e77275457..5f327d1bdf 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -52,6 +52,12 @@
} \
} while (0)
+#define REQUIRE_XTHEADFMV(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadfmv) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADMAC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadmac) { \
return false; \
@@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
return gen_fstore_idx(ctx, a, MO_TEUL, true);
}
+/* XTheadFmv */
+
+static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a)
+{
+ REQUIRE_XTHEADFMV(ctx);
+ REQUIRE_32BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t1, src1);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
+ tcg_temp_free_i64(t1);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a)
+{
+ REQUIRE_XTHEADFMV(ctx);
+ REQUIRE_32BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ TCGv dst;
+ TCGv_i64 t1;
+
+ dst = dest_gpr(ctx, a->rd);
+ t1 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
+ tcg_gen_trunc_i64_tl(dst, t1);
+ gen_set_gpr(ctx, a->rd, dst);
+ tcg_temp_free_i64(t1);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
/* XTheadMac */
static bool gen_th_mac(DisasContext *ctx, arg_r *a,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 216eaf9d12..182649dcb6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -135,9 +135,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
ctx->cfg_ptr->ext_xtheadcondmov ||
- ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac ||
- ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
- ctx->cfg_ptr->ext_xtheadsync;
+ ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
+ ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
+ ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index 81daf1d694..d1d104bcf2 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx
th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx
th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx
+# XTheadFmv
+th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2
+th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2
+
# XTheadMac
th_mula 00100 00 ..... ..... 001 ..... 0001011 @r
th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r
--
2.39.1
next prev parent reply other threads:[~2023-01-31 18:07 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-31 18:01 [PATCH v4 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-31 18:23 ` Richard Henderson
2023-01-31 20:09 ` Christoph Müllner
2023-01-31 18:01 ` [PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-31 18:01 ` [PATCH v4 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-31 18:01 ` Christoph Muellner [this message]
2023-01-31 18:01 ` [PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner
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