From: Abel Vesa <abel.vesa@linaro.org> To: "Andy Gross" <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Rob Herring" <robh@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "vkoul@kernel.org" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Manivannan Sadhasivam" <mani@kernel.org>, "Johan Hovold" <johan+linaro@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Subject: [PATCH v8 03/11] phy: qcom-qmp: pcs: Add v6.20 register offsets Date: Mon, 6 Feb 2023 23:26:11 +0200 [thread overview] Message-ID: <20230206212619.3218741-4-abel.vesa@linaro.org> (raw) In-Reply-To: <20230206212619.3218741-1-abel.vesa@linaro.org> The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- The v7 of this patch is: https://lore.kernel.org/all/20230203081807.2248625-4-abel.vesa@linaro.org/ Changes since v7: * none Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 ++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 20 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h new file mode 100644 index 000000000000..9c3f1e4950e6 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_20_H_ +#define QCOM_PHY_QMP_PCS_V6_20_H_ + +/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 +#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 +#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc +#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 +#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 +#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 80e3b5c860b6..760de4c76e5b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -40,6 +40,8 @@ #include "phy-qcom-qmp-pcs-v6.h" +#include "phy-qcom-qmp-pcs-v6_20.h" + /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 #define QPHY_V3_DP_COM_SW_RESET 0x04 -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@linaro.org> To: "Andy Gross" <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Rob Herring" <robh@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "vkoul@kernel.org" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Manivannan Sadhasivam" <mani@kernel.org>, "Johan Hovold" <johan+linaro@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Subject: [PATCH v8 03/11] phy: qcom-qmp: pcs: Add v6.20 register offsets Date: Mon, 6 Feb 2023 23:26:11 +0200 [thread overview] Message-ID: <20230206212619.3218741-4-abel.vesa@linaro.org> (raw) In-Reply-To: <20230206212619.3218741-1-abel.vesa@linaro.org> The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- The v7 of this patch is: https://lore.kernel.org/all/20230203081807.2248625-4-abel.vesa@linaro.org/ Changes since v7: * none Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 ++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 20 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h new file mode 100644 index 000000000000..9c3f1e4950e6 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_20_H_ +#define QCOM_PHY_QMP_PCS_V6_20_H_ + +/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 +#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 +#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc +#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 +#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 +#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 80e3b5c860b6..760de4c76e5b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -40,6 +40,8 @@ #include "phy-qcom-qmp-pcs-v6.h" +#include "phy-qcom-qmp-pcs-v6_20.h" + /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 #define QPHY_V3_DP_COM_SW_RESET 0x04 -- 2.34.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2023-02-06 21:26 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-06 21:26 [PATCH v8 00/11] sm8550: Add PCIe HC and PHY support Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 01/11] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 02/11] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` Abel Vesa [this message] 2023-02-06 21:26 ` [PATCH v8 03/11] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa 2023-02-06 21:26 ` [PATCH v8 04/11] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 05/11] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 06/11] phy: qcom-qmp: qserdes-txrx: " Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 07/11] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 08/11] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-08 16:48 ` Johan Hovold 2023-02-08 16:48 ` Johan Hovold 2023-02-06 21:26 ` [PATCH v8 09/11] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-06 21:26 ` [PATCH v8 10/11] PCI: qcom: Add SM8550 PCIe support Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-08 16:58 ` Johan Hovold 2023-02-08 16:58 ` Johan Hovold 2023-02-06 21:26 ` [PATCH v8 11/11] arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes Abel Vesa 2023-02-06 21:26 ` Abel Vesa 2023-02-08 17:02 ` Johan Hovold 2023-02-08 17:02 ` Johan Hovold
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