From: Bjorn Andersson <andersson@kernel.org> To: Kathiravan T <quic_kathirav@quicinc.com> Cc: krzysztof.kozlowski@linaro.org, agross@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, arnd@arndb.de, dmitry.baryshkov@linaro.org, marcel.ziswiler@toradex.com, nfraprado@collabora.com, robimarko@gmail.com, quic_gurus@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_varada@quicinc.com, quic_srichara@quicinc.com Subject: Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Date: Mon, 6 Feb 2023 19:41:08 -0800 [thread overview] Message-ID: <20230207034108.bypitlfxicpz6wqb@ripper> (raw) In-Reply-To: <20230206071217.29313-6-quic_kathirav@quicinc.com> On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote: > diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c [..] > + > +enum { > + DT_SLEEP_CLK, > + DT_XO, > + DT_PCIE_2LANE_PHY_PIPE_CLK, > + DT_PCIE_2LANE_PHY_PIPE_X1_CLK, > + DT_USB_PCIE_WRAPPER_PIPE_CLK, This list does not match the clocks as defined in the binding. > +}; > + > +enum { > + P_PCIE3X2_PIPE, > + P_PCIE3X1_0_PIPE, > + P_PCIE3X1_1_PIPE, > + P_USB3PHY_0_PIPE, > + P_CORE_BI_PLL_TEST_SE, > + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, > + P_GPLL0_OUT_AUX, > + P_GPLL0_OUT_MAIN, > + P_GPLL2_OUT_AUX, > + P_GPLL2_OUT_MAIN, > + P_GPLL4_OUT_AUX, > + P_GPLL4_OUT_MAIN, > + P_SLEEP_CLK, > + P_XO, > +}; > + > +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; > + > +static struct clk_alpha_pll gpll0_main = { > + .offset = 0x20000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], > + .clkr = { > + .enable_reg = 0xb000, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data){ Please add a space between ')' and '{ on all these. > + .name = "gpll0_main", > + .parent_data = &gcc_parent_data_xo, > + .num_parents = 1, > + .ops = &clk_alpha_pll_stromer_ops, > + }, > + }, > +}; [..] > +static const struct qcom_cc_desc gcc_ipq5332_desc = { > + .config = &gcc_ipq5332_regmap_config, > + .clks = gcc_ipq5332_clocks, > + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks), > + .resets = gcc_ipq5332_resets, > + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets), > + .clk_hws = gcc_ipq5332_hws, > + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws), No GDSCs? Regards, Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <andersson@kernel.org> To: Kathiravan T <quic_kathirav@quicinc.com> Cc: krzysztof.kozlowski@linaro.org, agross@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, arnd@arndb.de, dmitry.baryshkov@linaro.org, marcel.ziswiler@toradex.com, nfraprado@collabora.com, robimarko@gmail.com, quic_gurus@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_varada@quicinc.com, quic_srichara@quicinc.com Subject: Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Date: Mon, 6 Feb 2023 19:41:08 -0800 [thread overview] Message-ID: <20230207034108.bypitlfxicpz6wqb@ripper> (raw) In-Reply-To: <20230206071217.29313-6-quic_kathirav@quicinc.com> On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote: > diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c [..] > + > +enum { > + DT_SLEEP_CLK, > + DT_XO, > + DT_PCIE_2LANE_PHY_PIPE_CLK, > + DT_PCIE_2LANE_PHY_PIPE_X1_CLK, > + DT_USB_PCIE_WRAPPER_PIPE_CLK, This list does not match the clocks as defined in the binding. > +}; > + > +enum { > + P_PCIE3X2_PIPE, > + P_PCIE3X1_0_PIPE, > + P_PCIE3X1_1_PIPE, > + P_USB3PHY_0_PIPE, > + P_CORE_BI_PLL_TEST_SE, > + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, > + P_GPLL0_OUT_AUX, > + P_GPLL0_OUT_MAIN, > + P_GPLL2_OUT_AUX, > + P_GPLL2_OUT_MAIN, > + P_GPLL4_OUT_AUX, > + P_GPLL4_OUT_MAIN, > + P_SLEEP_CLK, > + P_XO, > +}; > + > +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; > + > +static struct clk_alpha_pll gpll0_main = { > + .offset = 0x20000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], > + .clkr = { > + .enable_reg = 0xb000, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data){ Please add a space between ')' and '{ on all these. > + .name = "gpll0_main", > + .parent_data = &gcc_parent_data_xo, > + .num_parents = 1, > + .ops = &clk_alpha_pll_stromer_ops, > + }, > + }, > +}; [..] > +static const struct qcom_cc_desc gcc_ipq5332_desc = { > + .config = &gcc_ipq5332_regmap_config, > + .clks = gcc_ipq5332_clocks, > + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks), > + .resets = gcc_ipq5332_resets, > + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets), > + .clk_hws = gcc_ipq5332_hws, > + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws), No GDSCs? Regards, Bjorn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-02-07 3:39 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-06 7:12 [PATCH V3 0/9] Add minimal boot support for IPQ5332 Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 7:12 ` [PATCH V3 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 8:26 ` Krzysztof Kozlowski 2023-02-06 8:26 ` Krzysztof Kozlowski 2023-02-06 7:12 ` [PATCH V3 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-07 3:34 ` Bjorn Andersson 2023-02-07 3:34 ` Bjorn Andersson 2023-02-06 7:12 ` [PATCH V3 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 7:12 ` [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 8:26 ` Krzysztof Kozlowski 2023-02-06 8:26 ` Krzysztof Kozlowski 2023-02-06 9:52 ` Dmitry Baryshkov 2023-02-06 9:52 ` Dmitry Baryshkov 2023-02-07 4:26 ` Kathiravan T 2023-02-07 4:26 ` Kathiravan T 2023-02-07 10:05 ` Dmitry Baryshkov 2023-02-07 10:05 ` Dmitry Baryshkov 2023-02-06 7:12 ` [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Kathiravan T 2023-02-06 9:52 ` Dmitry Baryshkov 2023-02-06 9:56 ` Dmitry Baryshkov 2023-02-06 9:56 ` Dmitry Baryshkov 2023-02-07 4:29 ` Kathiravan T 2023-02-07 4:29 ` Kathiravan T 2023-02-07 3:41 ` Bjorn Andersson [this message] 2023-02-07 3:41 ` Bjorn Andersson 2023-02-07 4:31 ` Kathiravan T 2023-02-07 4:31 ` Kathiravan T 2023-02-06 7:12 ` [PATCH V3 6/9] dt-bindings: qcom: add ipq5332 boards Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 8:27 ` Krzysztof Kozlowski 2023-02-06 8:27 ` Krzysztof Kozlowski 2023-02-06 7:12 ` [PATCH V3 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 7:12 ` [PATCH V3 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 7:12 ` [PATCH V3 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs Kathiravan T 2023-02-06 7:12 ` Kathiravan T 2023-02-06 9:53 ` Dmitry Baryshkov 2023-02-06 9:53 ` Dmitry Baryshkov 2023-02-06 11:25 ` [PATCH V3 0/9] Add minimal boot support for IPQ5332 Linus Walleij 2023-02-06 11:25 ` Linus Walleij 2023-02-06 11:42 ` Kathiravan T 2023-02-06 11:42 ` Kathiravan T
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