Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC

From: Kathiravan T <quic_kathirav@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>
Cc: <krzysztof.kozlowski@linaro.org>, <agross@kernel.org>,
	<konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,
	<sboyd@kernel.org>, <linus.walleij@linaro.org>,
	<catalin.marinas@arm.com>, <will@kernel.org>,
	<shawnguo@kernel.org>, <arnd@arndb.de>,
	<dmitry.baryshkov@linaro.org>, <marcel.ziswiler@toradex.com>,
	<nfraprado@collabora.com>, <robimarko@gmail.com>,
	<quic_gurus@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <quic_varada@quicinc.com>,
	<quic_srichara@quicinc.com>
Subject: Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
Date: Tue, 7 Feb 2023 10:01:55 +0530	[thread overview]
Message-ID: <e59d133e-40a9-0dae-b272-20d82e8c9b76@quicinc.com> (raw)
In-Reply-To: <20230207034108.bypitlfxicpz6wqb@ripper>

Thanks Bjorn for the review!

On 2/7/2023 9:11 AM, Bjorn Andersson wrote:
> On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote:
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> [..]
>> +
>> +enum {
>> +	DT_SLEEP_CLK,
>> +	DT_XO,
>> +	DT_PCIE_2LANE_PHY_PIPE_CLK,
>> +	DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
>> +	DT_USB_PCIE_WRAPPER_PIPE_CLK,
> This list does not match the clocks as defined in the binding.

Ack. will fix this in next spin.

>
>> +};
>> +
>> +enum {
>> +	P_PCIE3X2_PIPE,
>> +	P_PCIE3X1_0_PIPE,
>> +	P_PCIE3X1_1_PIPE,
>> +	P_USB3PHY_0_PIPE,
>> +	P_CORE_BI_PLL_TEST_SE,
>> +	P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
>> +	P_GPLL0_OUT_AUX,
>> +	P_GPLL0_OUT_MAIN,
>> +	P_GPLL2_OUT_AUX,
>> +	P_GPLL2_OUT_MAIN,
>> +	P_GPLL4_OUT_AUX,
>> +	P_GPLL4_OUT_MAIN,
>> +	P_SLEEP_CLK,
>> +	P_XO,
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> +	.offset = 0x20000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
>> +	.clkr = {
>> +		.enable_reg = 0xb000,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(const struct clk_init_data){
> Please add a space between ')' and '{ on all these.

Ack.

>
>> +			.name = "gpll0_main",
>> +			.parent_data = &gcc_parent_data_xo,
>> +			.num_parents = 1,
>> +			.ops = &clk_alpha_pll_stromer_ops,
>> +		},
>> +	},
>> +};
> [..]
>> +static const struct qcom_cc_desc gcc_ipq5332_desc = {
>> +	.config = &gcc_ipq5332_regmap_config,
>> +	.clks = gcc_ipq5332_clocks,
>> +	.num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
>> +	.resets = gcc_ipq5332_resets,
>> +	.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
>> +	.clk_hws = gcc_ipq5332_hws,
>> +	.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
> No GDSCs?

No, there is no GDSC support.

>
> Regards,
> Bjorn