From: Brad Larson <blarson@amd.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <adrian.hunter@intel.com>, <alcooperx@gmail.com>, <andy.shevchenko@gmail.com>, <arnd@arndb.de>, <blarson@amd.com>, <brendan.higgins@linux.dev>, <briannorris@chromium.org>, <brijeshkumar.singh@amd.com>, <catalin.marinas@arm.com>, <davidgow@google.com>, <gsomlo@gmail.com>, <gerg@linux-m68k.org>, <krzk@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <lee@kernel.org>, <lee.jones@linaro.org>, <broonie@kernel.org>, <yamada.masahiro@socionext.com>, <p.zabel@pengutronix.de>, <piotrs@cadence.com>, <p.yadav@ti.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <fancer.lancer@gmail.com>, <skhan@linuxfoundation.org>, <suravee.suthikulpanit@amd.com>, <thomas.lendacky@amd.com>, <tonyhuang.sunplus@gmail.com>, <ulf.hansson@linaro.org>, <vaishnav.a@ti.com>, <will@kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH v12 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:51 -0700 [thread overview] Message-ID: <20230323000657.28664-10-blarson@amd.com> (raw) In-Reply-To: <20230323000657.28664-1-blarson@amd.com> The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson <blarson@amd.com> --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Brad Larson <blarson@amd.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <adrian.hunter@intel.com>, <alcooperx@gmail.com>, <andy.shevchenko@gmail.com>, <arnd@arndb.de>, <blarson@amd.com>, <brendan.higgins@linux.dev>, <briannorris@chromium.org>, <brijeshkumar.singh@amd.com>, <catalin.marinas@arm.com>, <davidgow@google.com>, <gsomlo@gmail.com>, <gerg@linux-m68k.org>, <krzk@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <lee@kernel.org>, <lee.jones@linaro.org>, <broonie@kernel.org>, <yamada.masahiro@socionext.com>, <p.zabel@pengutronix.de>, <piotrs@cadence.com>, <p.yadav@ti.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <fancer.lancer@gmail.com>, <skhan@linuxfoundation.org>, <suravee.suthikulpanit@amd.com>, <thomas.lendacky@amd.com>, <tonyhuang.sunplus@gmail.com>, <ulf.hansson@linaro.org>, <vaishnav.a@ti.com>, <will@kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH v12 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:51 -0700 [thread overview] Message-ID: <20230323000657.28664-10-blarson@amd.com> (raw) In-Reply-To: <20230323000657.28664-1-blarson@amd.com> The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson <blarson@amd.com> --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-23 0:10 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-23 0:06 [PATCH v12 00/15] Support AMD Pensando Elba SoC Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 01/15] dt-bindings: arm: add AMD Pensando boards Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 6:36 ` Krzysztof Kozlowski 2023-03-23 6:36 ` Krzysztof Kozlowski 2023-03-23 0:06 ` [PATCH v12 03/15] dt-bindings: spi: cdns: Add compatible for " Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 05/15] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 06/15] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 07/15] arm64: Add config for AMD Pensando SoC platforms Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 08/15] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` Brad Larson [this message] 2023-03-23 0:06 ` [PATCH v12 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson 2023-03-23 0:06 ` [PATCH v12 10/15] spi: dw: Add support " Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 11/15] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 12/15] mmc: sdhci-cadence: Support device specific init during probe Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 10:42 ` Andy Shevchenko 2023-03-23 10:42 ` Andy Shevchenko 2023-03-23 0:06 ` [PATCH v12 14/15] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 9:04 ` Philipp Zabel 2023-03-23 9:04 ` Philipp Zabel 2023-03-23 0:06 ` [PATCH v12 15/15] soc: amd: Add support for AMD Pensando SoC Controller Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 11:06 ` Andy Shevchenko 2023-03-23 11:06 ` Andy Shevchenko 2023-03-31 22:26 ` Brad Larson 2023-03-31 22:26 ` Brad Larson
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230323000657.28664-10-blarson@amd.com \ --to=blarson@amd.com \ --cc=adrian.hunter@intel.com \ --cc=alcooperx@gmail.com \ --cc=andy.shevchenko@gmail.com \ --cc=arnd@arndb.de \ --cc=brendan.higgins@linux.dev \ --cc=briannorris@chromium.org \ --cc=brijeshkumar.singh@amd.com \ --cc=broonie@kernel.org \ --cc=catalin.marinas@arm.com \ --cc=davidgow@google.com \ --cc=devicetree@vger.kernel.org \ --cc=fancer.lancer@gmail.com \ --cc=gerg@linux-m68k.org \ --cc=gsomlo@gmail.com \ --cc=krzk@kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=lee.jones@linaro.org \ --cc=lee@kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mmc@vger.kernel.org \ --cc=linux-spi@vger.kernel.org \ --cc=p.yadav@ti.com \ --cc=p.zabel@pengutronix.de \ --cc=piotrs@cadence.com \ --cc=rdunlap@infradead.org \ --cc=robh+dt@kernel.org \ --cc=samuel@sholland.org \ --cc=skhan@linuxfoundation.org \ --cc=suravee.suthikulpanit@amd.com \ --cc=thomas.lendacky@amd.com \ --cc=tonyhuang.sunplus@gmail.com \ --cc=ulf.hansson@linaro.org \ --cc=vaishnav.a@ti.com \ --cc=will@kernel.org \ --cc=yamada.masahiro@socionext.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.