From: Brad Larson <blarson@amd.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <adrian.hunter@intel.com>, <alcooperx@gmail.com>, <andy.shevchenko@gmail.com>, <arnd@arndb.de>, <blarson@amd.com>, <brendan.higgins@linux.dev>, <briannorris@chromium.org>, <brijeshkumar.singh@amd.com>, <catalin.marinas@arm.com>, <davidgow@google.com>, <gsomlo@gmail.com>, <gerg@linux-m68k.org>, <krzk@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <lee@kernel.org>, <lee.jones@linaro.org>, <broonie@kernel.org>, <yamada.masahiro@socionext.com>, <p.zabel@pengutronix.de>, <piotrs@cadence.com>, <p.yadav@ti.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <fancer.lancer@gmail.com>, <skhan@linuxfoundation.org>, <suravee.suthikulpanit@amd.com>, <thomas.lendacky@amd.com>, <tonyhuang.sunplus@gmail.com>, <ulf.hansson@linaro.org>, <vaishnav.a@ti.com>, <will@kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH v12 14/15] mmc: sdhci-cadence: Support mmc hardware reset Date: Wed, 22 Mar 2023 17:06:56 -0700 [thread overview] Message-ID: <20230323000657.28664-15-blarson@amd.com> (raw) In-Reply-To: <20230323000657.28664-1-blarson@amd.com> Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson <blarson@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> --- v9 changes: - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() --- drivers/mmc/host/sdhci-cadence.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c0024d1e69a8..0d8db1a54729 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include <linux/mmc/mmc.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/reset.h> #include "sdhci-pltfm.h" @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -455,6 +457,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 3us for good measure */ + udelay(3); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -518,6 +536,15 @@ static int sdhci_cdns_probe(struct platform_device *pdev) if (ret) goto free; + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->rst_hw)) + return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw), + "reset controller error\n"); + if (priv->rst_hw) + host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset; + } + ret = sdhci_add_host(host); if (ret) goto free; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Brad Larson <blarson@amd.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <adrian.hunter@intel.com>, <alcooperx@gmail.com>, <andy.shevchenko@gmail.com>, <arnd@arndb.de>, <blarson@amd.com>, <brendan.higgins@linux.dev>, <briannorris@chromium.org>, <brijeshkumar.singh@amd.com>, <catalin.marinas@arm.com>, <davidgow@google.com>, <gsomlo@gmail.com>, <gerg@linux-m68k.org>, <krzk@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <lee@kernel.org>, <lee.jones@linaro.org>, <broonie@kernel.org>, <yamada.masahiro@socionext.com>, <p.zabel@pengutronix.de>, <piotrs@cadence.com>, <p.yadav@ti.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <fancer.lancer@gmail.com>, <skhan@linuxfoundation.org>, <suravee.suthikulpanit@amd.com>, <thomas.lendacky@amd.com>, <tonyhuang.sunplus@gmail.com>, <ulf.hansson@linaro.org>, <vaishnav.a@ti.com>, <will@kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH v12 14/15] mmc: sdhci-cadence: Support mmc hardware reset Date: Wed, 22 Mar 2023 17:06:56 -0700 [thread overview] Message-ID: <20230323000657.28664-15-blarson@amd.com> (raw) In-Reply-To: <20230323000657.28664-1-blarson@amd.com> Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson <blarson@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> --- v9 changes: - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() --- drivers/mmc/host/sdhci-cadence.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c0024d1e69a8..0d8db1a54729 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include <linux/mmc/mmc.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/reset.h> #include "sdhci-pltfm.h" @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -455,6 +457,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 3us for good measure */ + udelay(3); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -518,6 +536,15 @@ static int sdhci_cdns_probe(struct platform_device *pdev) if (ret) goto free; + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->rst_hw)) + return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw), + "reset controller error\n"); + if (priv->rst_hw) + host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset; + } + ret = sdhci_add_host(host); if (ret) goto free; -- 2.17.1
next prev parent reply other threads:[~2023-03-23 0:11 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-23 0:06 [PATCH v12 00/15] Support AMD Pensando Elba SoC Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 01/15] dt-bindings: arm: add AMD Pensando boards Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 6:36 ` Krzysztof Kozlowski 2023-03-23 6:36 ` Krzysztof Kozlowski 2023-03-23 0:06 ` [PATCH v12 03/15] dt-bindings: spi: cdns: Add compatible for " Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 05/15] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 06/15] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 07/15] arm64: Add config for AMD Pensando SoC platforms Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 08/15] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 10/15] spi: dw: Add support " Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 11/15] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 12/15] mmc: sdhci-cadence: Support device specific init during probe Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 0:06 ` [PATCH v12 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 10:42 ` Andy Shevchenko 2023-03-23 10:42 ` Andy Shevchenko 2023-03-23 0:06 ` Brad Larson [this message] 2023-03-23 0:06 ` [PATCH v12 14/15] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson 2023-03-23 9:04 ` Philipp Zabel 2023-03-23 9:04 ` Philipp Zabel 2023-03-23 0:06 ` [PATCH v12 15/15] soc: amd: Add support for AMD Pensando SoC Controller Brad Larson 2023-03-23 0:06 ` Brad Larson 2023-03-23 11:06 ` Andy Shevchenko 2023-03-23 11:06 ` Andy Shevchenko 2023-03-31 22:26 ` Brad Larson 2023-03-31 22:26 ` Brad Larson
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