From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: Frank Li <Frank.Li@nxp.com> Cc: krzysztof.kozlowski@linaro.org, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: Re: [PATCH v7 16/16] PCI: imx6: Add iMX95 Endpoint (EP) function support Date: Sun, 7 Jan 2024 11:56:54 +0530 [thread overview] Message-ID: <20240107062654.GO3416@thinkpad> (raw) In-Reply-To: <20231227182727.1747435-17-Frank.Li@nxp.com> On Wed, Dec 27, 2023 at 01:27:27PM -0500, Frank Li wrote: Subject: PCI: imx6: Add iMX95 Endpoint (EP) support > Add iMX95 EP function support and add 64bit address support. Internal bus Remove 'function' as that refers to endpoint function. > bridge for PCI support 64bit dma address in iMX95. So set call > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). > 'Hence, call dma_set_mask_and_coherent() to set 64 bit DMA mask.' > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > > Notes: > Change from v3 to v4 > - change align to 4k for imx95 > Change from v1 to v3 > - new patches at v3 > > drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 6a58fd63a9dd2..00ec59867c17b 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -75,6 +75,7 @@ enum imx6_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX95_EP, > }; > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > @@ -84,6 +85,7 @@ enum imx6_pcie_variants { > #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) > #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) > #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) > +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > break; > case IMX7D: > case IMX95: > + case IMX95_EP: > break; > case IMX8MM: > case IMX8MM_EP: > @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +/* > + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > + * ================================================================================================ > + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit I couldn't understand above. And not aligned properly. > + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > + * BAR4 | Enable | 32-bit | 1M | Programmable Size > + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > + */ > +static const struct pci_epc_features imx95_pcie_epc_features = { > + .msi_capable = true, > + .bar_fixed_size[1] = SZ_64K, > + .align = SZ_4K, > +}; > + > static const struct pci_epc_features* > imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) > { > @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; > > + /* Use FIXME here. - Mani > + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from > + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed > + * after all dts added "dbi2" reg. > + */ > + if (imx6_pcie->drvdata->variant == IMX95_EP) > + pci->dbi_base2 = NULL; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > @@ -1355,6 +1383,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) > "unable to find iomuxc registers\n"); > } > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > + > /* Grab PCIe PHY Tx Settings */ > if (of_property_read_u32(node, "fsl,tx-deemph-gen1", > &imx6_pcie->tx_deemph_gen1)) > @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .epc_features = &imx8m_pcie_epc_features, > }, > + [IMX95_EP] = { > + .variant = IMX95_EP, > + .flags = IMX6_PCIE_FLAG_HAS_SERDES | > + IMX6_PCIE_FLAG_SUPPORT_64BIT, > + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, > + .ltssm_off = IMX95_PE0_GEN_CTRL_3, > + .ltssm_mask = IMX95_PCIE_LTSSM_EN, > + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > + .init_phy = imx95_pcie_init_phy, > + .epc_features = &imx95_pcie_epc_features, > + .mode = DW_PCIE_EP_TYPE, > + }, > }; > > static const struct of_device_id imx6_pcie_of_match[] = { > @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
WARNING: multiple messages have this Message-ID (diff)
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: Frank Li <Frank.Li@nxp.com> Cc: krzysztof.kozlowski@linaro.org, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: Re: [PATCH v7 16/16] PCI: imx6: Add iMX95 Endpoint (EP) function support Date: Sun, 7 Jan 2024 11:56:54 +0530 [thread overview] Message-ID: <20240107062654.GO3416@thinkpad> (raw) In-Reply-To: <20231227182727.1747435-17-Frank.Li@nxp.com> On Wed, Dec 27, 2023 at 01:27:27PM -0500, Frank Li wrote: Subject: PCI: imx6: Add iMX95 Endpoint (EP) support > Add iMX95 EP function support and add 64bit address support. Internal bus Remove 'function' as that refers to endpoint function. > bridge for PCI support 64bit dma address in iMX95. So set call > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). > 'Hence, call dma_set_mask_and_coherent() to set 64 bit DMA mask.' > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > > Notes: > Change from v3 to v4 > - change align to 4k for imx95 > Change from v1 to v3 > - new patches at v3 > > drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 6a58fd63a9dd2..00ec59867c17b 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -75,6 +75,7 @@ enum imx6_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX95_EP, > }; > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > @@ -84,6 +85,7 @@ enum imx6_pcie_variants { > #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) > #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) > #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) > +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > break; > case IMX7D: > case IMX95: > + case IMX95_EP: > break; > case IMX8MM: > case IMX8MM_EP: > @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +/* > + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > + * ================================================================================================ > + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit I couldn't understand above. And not aligned properly. > + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > + * BAR4 | Enable | 32-bit | 1M | Programmable Size > + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > + */ > +static const struct pci_epc_features imx95_pcie_epc_features = { > + .msi_capable = true, > + .bar_fixed_size[1] = SZ_64K, > + .align = SZ_4K, > +}; > + > static const struct pci_epc_features* > imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) > { > @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; > > + /* Use FIXME here. - Mani > + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from > + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed > + * after all dts added "dbi2" reg. > + */ > + if (imx6_pcie->drvdata->variant == IMX95_EP) > + pci->dbi_base2 = NULL; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > @@ -1355,6 +1383,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) > "unable to find iomuxc registers\n"); > } > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > + > /* Grab PCIe PHY Tx Settings */ > if (of_property_read_u32(node, "fsl,tx-deemph-gen1", > &imx6_pcie->tx_deemph_gen1)) > @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .epc_features = &imx8m_pcie_epc_features, > }, > + [IMX95_EP] = { > + .variant = IMX95_EP, > + .flags = IMX6_PCIE_FLAG_HAS_SERDES | > + IMX6_PCIE_FLAG_SUPPORT_64BIT, > + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, > + .ltssm_off = IMX95_PE0_GEN_CTRL_3, > + .ltssm_mask = IMX95_PCIE_LTSSM_EN, > + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > + .init_phy = imx95_pcie_init_phy, > + .epc_features = &imx95_pcie_epc_features, > + .mode = DW_PCIE_EP_TYPE, > + }, > }; > > static const struct of_device_id imx6_pcie_of_match[] = { > @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-07 6:27 UTC|newest] Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-12-27 18:27 [PATCH v7 00/16] PCI: imx6: Clean up and add imx95 pci support Frank Li 2023-12-27 18:27 ` Frank Li 2023-12-27 18:27 ` [PATCH v7 01/16] PCI: imx6: Simplify clock handling by using bulk_clk_*() function Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-02 8:47 ` Marco Felsch 2024-01-02 8:47 ` Marco Felsch 2024-01-03 17:02 ` Frank Li 2024-01-03 17:02 ` Frank Li 2024-01-04 10:07 ` Marco Felsch 2024-01-04 10:07 ` Marco Felsch 2024-01-06 15:27 ` Manivannan Sadhasivam 2024-01-06 15:27 ` Manivannan Sadhasivam 2024-01-06 16:48 ` Frank Li 2024-01-06 16:48 ` Frank Li 2024-01-07 3:02 ` Manivannan Sadhasivam 2024-01-07 3:02 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 02/16] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-06 15:33 ` Manivannan Sadhasivam 2024-01-06 15:33 ` Manivannan Sadhasivam 2024-01-06 16:50 ` Frank Li 2024-01-06 16:50 ` Frank Li 2024-01-07 3:04 ` Manivannan Sadhasivam 2024-01-07 3:04 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 03/16] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Frank Li 2023-12-27 18:27 ` Frank Li 2023-12-27 18:27 ` [PATCH v7 04/16] dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 3:15 ` Manivannan Sadhasivam 2024-01-07 3:15 ` Manivannan Sadhasivam 2024-01-07 4:47 ` Frank Li 2024-01-07 4:47 ` Frank Li 2024-01-07 5:19 ` Manivannan Sadhasivam 2024-01-07 5:19 ` Manivannan Sadhasivam 2024-01-07 5:38 ` Frank Li 2024-01-07 5:38 ` Frank Li 2024-01-07 6:29 ` Manivannan Sadhasivam 2024-01-07 6:29 ` Manivannan Sadhasivam 2024-01-09 3:49 ` Rob Herring 2024-01-09 3:49 ` Rob Herring 2024-01-09 3:49 ` Rob Herring 2024-01-09 3:49 ` Rob Herring 2023-12-27 18:27 ` [PATCH v7 05/16] PCI: imx6: Using "linux,pci-domain" as slot ID Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 3:22 ` Manivannan Sadhasivam 2024-01-07 3:22 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 06/16] PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 3:24 ` Manivannan Sadhasivam 2024-01-07 3:24 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 07/16] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 5:16 ` Manivannan Sadhasivam 2024-01-07 5:16 ` Manivannan Sadhasivam 2024-01-07 5:32 ` Frank Li 2024-01-07 5:32 ` Frank Li 2024-01-07 5:35 ` Manivannan Sadhasivam 2024-01-07 5:35 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 08/16] PCI: imx6: Simplify switch-case logic by involve init_phy callback Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 5:33 ` Manivannan Sadhasivam 2024-01-07 5:33 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 09/16] dt-bindings: imx6q-pcie: Clean up irrationality clocks check Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 5:34 ` Manivannan Sadhasivam 2024-01-07 5:34 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 10/16] dt-bindings: imx6q-pcie: restruct reg and reg-name Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 5:35 ` Manivannan Sadhasivam 2024-01-07 5:35 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 11/16] dt-bindings: imx6q-pcie: Add imx95 pcie compatible string Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-02 16:03 ` Rob Herring 2024-01-02 16:03 ` Rob Herring 2023-12-27 18:27 ` [PATCH v7 12/16] PCI: imx6: Add iMX95 PCIe support Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 5:51 ` Manivannan Sadhasivam 2024-01-07 5:51 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 13/16] PCI: imx6: Clean up get addr_space code Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 5:55 ` Manivannan Sadhasivam 2024-01-07 5:55 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 14/16] PCI: imx6: Add epc_features in imx6_pcie_drvdata Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 6:16 ` Manivannan Sadhasivam 2024-01-07 6:16 ` Manivannan Sadhasivam 2023-12-27 18:27 ` [PATCH v7 15/16] dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-09 3:53 ` Rob Herring 2024-01-09 3:53 ` Rob Herring 2023-12-27 18:27 ` [PATCH v7 16/16] PCI: imx6: Add iMX95 Endpoint (EP) function support Frank Li 2023-12-27 18:27 ` Frank Li 2024-01-07 6:26 ` Manivannan Sadhasivam [this message] 2024-01-07 6:26 ` Manivannan Sadhasivam 2024-01-08 17:39 ` Frank Li 2024-01-08 17:39 ` Frank Li
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