Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

From: Conor Dooley <conor.dooley@microchip.com>
To: Conor Dooley <conor@kernel.org>
Cc: Joshua Yeong <joshua.yeong@starfivetech.com>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <geert+renesas@glider.be>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<alexghiti@rivosinc.com>, <evan@rivosinc.com>,
	<ajones@ventanamicro.com>, <heiko@sntech.de>, <guoren@kernel.org>,
	<uwu@icenowy.me>, <jszhang@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
	<leyfoon.tan@starfivetech.com>, <jeeheng.sia@starfivetech.com>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
Date: Wed, 20 Mar 2024 08:08:41 +0000	[thread overview]
Message-ID: <20240320-implement-finishing-136eae51d659@wendy> (raw)
In-Reply-To: <20240317-viral-handcraft-12b2519ff1be@spud>

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On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
> > conventional CMO method. This driver provides the cache handling on StarFive
> > RISC-V SoC.
> 
> Unlike the other "non-conventional" CMO methods, the jh8100 does not
> pre-date the Zicbom extension. Why has that not been implemented?

Stefan pointed out on IRC yesterday that one of the main selling points
is the ease of operating on large ranges.

> How many peripherals on the jh8100 rely on non-coherent DMA?
> 
> Cheers,
> Conor.

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