RE: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

From: Joshua Yeong <joshua.yeong@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>,
	Conor Dooley <conor@kernel.org>
Cc: "paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"geert+renesas@glider.be" <geert+renesas@glider.be>,
	"prabhakar.mahadev-lad.rj@bp.renesas.com"
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
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	"heiko@sntech.de" <heiko@sntech.de>,
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	<krzysztof.kozlowski+dt@linaro.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	JeeHeng Sia <jeeheng.sia@starfivetech.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
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	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
Date: Fri, 22 Mar 2024 06:16:21 +0000	[thread overview]
Message-ID: <SH0PR01MB0841F41082D1B638C6CDCCD1F931A@SH0PR01MB0841.CHNPR01.prod.partner.outlook.cn> (raw)
In-Reply-To: <20240320-implement-finishing-136eae51d659@wendy>

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor.dooley@microchip.com>
> Sent: Wednesday, March 20, 2024 4:09 PM
> To: Conor Dooley <conor@kernel.org>
> Cc: Joshua Yeong <joshua.yeong@starfivetech.com>;
> paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> geert+renesas@glider.be; prabhakar.mahadev-lad.rj@bp.renesas.com;
> alexghiti@rivosinc.com; evan@rivosinc.com; ajones@ventanamicro.com;
> heiko@sntech.de; guoren@kernel.org; uwu@icenowy.me;
> jszhang@kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; JeeHeng
> Sia <jeeheng.sia@starfivetech.com>; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
> 
> On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> > On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > > StarFive's StarLink-500 Cache Controller flush/invalidates cache
> > > using non- conventional CMO method. This driver provides the cache
> > > handling on StarFive RISC-V SoC.
> >
> > Unlike the other "non-conventional" CMO methods, the jh8100 does not
> > pre-date the Zicbom extension. Why has that not been implemented?
> 
> Stefan pointed out on IRC yesterday that one of the main selling points is the
> ease of operating on large ranges.
> 
> > How many peripherals on the jh8100 rely on non-coherent DMA?

JH8100 integrates in-house matured/stable CPU but it is a bit dated today.
However, our newer generation of CPU should already support this extension.

Most of the peripherals are coherent except mainly multimedia peripheral.

Regards,
Joshua

> >
> > Cheers,
> > Conor.
> 