From: Peter Oh <peter.oh@eero.com>
To: zhichen@codeaurora.org
Cc: ath10k@lists.infradead.org, linux-wireless@vger.kernel.org
Subject: Re: [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices"
Date: Wed, 30 Oct 2019 16:01:42 -0700 [thread overview]
Message-ID: <3f108a96-3ea5-79c0-54d5-b2f26a3e0a9a@eero.com> (raw)
In-Reply-To: <8c6d531f6474faf4df55f90185466774@codeaurora.org>
On 10/29/19 11:16 PM, zhichen@codeaurora.org wrote:
> On 2019-10-23 01:16, Peter Oh wrote:
>>
>> How can you say value 0 (I believe it's 64 bytes) DMA burst size
>> causes the symptom and 1 fixes it?
>>
>> Peter
>
> Confirmed from HW team that the configuration controls AXI burst size
> of the RD/WR access to the HOST MEM.
> 0- No split , RAW read/write transfer size from MAC is put out on
> bus as burst length.
> 1- Split at 256 byte boundary
> 2,3- Reserved
>
I would ACK to this change. Although QCA4019 host mem max AXI read/write
registers have different descriptions from above, they say 1 (256-byte)
is default and the values, 0, 2, and 3 are reserved. So changing it back
to 1 is reasonable to me.
Thanks,
Peter
WARNING: multiple messages have this Message-ID (diff)
From: Peter Oh <peter.oh@eero.com>
To: zhichen@codeaurora.org
Cc: linux-wireless@vger.kernel.org, ath10k@lists.infradead.org
Subject: Re: [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices"
Date: Wed, 30 Oct 2019 16:01:42 -0700 [thread overview]
Message-ID: <3f108a96-3ea5-79c0-54d5-b2f26a3e0a9a@eero.com> (raw)
In-Reply-To: <8c6d531f6474faf4df55f90185466774@codeaurora.org>
On 10/29/19 11:16 PM, zhichen@codeaurora.org wrote:
> On 2019-10-23 01:16, Peter Oh wrote:
>>
>> How can you say value 0 (I believe it's 64 bytes) DMA burst size
>> causes the symptom and 1 fixes it?
>>
>> Peter
>
> Confirmed from HW team that the configuration controls AXI burst size
> of the RD/WR access to the HOST MEM.
> 0- No split , RAW read/write transfer size from MAC is put out on
> bus as burst length.
> 1- Split at 256 byte boundary
> 2,3- Reserved
>
I would ACK to this change. Although QCA4019 host mem max AXI read/write
registers have different descriptions from above, they say 1 (256-byte)
is default and the values, 0, 2, and 3 are reserved. So changing it back
to 1 is reasonable to me.
Thanks,
Peter
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next prev parent reply other threads:[~2019-10-30 23:01 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-22 8:57 [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices" Zhi Chen
2019-10-22 8:57 ` Zhi Chen
2019-10-22 10:07 ` Tom Psyborg
2019-10-22 10:07 ` Tom Psyborg
2019-10-30 2:44 ` zhichen
2019-10-30 2:44 ` zhichen
2019-11-06 10:01 ` Tom Psyborg
2019-11-06 10:01 ` Tom Psyborg
2019-11-07 5:35 ` zhichen
2019-11-07 5:35 ` zhichen
2019-10-22 17:16 ` Peter Oh
2019-10-22 17:16 ` Peter Oh
2019-10-22 18:24 ` Adrian Chadd
2019-10-22 18:24 ` Adrian Chadd
2019-10-30 6:04 ` Peter Oh
2019-10-30 6:04 ` Peter Oh
2019-10-30 6:28 ` zhichen
2019-10-30 6:28 ` zhichen
2019-10-30 6:16 ` zhichen
2019-10-30 6:16 ` zhichen
2019-10-30 23:01 ` Peter Oh [this message]
2019-10-30 23:01 ` Peter Oh
2019-11-03 15:36 ` Tom Psyborg
2019-11-03 15:36 ` Tom Psyborg
2019-11-04 18:41 ` Peter Oh
2019-11-04 18:41 ` Peter Oh
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