From: Peter Oh <peter.oh@eero.com>
To: Tom Psyborg <pozega.tomislav@gmail.com>, zhichen@codeaurora.org
Cc: linux-wireless@vger.kernel.org, ath10k@lists.infradead.org
Subject: Re: [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices"
Date: Mon, 4 Nov 2019 10:41:58 -0800 [thread overview]
Message-ID: <3f3b683f-789a-9b7f-a854-0fdcc20819d1@eero.com> (raw)
In-Reply-To: <CAKR_QV+Qh_ErYduYoD8=u_i-y=cbKSJkkajtKxsJ5ML8-Z79EQ@mail.gmail.com>
On 11/3/19 7:36 AM, Tom Psyborg wrote:
> On 30/10/2019, zhichen@codeaurora.org <zhichen@codeaurora.org> wrote:
>> On 2019-10-23 01:16, Peter Oh wrote:
>>> How can you say value 0 (I believe it's 64 bytes) DMA burst size
>>> causes the symptom and 1 fixes it?
>>>
>>> Peter
>> Confirmed from HW team that the configuration controls AXI burst size of
>> the RD/WR access to the HOST MEM.
>> 0- No split , RAW read/write transfer size from MAC is put out on bus as
>> burst length.
>> 1- Split at 256 byte boundary
>> 2,3- Reserved
>>
>> That's why we see issue with value 0.
>>
>> Zhi
>>
>> _______________________________________________
>> ath10k mailing list
>> ath10k@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/ath10k
>>
> is this true for both wave1 and wave2 ? at least per this commit
> message: ath10k: Fix DMA burst size
> it's suppose to be:
>
> 0 - 128B max (not sure if this means 128B static, or any size between 0 and 128)
> 1 - 256B
I didn't check other chipsets, but QCA4019 registers say AXI read/write
burst size is 64 bytes for 0.
WARNING: multiple messages have this Message-ID (diff)
From: Peter Oh <peter.oh@eero.com>
To: Tom Psyborg <pozega.tomislav@gmail.com>, zhichen@codeaurora.org
Cc: linux-wireless@vger.kernel.org, ath10k@lists.infradead.org
Subject: Re: [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices"
Date: Mon, 4 Nov 2019 10:41:58 -0800 [thread overview]
Message-ID: <3f3b683f-789a-9b7f-a854-0fdcc20819d1@eero.com> (raw)
In-Reply-To: <CAKR_QV+Qh_ErYduYoD8=u_i-y=cbKSJkkajtKxsJ5ML8-Z79EQ@mail.gmail.com>
On 11/3/19 7:36 AM, Tom Psyborg wrote:
> On 30/10/2019, zhichen@codeaurora.org <zhichen@codeaurora.org> wrote:
>> On 2019-10-23 01:16, Peter Oh wrote:
>>> How can you say value 0 (I believe it's 64 bytes) DMA burst size
>>> causes the symptom and 1 fixes it?
>>>
>>> Peter
>> Confirmed from HW team that the configuration controls AXI burst size of
>> the RD/WR access to the HOST MEM.
>> 0- No split , RAW read/write transfer size from MAC is put out on bus as
>> burst length.
>> 1- Split at 256 byte boundary
>> 2,3- Reserved
>>
>> That's why we see issue with value 0.
>>
>> Zhi
>>
>> _______________________________________________
>> ath10k mailing list
>> ath10k@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/ath10k
>>
> is this true for both wave1 and wave2 ? at least per this commit
> message: ath10k: Fix DMA burst size
> it's suppose to be:
>
> 0 - 128B max (not sure if this means 128B static, or any size between 0 and 128)
> 1 - 256B
I didn't check other chipsets, but QCA4019 registers say AXI read/write
burst size is 64 bytes for 0.
_______________________________________________
ath10k mailing list
ath10k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath10k
next prev parent reply other threads:[~2019-11-04 18:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-22 8:57 [PATCH RFC] Revert "ath10k: fix DMA related firmware crashes on multiple devices" Zhi Chen
2019-10-22 8:57 ` Zhi Chen
2019-10-22 10:07 ` Tom Psyborg
2019-10-22 10:07 ` Tom Psyborg
2019-10-30 2:44 ` zhichen
2019-10-30 2:44 ` zhichen
2019-11-06 10:01 ` Tom Psyborg
2019-11-06 10:01 ` Tom Psyborg
2019-11-07 5:35 ` zhichen
2019-11-07 5:35 ` zhichen
2019-10-22 17:16 ` Peter Oh
2019-10-22 17:16 ` Peter Oh
2019-10-22 18:24 ` Adrian Chadd
2019-10-22 18:24 ` Adrian Chadd
2019-10-30 6:04 ` Peter Oh
2019-10-30 6:04 ` Peter Oh
2019-10-30 6:28 ` zhichen
2019-10-30 6:28 ` zhichen
2019-10-30 6:16 ` zhichen
2019-10-30 6:16 ` zhichen
2019-10-30 23:01 ` Peter Oh
2019-10-30 23:01 ` Peter Oh
2019-11-03 15:36 ` Tom Psyborg
2019-11-03 15:36 ` Tom Psyborg
2019-11-04 18:41 ` Peter Oh [this message]
2019-11-04 18:41 ` Peter Oh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3f3b683f-789a-9b7f-a854-0fdcc20819d1@eero.com \
--to=peter.oh@eero.com \
--cc=ath10k@lists.infradead.org \
--cc=linux-wireless@vger.kernel.org \
--cc=pozega.tomislav@gmail.com \
--cc=zhichen@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.