From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
Date: Tue, 30 Jul 2019 16:35:34 -0700 [thread overview]
Message-ID: <4dad98dcc3b6a3f3a5097922494b0521c60570c7.1564529681.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564529681.git.alistair.francis@wdc.com>
From: Atish Patra <atish.patra@wdc.com>
As per the RISC-V spec, Floating Point registers are named as f0..f31
so lets fix the register names accordingly.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd20a..af1e9b7690 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = {
};
const char * const riscv_fpr_regnames[] = {
- "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
- "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
- "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
- "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
};
const char * const riscv_excp_names[] = {
--
2.22.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
Date: Tue, 30 Jul 2019 16:35:34 -0700 [thread overview]
Message-ID: <4dad98dcc3b6a3f3a5097922494b0521c60570c7.1564529681.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564529681.git.alistair.francis@wdc.com>
From: Atish Patra <atish.patra@wdc.com>
As per the RISC-V spec, Floating Point registers are named as f0..f31
so lets fix the register names accordingly.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd20a..af1e9b7690 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = {
};
const char * const riscv_fpr_regnames[] = {
- "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
- "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
- "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
- "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
};
const char * const riscv_excp_names[] = {
--
2.22.0
next prev parent reply other threads:[~2019-07-30 23:43 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 23:35 [Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 2/5] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-05 6:59 ` [Qemu-devel] " Chih-Min Chao
2019-08-05 6:59 ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-05 6:19 ` [Qemu-devel] " Chih-Min Chao
2019-08-05 6:19 ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 23:35 ` Alistair Francis [this message]
2019-07-30 23:35 ` [Qemu-riscv] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names Alistair Francis
2019-08-12 23:08 ` [Qemu-devel] " Palmer Dabbelt
2019-08-12 23:08 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-13 17:06 ` [Qemu-devel] " Alistair Francis
2019-08-13 17:06 ` [Qemu-riscv] " Alistair Francis
2019-08-14 18:07 ` [Qemu-devel] " Palmer Dabbelt
2019-08-14 18:07 ` [Qemu-riscv] " Palmer Dabbelt
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