From: Palmer Dabbelt <palmer@sifive.com>
To: alistair23@gmail.com
Cc: qemu-riscv@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
Date: Wed, 14 Aug 2019 11:07:16 -0700 (PDT) [thread overview]
Message-ID: <mhng-dea7d47b-8f66-44b1-84c8-6b5a04ee0b86@palmer-si-x1c4> (raw)
In-Reply-To: <CAKmqyKOikOJCp0d7ivt2tvd9P56xGZKEh_OrGBf4qo0hQOidJA@mail.gmail.com>
On Tue, 13 Aug 2019 10:06:58 PDT (-0700), alistair23@gmail.com wrote:
> On Mon, Aug 12, 2019 at 4:08 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
>> > From: Atish Patra <atish.patra@wdc.com>
>> >
>> > As per the RISC-V spec, Floating Point registers are named as f0..f31
>> > so lets fix the register names accordingly.
>> >
>> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > ---
>> > target/riscv/cpu.c | 8 ++++----
>> > 1 file changed, 4 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> > index f8d07bd20a..af1e9b7690 100644
>> > --- a/target/riscv/cpu.c
>> > +++ b/target/riscv/cpu.c
>> > @@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = {
>> > };
>> >
>> > const char * const riscv_fpr_regnames[] = {
>> > - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
>> > - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
>> > - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
>> > - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
>> > + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
>> > + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
>> > + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
>> > + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
>> > };
>> >
>> > const char * const riscv_excp_names[] = {
>>
>> I actually don't think this one is right: riscv_int_regnames uses the ABI
>> names, so this should match. I'd be OK switching both of them, but not just
>> one.
>
> I like that the int registers use the ABI names though, as I find that useful.
>
> What about we change the registers to use both? As in something like
> x0/zero for all registers?
>
> The disadvantage is that it's a little longer, but it seems the most useful.
I'm fine with that, as long as it doesn't show up in the GDB XML stuff as that
will likely cause issues.
> Alistair
>
>>
>> I've queued the other four patches.
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com>
To: alistair23@gmail.com
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [Qemu-riscv] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
Date: Wed, 14 Aug 2019 11:07:16 -0700 (PDT) [thread overview]
Message-ID: <mhng-dea7d47b-8f66-44b1-84c8-6b5a04ee0b86@palmer-si-x1c4> (raw)
In-Reply-To: <CAKmqyKOikOJCp0d7ivt2tvd9P56xGZKEh_OrGBf4qo0hQOidJA@mail.gmail.com>
On Tue, 13 Aug 2019 10:06:58 PDT (-0700), alistair23@gmail.com wrote:
> On Mon, Aug 12, 2019 at 4:08 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
>> > From: Atish Patra <atish.patra@wdc.com>
>> >
>> > As per the RISC-V spec, Floating Point registers are named as f0..f31
>> > so lets fix the register names accordingly.
>> >
>> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > ---
>> > target/riscv/cpu.c | 8 ++++----
>> > 1 file changed, 4 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> > index f8d07bd20a..af1e9b7690 100644
>> > --- a/target/riscv/cpu.c
>> > +++ b/target/riscv/cpu.c
>> > @@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = {
>> > };
>> >
>> > const char * const riscv_fpr_regnames[] = {
>> > - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
>> > - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
>> > - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
>> > - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
>> > + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
>> > + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
>> > + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
>> > + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
>> > };
>> >
>> > const char * const riscv_excp_names[] = {
>>
>> I actually don't think this one is right: riscv_int_regnames uses the ABI
>> names, so this should match. I'd be OK switching both of them, but not just
>> one.
>
> I like that the int registers use the ABI names though, as I find that useful.
>
> What about we change the registers to use both? As in something like
> x0/zero for all registers?
>
> The disadvantage is that it's a little longer, but it seems the most useful.
I'm fine with that, as long as it doesn't show up in the GDB XML stuff as that
will likely cause issues.
> Alistair
>
>>
>> I've queued the other four patches.
next prev parent reply other threads:[~2019-08-14 18:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 23:35 [Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 2/5] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-05 6:59 ` [Qemu-devel] " Chih-Min Chao
2019-08-05 6:59 ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-05 6:19 ` [Qemu-devel] " Chih-Min Chao
2019-08-05 6:19 ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-12 23:08 ` [Qemu-devel] " Palmer Dabbelt
2019-08-12 23:08 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-13 17:06 ` [Qemu-devel] " Alistair Francis
2019-08-13 17:06 ` [Qemu-riscv] " Alistair Francis
2019-08-14 18:07 ` Palmer Dabbelt [this message]
2019-08-14 18:07 ` Palmer Dabbelt
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