From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs
Date: Tue, 30 Jul 2019 16:35:19 -0700 [thread overview]
Message-ID: <868a01ec5dd656f26ebb06d0b4313452f66206e3.1564529681.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564529681.git.alistair.francis@wdc.com>
Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b6126af..f027be7f16 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,10 +340,8 @@ restart:
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
- /* add write permission on stores or if the page is already dirty,
- so that we TLB miss on later writes to update the dirty bit */
- if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ /* add write permission on stores */
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
--
2.22.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs
Date: Tue, 30 Jul 2019 16:35:19 -0700 [thread overview]
Message-ID: <868a01ec5dd656f26ebb06d0b4313452f66206e3.1564529681.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1564529681.git.alistair.francis@wdc.com>
Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e32b6126af..f027be7f16 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,10 +340,8 @@ restart:
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
- /* add write permission on stores or if the page is already dirty,
- so that we TLB miss on later writes to update the dirty bit */
- if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ /* add write permission on stores */
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
--
2.22.0
next prev parent reply other threads:[~2019-07-30 23:39 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 23:35 [Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` Alistair Francis [this message]
2019-07-30 23:35 ` [Qemu-riscv] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 2/5] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-05 6:59 ` [Qemu-devel] " Chih-Min Chao
2019-08-05 6:59 ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-05 6:19 ` [Qemu-devel] " Chih-Min Chao
2019-08-05 6:19 ` [Qemu-riscv] " Chih-Min Chao
2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names Alistair Francis
2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis
2019-08-12 23:08 ` [Qemu-devel] " Palmer Dabbelt
2019-08-12 23:08 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-13 17:06 ` [Qemu-devel] " Alistair Francis
2019-08-13 17:06 ` [Qemu-riscv] " Alistair Francis
2019-08-14 18:07 ` [Qemu-devel] " Palmer Dabbelt
2019-08-14 18:07 ` [Qemu-riscv] " Palmer Dabbelt
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