From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Richard Henderson <richard.henderson@linaro.org>,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com
Subject: Re: [PATCH v2 3/6] target/riscv: add support for zfinx
Date: Sat, 1 Jan 2022 14:05:56 +0800 [thread overview]
Message-ID: <7096a296-f1c2-44e7-d084-1c473b50a711@iscas.ac.cn> (raw)
In-Reply-To: <a522f7f6-b6ad-02de-dabc-0511740aef83@linaro.org>
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在 2022/1/1 上午4:06, Richard Henderson 写道:
> On 12/30/21 7:23 PM, Weiwei Li wrote:
>> + if (reg_num != 0) {
>> + switch (get_ol(ctx)) {
>
> Oh, you should be using get_xl here and elsewhere in this patch, not
> get_ol.
Sorry. I don't know the difference between get_xl and get_ol. From gpr
register read/write function, It seems get_ol is used in register read,
and get_xl is used in register write.
However, "ctx->ol= ctx->xl;" is executed before translate instruction.
"
>
>
> r~
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next prev parent reply other threads:[~2022-01-01 6:08 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-31 3:23 [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 6:28 ` Bin Meng
2021-12-31 6:28 ` Bin Meng
2021-12-31 3:23 ` [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 19:56 ` Richard Henderson
2022-01-01 5:55 ` Weiwei Li
2022-01-01 19:46 ` Richard Henderson
2022-01-02 5:53 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 3/6] target/riscv: add support for zfinx Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 20:03 ` Richard Henderson
2021-12-31 20:06 ` Richard Henderson
2022-01-01 6:05 ` Weiwei Li [this message]
2022-01-01 19:48 ` Richard Henderson
2022-01-02 5:56 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 4/6] target/riscv: add support for zdinx Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 20:07 ` Richard Henderson
2022-01-01 6:06 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 20:08 ` Richard Henderson
2021-12-31 3:23 ` [PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li
2021-12-31 3:23 ` Weiwei Li
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