From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>, lazyparser@gmail.com, ardxwe@gmail.com Subject: [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Date: Fri, 31 Dec 2021 11:23:31 +0800 [thread overview] Message-ID: <20211231032337.15579-1-liweiwei@iscas.ac.cn> (raw) This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0.0-rc), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. Specification: https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v2 To test this implementation, specify cpu argument with 'Zfinx =true,Zdinx=true,Zhinx=true,Zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/ v2: * hardwire mstatus.FS to zero when enable zfinx * do register-pair check at the begin of translation * optimize partial implemention as suggested liweiwei (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv/cpu.c | 20 ++ target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c | 24 +- target/riscv/fpu_helper.c | 178 ++++++------ target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 319 ++++++++++++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- target/riscv/internals.h | 32 ++- target/riscv/translate.c | 161 +++++++++++ 11 files changed, 1023 insertions(+), 371 deletions(-) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Date: Fri, 31 Dec 2021 11:23:31 +0800 [thread overview] Message-ID: <20211231032337.15579-1-liweiwei@iscas.ac.cn> (raw) This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0.0-rc), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. Specification: https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v2 To test this implementation, specify cpu argument with 'Zfinx =true,Zdinx=true,Zhinx=true,Zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/ v2: * hardwire mstatus.FS to zero when enable zfinx * do register-pair check at the begin of translation * optimize partial implemention as suggested liweiwei (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv/cpu.c | 20 ++ target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c | 24 +- target/riscv/fpu_helper.c | 178 ++++++------ target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 319 ++++++++++++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- target/riscv/internals.h | 32 ++- target/riscv/translate.c | 161 +++++++++++ 11 files changed, 1023 insertions(+), 371 deletions(-) -- 2.17.1
next reply other threads:[~2021-12-31 3:27 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-31 3:23 Weiwei Li [this message] 2021-12-31 3:23 ` [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li 2021-12-31 3:23 ` [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 6:28 ` Bin Meng 2021-12-31 6:28 ` Bin Meng 2021-12-31 3:23 ` [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 19:56 ` Richard Henderson 2022-01-01 5:55 ` Weiwei Li 2022-01-01 19:46 ` Richard Henderson 2022-01-02 5:53 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 3/6] target/riscv: add support for zfinx Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 20:03 ` Richard Henderson 2021-12-31 20:06 ` Richard Henderson 2022-01-01 6:05 ` Weiwei Li 2022-01-01 19:48 ` Richard Henderson 2022-01-02 5:56 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 4/6] target/riscv: add support for zdinx Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 20:07 ` Richard Henderson 2022-01-01 6:06 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 20:08 ` Richard Henderson 2021-12-31 3:23 ` [PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li 2021-12-31 3:23 ` Weiwei Li
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