From: Bin Meng <bmeng.cn@gmail.com> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: lazyparser@gmail.com, "open list:RISC-V" <qemu-riscv@nongnu.org>, wangjunqiang <wangjunqiang@iscas.ac.cn>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, ardxwe@gmail.com, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com> Subject: Re: [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Date: Fri, 31 Dec 2021 14:28:23 +0800 [thread overview] Message-ID: <CAEUhbmWG-G96R6k8frQg+cdwkEV84xkQKt3h8zd=Wg1H8_aSfA@mail.gmail.com> (raw) In-Reply-To: <20211231032337.15579-2-liweiwei@iscas.ac.cn> On Fri, Dec 31, 2021 at 11:26 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > From: liweiwei <liweiwei@iscas.ac.cn> You missed here, "From" should match "SoB" name > > Co-authored-by: ardxwe <ardxwe@gmail.com> > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/cpu.c | 12 ++++++++++++ > target/riscv/cpu.h | 4 ++++ > target/riscv/translate.c | 8 ++++++++ > 3 files changed, 24 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..d9ea005724 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -491,6 +491,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > cpu->cfg.ext_d = true; > } > > + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || > + cpu->cfg.ext_zhinxmin) { > + cpu->cfg.ext_zfinx = true; > + } > + > /* Set the ISA extensions, checks should have happened above */ > if (cpu->cfg.ext_i) { > ext |= RVI; > @@ -565,6 +570,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_j) { > ext |= RVJ; > } > + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || > + cpu->cfg.ext_zfhmin)) { > + error_setg(errp, > + "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," > + " 'Zfhmin'"); > + return; > + } > > set_misa(env, env->misa_mxl, ext); > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index dc10f27093..6fba31c5cd 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,8 +315,12 @@ struct RISCVCPU { > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > + bool ext_zdinx; > bool ext_zfh; > bool ext_zfhmin; > + bool ext_zfinx; > + bool ext_zhinx; > + bool ext_zhinxmin; > > char *priv_spec; > char *user_spec; > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 5df6c0d800..8b1cdacf50 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -76,8 +76,12 @@ typedef struct DisasContext { > RISCVMXL ol; > bool virt_enabled; > bool ext_ifencei; > + bool ext_zdinx; > bool ext_zfh; > bool ext_zfhmin; > + bool ext_zfinx; > + bool ext_zhinx; > + bool ext_zhinxmin; > bool hlsx; > /* vector extension */ > bool vill; > @@ -703,8 +707,12 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->misa_ext = env->misa_ext; > ctx->frm = -1; /* unknown rounding mode */ > ctx->ext_ifencei = cpu->cfg.ext_ifencei; > + ctx->ext_zdinx = cpu->cfg.ext_zdinx; > ctx->ext_zfh = cpu->cfg.ext_zfh; > ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; > + ctx->ext_zfinx = cpu->cfg.ext_zfinx; > + ctx->ext_zhinx = cpu->cfg.ext_zhinx; > + ctx->ext_zhinxmin = cpu->cfg.ext_zhinxmin; > ctx->vlen = cpu->cfg.vlen; > ctx->elen = cpu->cfg.elen; > ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); > -- Regards, Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wangjunqiang <wangjunqiang@iscas.ac.cn>, lazyparser@gmail.com, ardxwe@gmail.com Subject: Re: [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Date: Fri, 31 Dec 2021 14:28:23 +0800 [thread overview] Message-ID: <CAEUhbmWG-G96R6k8frQg+cdwkEV84xkQKt3h8zd=Wg1H8_aSfA@mail.gmail.com> (raw) In-Reply-To: <20211231032337.15579-2-liweiwei@iscas.ac.cn> On Fri, Dec 31, 2021 at 11:26 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > From: liweiwei <liweiwei@iscas.ac.cn> You missed here, "From" should match "SoB" name > > Co-authored-by: ardxwe <ardxwe@gmail.com> > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/cpu.c | 12 ++++++++++++ > target/riscv/cpu.h | 4 ++++ > target/riscv/translate.c | 8 ++++++++ > 3 files changed, 24 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..d9ea005724 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -491,6 +491,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > cpu->cfg.ext_d = true; > } > > + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || > + cpu->cfg.ext_zhinxmin) { > + cpu->cfg.ext_zfinx = true; > + } > + > /* Set the ISA extensions, checks should have happened above */ > if (cpu->cfg.ext_i) { > ext |= RVI; > @@ -565,6 +570,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_j) { > ext |= RVJ; > } > + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || > + cpu->cfg.ext_zfhmin)) { > + error_setg(errp, > + "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," > + " 'Zfhmin'"); > + return; > + } > > set_misa(env, env->misa_mxl, ext); > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index dc10f27093..6fba31c5cd 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,8 +315,12 @@ struct RISCVCPU { > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > + bool ext_zdinx; > bool ext_zfh; > bool ext_zfhmin; > + bool ext_zfinx; > + bool ext_zhinx; > + bool ext_zhinxmin; > > char *priv_spec; > char *user_spec; > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 5df6c0d800..8b1cdacf50 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -76,8 +76,12 @@ typedef struct DisasContext { > RISCVMXL ol; > bool virt_enabled; > bool ext_ifencei; > + bool ext_zdinx; > bool ext_zfh; > bool ext_zfhmin; > + bool ext_zfinx; > + bool ext_zhinx; > + bool ext_zhinxmin; > bool hlsx; > /* vector extension */ > bool vill; > @@ -703,8 +707,12 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->misa_ext = env->misa_ext; > ctx->frm = -1; /* unknown rounding mode */ > ctx->ext_ifencei = cpu->cfg.ext_ifencei; > + ctx->ext_zdinx = cpu->cfg.ext_zdinx; > ctx->ext_zfh = cpu->cfg.ext_zfh; > ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; > + ctx->ext_zfinx = cpu->cfg.ext_zfinx; > + ctx->ext_zhinx = cpu->cfg.ext_zhinx; > + ctx->ext_zhinxmin = cpu->cfg.ext_zhinxmin; > ctx->vlen = cpu->cfg.vlen; > ctx->elen = cpu->cfg.elen; > ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); > -- Regards, Bin
next prev parent reply other threads:[~2021-12-31 6:32 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-31 3:23 [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 6:28 ` Bin Meng [this message] 2021-12-31 6:28 ` Bin Meng 2021-12-31 3:23 ` [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 19:56 ` Richard Henderson 2022-01-01 5:55 ` Weiwei Li 2022-01-01 19:46 ` Richard Henderson 2022-01-02 5:53 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 3/6] target/riscv: add support for zfinx Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 20:03 ` Richard Henderson 2021-12-31 20:06 ` Richard Henderson 2022-01-01 6:05 ` Weiwei Li 2022-01-01 19:48 ` Richard Henderson 2022-01-02 5:56 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 4/6] target/riscv: add support for zdinx Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 20:07 ` Richard Henderson 2022-01-01 6:06 ` Weiwei Li 2021-12-31 3:23 ` [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li 2021-12-31 3:23 ` Weiwei Li 2021-12-31 20:08 ` Richard Henderson 2021-12-31 3:23 ` [PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li 2021-12-31 3:23 ` Weiwei Li
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