From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, liweiwei <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com, ardxwe@gmail.com
Subject: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
Date: Fri, 31 Dec 2021 11:23:33 +0800 [thread overview]
Message-ID: <20211231032337.15579-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20211231032337.15579-1-liweiwei@iscas.ac.cn>
From: liweiwei <liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu_helper.c | 6 +++++-
target/riscv/csr.c | 24 +++++++++++++++++++-----
target/riscv/translate.c | 5 +++++
4 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d9ea005724..cc7da446f1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -363,6 +363,10 @@ static void riscv_cpu_reset(DeviceState *dev)
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus &= ~MSTATUS_FS;
+ }
if (env->misa_mxl > MXL_RV32) {
/*
* The reset status of SXL/UXL is undefined, but mstatus is WARL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10f3baba53..a71edee44c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -222,9 +222,13 @@ bool riscv_cpu_vector_enabled(CPURISCVState *env)
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
- uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+ uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM|
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | MSTATUS_VS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ mstatus_mask |= MSTATUS_FS;
+ }
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 146447eac5..de20206b73 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -38,7 +38,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+ if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
+ !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
@@ -234,7 +235,10 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return RISCV_EXCP_NONE;
@@ -251,7 +255,10 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
return RISCV_EXCP_NONE;
@@ -269,7 +276,10 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
@@ -562,9 +572,13 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ mask |= MSTATUS_FS;
+ }
if (riscv_cpu_mxl(env) != MXL_RV32) {
/*
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8b1cdacf50..17bf20a799 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -342,6 +342,11 @@ static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (ctx->ext_zfinx) {
+ return;
+ }
+
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com,
liweiwei <liweiwei@iscas.ac.cn>
Subject: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
Date: Fri, 31 Dec 2021 11:23:33 +0800 [thread overview]
Message-ID: <20211231032337.15579-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20211231032337.15579-1-liweiwei@iscas.ac.cn>
From: liweiwei <liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu_helper.c | 6 +++++-
target/riscv/csr.c | 24 +++++++++++++++++++-----
target/riscv/translate.c | 5 +++++
4 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d9ea005724..cc7da446f1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -363,6 +363,10 @@ static void riscv_cpu_reset(DeviceState *dev)
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus &= ~MSTATUS_FS;
+ }
if (env->misa_mxl > MXL_RV32) {
/*
* The reset status of SXL/UXL is undefined, but mstatus is WARL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10f3baba53..a71edee44c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -222,9 +222,13 @@ bool riscv_cpu_vector_enabled(CPURISCVState *env)
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
- uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+ uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM|
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | MSTATUS_VS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ mstatus_mask |= MSTATUS_FS;
+ }
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 146447eac5..de20206b73 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -38,7 +38,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+ if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
+ !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
@@ -234,7 +235,10 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return RISCV_EXCP_NONE;
@@ -251,7 +255,10 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
return RISCV_EXCP_NONE;
@@ -269,7 +276,10 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
@@ -562,9 +572,13 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ mask |= MSTATUS_FS;
+ }
if (riscv_cpu_mxl(env) != MXL_RV32) {
/*
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8b1cdacf50..17bf20a799 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -342,6 +342,11 @@ static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ /* hardwire mstatus.FS to zero when enable zfinx */
+ if (ctx->ext_zfinx) {
+ return;
+ }
+
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
--
2.17.1
next prev parent reply other threads:[~2021-12-31 3:30 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-31 3:23 [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 6:28 ` Bin Meng
2021-12-31 6:28 ` Bin Meng
2021-12-31 3:23 ` Weiwei Li [this message]
2021-12-31 3:23 ` [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li
2021-12-31 19:56 ` Richard Henderson
2022-01-01 5:55 ` Weiwei Li
2022-01-01 19:46 ` Richard Henderson
2022-01-02 5:53 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 3/6] target/riscv: add support for zfinx Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 20:03 ` Richard Henderson
2021-12-31 20:06 ` Richard Henderson
2022-01-01 6:05 ` Weiwei Li
2022-01-01 19:48 ` Richard Henderson
2022-01-02 5:56 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 4/6] target/riscv: add support for zdinx Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 20:07 ` Richard Henderson
2022-01-01 6:06 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li
2021-12-31 3:23 ` Weiwei Li
2021-12-31 20:08 ` Richard Henderson
2021-12-31 3:23 ` [PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li
2021-12-31 3:23 ` Weiwei Li
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