From: Suzuki K Poulose <suzuki.poulose@arm.com> To: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 18/26] coresight: etm4x: Clean up exception level masks Date: Tue, 10 Nov 2020 23:15:59 +0000 [thread overview] Message-ID: <80b0933d-ef0a-2937-bf47-daf9fefebf3f@arm.com> (raw) In-Reply-To: <20201106185241.GA3299843@xps15> On 11/6/20 6:52 PM, Mathieu Poirier wrote: > Good morning, > > On Wed, Oct 28, 2020 at 10:09:37PM +0000, Suzuki K Poulose wrote: >> etm4_get_access_type() calculates the exception level bits >> for use in address comparator registers. This is also used >> by the TRCVICTLR register by shifting to the required position. >> >> This patch cleans up the logic to make etm4_get_access_type() >> calcualte a generic mask which can be used by all users by >> shifting to their field. >> >> No functional changes, only code cleanups. >> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> --- >> Changes since previous version: >> - Fix the duplicate shift. More commentary >> --- >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index 2ac4ecb0af61..f1251ddf1984 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -548,24 +548,38 @@ >> >> #define TRCACATR_EXLEVEL_SHIFT 8 >> >> -/* secure state access levels - TRCACATRn */ >> -#define ETM_EXLEVEL_S_APP BIT(8) >> -#define ETM_EXLEVEL_S_OS BIT(9) >> -#define ETM_EXLEVEL_S_HYP BIT(10) >> -#define ETM_EXLEVEL_S_MON BIT(11) >> -/* non-secure state access levels - TRCACATRn */ >> -#define ETM_EXLEVEL_NS_APP BIT(12) >> -#define ETM_EXLEVEL_NS_OS BIT(13) >> -#define ETM_EXLEVEL_NS_HYP BIT(14) >> -#define ETM_EXLEVEL_NS_NA BIT(15) >> - >> -/* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */ >> -#define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8 >> +/* >> + * Exception level mask for Secure and Non-Secure ELs. >> + * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). >> + * The Secure and Non-Secure ELs are always to gether. >> + * Non-secure EL3 is never implemented. >> + * We use the following generic mask as they appear in different >> + * registers and this can be shifted for the appropriate >> + * fields. >> + */ >> +#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ >> +#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ >> +#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ >> +#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Montor */ > > s/Montor/Monitor > >> +#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ >> +#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ >> +#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ >> + >> +#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) > > Not used. > I have updated the patch to use this for creating the TRCVICTLR_EXLEVEL_MASK (see below), which is used to clear all the EXLEVEL bits from TRCVICTLR. >> +#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) >> +#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) > > This needs to be GENMASK(2, 0) in order TRCVICTLR_EXLEVEL_NS_SHIFT to be 20. > Otherwise the resulting mask is 4 bit off to the left. I have retained the ETM_EXLEVEL_NS_MASK as it is above, to keep the defintions above consistent. I have fixed the problem by using TRCVICTLR_EXLEVEL_SHIFT whenever we use ETM_EXLEVEL_*_MASK. And TRCVICTLR_EXLEVEL_*_SHIFT is used when we set a given value from the sysfs, respectively. e.g : @@ -795,10 +795,10 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, spin_lock(&drvdata->spinlock); /* clear EXLEVEL_NS bits */ - config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_NS_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; - config->vinst_ctrl |= (val << 20); + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_NS_SHIFT); spin_unlock(&drvdata->spinlock); return size; } > >> + >> +/* access level controls in TRCACATRn */ >> +#define TRCACATR_EXLEVEL_SHIFT 8 >> + >> +/* access level control in TRCVICTLR */ >> +#define TRCVICTLR_EXLEVEL_SHIFT 16 >> +#define TRCVICTLR_EXLEVEL_S_SHIFT 16 >> +#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 >> >> /* secure / non secure masks - TRCVICTLR, IDR3 */ >> -#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) >> -/* NS MON (EL3) mode never implemented */ >> -#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) >> +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_S_SHIFT) >> +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_NS_SHIFT) And the above has been updated to : +#define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Subject: Re: [PATCH v3 18/26] coresight: etm4x: Clean up exception level masks Date: Tue, 10 Nov 2020 23:15:59 +0000 [thread overview] Message-ID: <80b0933d-ef0a-2937-bf47-daf9fefebf3f@arm.com> (raw) In-Reply-To: <20201106185241.GA3299843@xps15> On 11/6/20 6:52 PM, Mathieu Poirier wrote: > Good morning, > > On Wed, Oct 28, 2020 at 10:09:37PM +0000, Suzuki K Poulose wrote: >> etm4_get_access_type() calculates the exception level bits >> for use in address comparator registers. This is also used >> by the TRCVICTLR register by shifting to the required position. >> >> This patch cleans up the logic to make etm4_get_access_type() >> calcualte a generic mask which can be used by all users by >> shifting to their field. >> >> No functional changes, only code cleanups. >> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> --- >> Changes since previous version: >> - Fix the duplicate shift. More commentary >> --- >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index 2ac4ecb0af61..f1251ddf1984 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -548,24 +548,38 @@ >> >> #define TRCACATR_EXLEVEL_SHIFT 8 >> >> -/* secure state access levels - TRCACATRn */ >> -#define ETM_EXLEVEL_S_APP BIT(8) >> -#define ETM_EXLEVEL_S_OS BIT(9) >> -#define ETM_EXLEVEL_S_HYP BIT(10) >> -#define ETM_EXLEVEL_S_MON BIT(11) >> -/* non-secure state access levels - TRCACATRn */ >> -#define ETM_EXLEVEL_NS_APP BIT(12) >> -#define ETM_EXLEVEL_NS_OS BIT(13) >> -#define ETM_EXLEVEL_NS_HYP BIT(14) >> -#define ETM_EXLEVEL_NS_NA BIT(15) >> - >> -/* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */ >> -#define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8 >> +/* >> + * Exception level mask for Secure and Non-Secure ELs. >> + * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). >> + * The Secure and Non-Secure ELs are always to gether. >> + * Non-secure EL3 is never implemented. >> + * We use the following generic mask as they appear in different >> + * registers and this can be shifted for the appropriate >> + * fields. >> + */ >> +#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ >> +#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ >> +#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ >> +#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Montor */ > > s/Montor/Monitor > >> +#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ >> +#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ >> +#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ >> + >> +#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) > > Not used. > I have updated the patch to use this for creating the TRCVICTLR_EXLEVEL_MASK (see below), which is used to clear all the EXLEVEL bits from TRCVICTLR. >> +#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) >> +#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) > > This needs to be GENMASK(2, 0) in order TRCVICTLR_EXLEVEL_NS_SHIFT to be 20. > Otherwise the resulting mask is 4 bit off to the left. I have retained the ETM_EXLEVEL_NS_MASK as it is above, to keep the defintions above consistent. I have fixed the problem by using TRCVICTLR_EXLEVEL_SHIFT whenever we use ETM_EXLEVEL_*_MASK. And TRCVICTLR_EXLEVEL_*_SHIFT is used when we set a given value from the sysfs, respectively. e.g : @@ -795,10 +795,10 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, spin_lock(&drvdata->spinlock); /* clear EXLEVEL_NS bits */ - config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_NS_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; - config->vinst_ctrl |= (val << 20); + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_NS_SHIFT); spin_unlock(&drvdata->spinlock); return size; } > >> + >> +/* access level controls in TRCACATRn */ >> +#define TRCACATR_EXLEVEL_SHIFT 8 >> + >> +/* access level control in TRCVICTLR */ >> +#define TRCVICTLR_EXLEVEL_SHIFT 16 >> +#define TRCVICTLR_EXLEVEL_S_SHIFT 16 >> +#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 >> >> /* secure / non secure masks - TRCVICTLR, IDR3 */ >> -#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) >> -/* NS MON (EL3) mode never implemented */ >> -#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) >> +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_S_SHIFT) >> +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_NS_SHIFT) And the above has been updated to : +#define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-10 23:16 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-28 22:09 [PATCH v3 00/26] coresight: Support for ETM system instructions Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 01/26] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 02/26] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 03/26] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 04/26] coresight: etm4x: Fix accesses to TRCPROCSELR Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 05/26] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-02 21:46 ` Mathieu Poirier 2020-11-02 21:46 ` Mathieu Poirier 2020-11-02 22:04 ` Suzuki K Poulose 2020-11-02 22:04 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 07/26] coresight: Introduce device access abstraction Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 17:14 ` Mathieu Poirier 2020-11-03 17:14 ` Mathieu Poirier 2020-11-03 17:25 ` Mathieu Poirier 2020-11-03 17:25 ` Mathieu Poirier 2020-11-04 10:07 ` Suzuki K Poulose 2020-11-04 10:07 ` Suzuki K Poulose 2020-11-09 21:00 ` Mathieu Poirier 2020-11-09 21:00 ` Mathieu Poirier 2020-11-10 9:24 ` Suzuki K Poulose 2020-11-10 9:24 ` Suzuki K Poulose 2020-11-10 17:02 ` Mathieu Poirier 2020-11-10 17:02 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 08/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:03 ` Mathieu Poirier 2020-11-03 18:03 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 09/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:03 ` Mathieu Poirier 2020-11-03 18:03 ` Mathieu Poirier 2020-11-04 10:42 ` Suzuki K Poulose 2020-11-04 10:42 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 10/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:36 ` Mathieu Poirier 2020-11-03 18:36 ` Mathieu Poirier 2020-11-04 10:54 ` Suzuki K Poulose 2020-11-04 10:54 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 11/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 12/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:53 ` Mathieu Poirier 2020-11-03 18:53 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 19:03 ` Mathieu Poirier 2020-11-03 19:03 ` Mathieu Poirier 2020-11-03 19:04 ` Mathieu Poirier 2020-11-03 19:04 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 14/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-29 15:26 ` Suzuki K Poulose 2020-10-29 15:26 ` Suzuki K Poulose 2020-11-05 20:52 ` Mathieu Poirier 2020-11-05 20:52 ` Mathieu Poirier 2020-11-05 22:47 ` Suzuki K Poulose 2020-11-05 22:47 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 15/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-05 21:50 ` Mathieu Poirier 2020-11-05 21:50 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 17/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-05 21:55 ` Mathieu Poirier 2020-11-05 21:55 ` Mathieu Poirier 2020-11-09 9:40 ` Suzuki K Poulose 2020-11-09 9:40 ` Suzuki K Poulose 2020-11-09 17:42 ` Mathieu Poirier 2020-11-09 17:42 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 18/26] coresight: etm4x: Clean up " Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 18:52 ` Mathieu Poirier 2020-11-06 18:52 ` Mathieu Poirier 2020-11-09 9:44 ` Suzuki K Poulose 2020-11-09 9:44 ` Suzuki K Poulose 2020-11-10 23:15 ` Suzuki K Poulose [this message] 2020-11-10 23:15 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 19/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 20:34 ` Mathieu Poirier 2020-11-06 20:34 ` Mathieu Poirier 2020-11-09 9:48 ` Suzuki K Poulose 2020-11-09 9:48 ` Suzuki K Poulose 2020-11-09 17:48 ` Mathieu Poirier 2020-11-09 17:48 ` Mathieu Poirier 2020-11-06 20:46 ` Mathieu Poirier 2020-11-06 20:46 ` Mathieu Poirier 2020-11-10 10:47 ` Suzuki K Poulose 2020-11-10 10:47 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 20/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 21:11 ` Mathieu Poirier 2020-11-06 21:11 ` Mathieu Poirier 2020-11-09 9:51 ` Suzuki K Poulose 2020-11-09 9:51 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 21/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 21:42 ` Mathieu Poirier 2020-11-06 21:42 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 18:32 ` Mathieu Poirier 2020-11-09 18:32 ` Mathieu Poirier 2020-11-10 10:11 ` Suzuki K Poulose 2020-11-10 10:11 ` Suzuki K Poulose 2020-11-10 11:40 ` John Horley 2020-11-10 11:40 ` John Horley 2020-11-10 17:35 ` Mathieu Poirier 2020-11-10 17:35 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 23/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 20:22 ` Mathieu Poirier 2020-11-09 20:22 ` Mathieu Poirier 2020-11-10 9:31 ` Suzuki K Poulose 2020-11-10 9:31 ` Suzuki K Poulose 2020-11-10 17:33 ` Mathieu Poirier 2020-11-10 17:33 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 24/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 20:43 ` Mathieu Poirier 2020-11-09 20:43 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 25/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 20:46 ` Mathieu Poirier 2020-11-09 20:46 ` Mathieu Poirier 2020-11-10 10:50 ` Suzuki K Poulose 2020-11-10 10:50 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 26/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-02 15:31 ` Rob Herring 2020-11-02 15:31 ` Rob Herring 2020-11-09 20:50 ` Mathieu Poirier 2020-11-09 20:50 ` Mathieu Poirier 2020-11-10 10:51 ` Suzuki K Poulose 2020-11-10 10:51 ` Suzuki K Poulose 2020-10-29 7:53 ` [PATCH v3 00/26] coresight: Support for ETM system instructions Mike Leach 2020-10-29 7:53 ` Mike Leach 2020-10-29 15:45 ` Suzuki K Poulose 2020-10-29 15:45 ` Suzuki K Poulose
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