From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, Mike Leach <mike.leach@linaro.org>, Coresight ML <coresight@lists.linaro.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Date: Tue, 3 Nov 2020 12:04:59 -0700 [thread overview] Message-ID: <CANLsYkxhsj39+oG6i8hWLUsrU5shSTEq88_6_5zmAJcbFjTMgA@mail.gmail.com> (raw) In-Reply-To: <20201028220945.3826358-15-suzuki.poulose@arm.com> On Wed, 28 Oct 2020 at 16:10, Suzuki K Poulose <suzuki.poulose@arm.com> wrote: > > As we are about define a switch..case table for individual register > access by offset for implementing the system instruction support, > document the possible set of registers for each group to make > it easier to co-relate. s/co-relate/correlate > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 14e0f29db6b3..510828c73db6 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -44,13 +44,13 @@ > #define TRCVDSACCTLR 0x0A4 > #define TRCVDARCCTLR 0x0A8 > /* Derived resources registers */ > -#define TRCSEQEVRn(n) (0x100 + (n * 4)) > +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ > #define TRCSEQRSTEVR 0x118 > #define TRCSEQSTR 0x11C > #define TRCEXTINSELR 0x120 > -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) > -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) > -#define TRCCNTVRn(n) (0x160 + (n * 4)) > +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ > /* ID registers */ > #define TRCIDR8 0x180 > #define TRCIDR9 0x184 > @@ -59,7 +59,7 @@ > #define TRCIDR12 0x190 > #define TRCIDR13 0x194 > #define TRCIMSPEC0 0x1C0 > -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) > +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ > #define TRCIDR0 0x1E0 > #define TRCIDR1 0x1E4 > #define TRCIDR2 0x1E8 > @@ -68,9 +68,12 @@ > #define TRCIDR5 0x1F4 > #define TRCIDR6 0x1F8 > #define TRCIDR7 0x1FC > -/* Resource selection registers */ > +/* > + * Resource selection registers, n = 2-31. > + * First pair (regs 0, 1) is always present and is reserved. > + */ > #define TRCRSCTLRn(n) (0x200 + (n * 4)) > -/* Single-shot comparator registers */ > +/* Single-shot comparator registers, n = 0-7 */ > #define TRCSSCCRn(n) (0x280 + (n * 4)) > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) > @@ -80,11 +83,13 @@ > #define TRCPDCR 0x310 > #define TRCPDSR 0x314 > /* Trace registers (0x318-0xEFC) */ > -/* Comparator registers */ > +/* Address Comparator registers n = 0-15 */ > #define TRCACVRn(n) (0x400 + (n * 8)) > #define TRCACATRn(n) (0x480 + (n * 8)) > +/* Data Value Comparator Value registers, n = 0-7 */ > #define TRCDVCVRn(n) (0x500 + (n * 16)) > #define TRCDVCMRn(n) (0x580 + (n * 16)) > +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > #define TRCCIDCVRn(n) (0x600 + (n * 8)) > #define TRCVMIDCVRn(n) (0x640 + (n * 8)) > #define TRCCIDCCTLR0 0x680 > -- > 2.24.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Coresight ML <coresight@lists.linaro.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, Mike Leach <mike.leach@linaro.org> Subject: Re: [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Date: Tue, 3 Nov 2020 12:04:59 -0700 [thread overview] Message-ID: <CANLsYkxhsj39+oG6i8hWLUsrU5shSTEq88_6_5zmAJcbFjTMgA@mail.gmail.com> (raw) In-Reply-To: <20201028220945.3826358-15-suzuki.poulose@arm.com> On Wed, 28 Oct 2020 at 16:10, Suzuki K Poulose <suzuki.poulose@arm.com> wrote: > > As we are about define a switch..case table for individual register > access by offset for implementing the system instruction support, > document the possible set of registers for each group to make > it easier to co-relate. s/co-relate/correlate > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 14e0f29db6b3..510828c73db6 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -44,13 +44,13 @@ > #define TRCVDSACCTLR 0x0A4 > #define TRCVDARCCTLR 0x0A8 > /* Derived resources registers */ > -#define TRCSEQEVRn(n) (0x100 + (n * 4)) > +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ > #define TRCSEQRSTEVR 0x118 > #define TRCSEQSTR 0x11C > #define TRCEXTINSELR 0x120 > -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) > -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) > -#define TRCCNTVRn(n) (0x160 + (n * 4)) > +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ > /* ID registers */ > #define TRCIDR8 0x180 > #define TRCIDR9 0x184 > @@ -59,7 +59,7 @@ > #define TRCIDR12 0x190 > #define TRCIDR13 0x194 > #define TRCIMSPEC0 0x1C0 > -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) > +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ > #define TRCIDR0 0x1E0 > #define TRCIDR1 0x1E4 > #define TRCIDR2 0x1E8 > @@ -68,9 +68,12 @@ > #define TRCIDR5 0x1F4 > #define TRCIDR6 0x1F8 > #define TRCIDR7 0x1FC > -/* Resource selection registers */ > +/* > + * Resource selection registers, n = 2-31. > + * First pair (regs 0, 1) is always present and is reserved. > + */ > #define TRCRSCTLRn(n) (0x200 + (n * 4)) > -/* Single-shot comparator registers */ > +/* Single-shot comparator registers, n = 0-7 */ > #define TRCSSCCRn(n) (0x280 + (n * 4)) > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) > @@ -80,11 +83,13 @@ > #define TRCPDCR 0x310 > #define TRCPDSR 0x314 > /* Trace registers (0x318-0xEFC) */ > -/* Comparator registers */ > +/* Address Comparator registers n = 0-15 */ > #define TRCACVRn(n) (0x400 + (n * 8)) > #define TRCACATRn(n) (0x480 + (n * 8)) > +/* Data Value Comparator Value registers, n = 0-7 */ > #define TRCDVCVRn(n) (0x500 + (n * 16)) > #define TRCDVCMRn(n) (0x580 + (n * 16)) > +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > #define TRCCIDCVRn(n) (0x600 + (n * 8)) > #define TRCVMIDCVRn(n) (0x640 + (n * 8)) > #define TRCCIDCCTLR0 0x680 > -- > 2.24.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-03 19:05 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-28 22:09 [PATCH v3 00/26] coresight: Support for ETM system instructions Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 01/26] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 02/26] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 03/26] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 04/26] coresight: etm4x: Fix accesses to TRCPROCSELR Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 05/26] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-02 21:46 ` Mathieu Poirier 2020-11-02 21:46 ` Mathieu Poirier 2020-11-02 22:04 ` Suzuki K Poulose 2020-11-02 22:04 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 07/26] coresight: Introduce device access abstraction Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 17:14 ` Mathieu Poirier 2020-11-03 17:14 ` Mathieu Poirier 2020-11-03 17:25 ` Mathieu Poirier 2020-11-03 17:25 ` Mathieu Poirier 2020-11-04 10:07 ` Suzuki K Poulose 2020-11-04 10:07 ` Suzuki K Poulose 2020-11-09 21:00 ` Mathieu Poirier 2020-11-09 21:00 ` Mathieu Poirier 2020-11-10 9:24 ` Suzuki K Poulose 2020-11-10 9:24 ` Suzuki K Poulose 2020-11-10 17:02 ` Mathieu Poirier 2020-11-10 17:02 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 08/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:03 ` Mathieu Poirier 2020-11-03 18:03 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 09/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:03 ` Mathieu Poirier 2020-11-03 18:03 ` Mathieu Poirier 2020-11-04 10:42 ` Suzuki K Poulose 2020-11-04 10:42 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 10/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:36 ` Mathieu Poirier 2020-11-03 18:36 ` Mathieu Poirier 2020-11-04 10:54 ` Suzuki K Poulose 2020-11-04 10:54 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 11/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 12/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 18:53 ` Mathieu Poirier 2020-11-03 18:53 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-03 19:03 ` Mathieu Poirier 2020-11-03 19:03 ` Mathieu Poirier 2020-11-03 19:04 ` Mathieu Poirier [this message] 2020-11-03 19:04 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 14/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-29 15:26 ` Suzuki K Poulose 2020-10-29 15:26 ` Suzuki K Poulose 2020-11-05 20:52 ` Mathieu Poirier 2020-11-05 20:52 ` Mathieu Poirier 2020-11-05 22:47 ` Suzuki K Poulose 2020-11-05 22:47 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 15/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-05 21:50 ` Mathieu Poirier 2020-11-05 21:50 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 17/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-05 21:55 ` Mathieu Poirier 2020-11-05 21:55 ` Mathieu Poirier 2020-11-09 9:40 ` Suzuki K Poulose 2020-11-09 9:40 ` Suzuki K Poulose 2020-11-09 17:42 ` Mathieu Poirier 2020-11-09 17:42 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 18/26] coresight: etm4x: Clean up " Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 18:52 ` Mathieu Poirier 2020-11-06 18:52 ` Mathieu Poirier 2020-11-09 9:44 ` Suzuki K Poulose 2020-11-09 9:44 ` Suzuki K Poulose 2020-11-10 23:15 ` Suzuki K Poulose 2020-11-10 23:15 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 19/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 20:34 ` Mathieu Poirier 2020-11-06 20:34 ` Mathieu Poirier 2020-11-09 9:48 ` Suzuki K Poulose 2020-11-09 9:48 ` Suzuki K Poulose 2020-11-09 17:48 ` Mathieu Poirier 2020-11-09 17:48 ` Mathieu Poirier 2020-11-06 20:46 ` Mathieu Poirier 2020-11-06 20:46 ` Mathieu Poirier 2020-11-10 10:47 ` Suzuki K Poulose 2020-11-10 10:47 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 20/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 21:11 ` Mathieu Poirier 2020-11-06 21:11 ` Mathieu Poirier 2020-11-09 9:51 ` Suzuki K Poulose 2020-11-09 9:51 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 21/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-06 21:42 ` Mathieu Poirier 2020-11-06 21:42 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 18:32 ` Mathieu Poirier 2020-11-09 18:32 ` Mathieu Poirier 2020-11-10 10:11 ` Suzuki K Poulose 2020-11-10 10:11 ` Suzuki K Poulose 2020-11-10 11:40 ` John Horley 2020-11-10 11:40 ` John Horley 2020-11-10 17:35 ` Mathieu Poirier 2020-11-10 17:35 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 23/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 20:22 ` Mathieu Poirier 2020-11-09 20:22 ` Mathieu Poirier 2020-11-10 9:31 ` Suzuki K Poulose 2020-11-10 9:31 ` Suzuki K Poulose 2020-11-10 17:33 ` Mathieu Poirier 2020-11-10 17:33 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 24/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 20:43 ` Mathieu Poirier 2020-11-09 20:43 ` Mathieu Poirier 2020-10-28 22:09 ` [PATCH v3 25/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-09 20:46 ` Mathieu Poirier 2020-11-09 20:46 ` Mathieu Poirier 2020-11-10 10:50 ` Suzuki K Poulose 2020-11-10 10:50 ` Suzuki K Poulose 2020-10-28 22:09 ` [PATCH v3 26/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose 2020-10-28 22:09 ` Suzuki K Poulose 2020-11-02 15:31 ` Rob Herring 2020-11-02 15:31 ` Rob Herring 2020-11-09 20:50 ` Mathieu Poirier 2020-11-09 20:50 ` Mathieu Poirier 2020-11-10 10:51 ` Suzuki K Poulose 2020-11-10 10:51 ` Suzuki K Poulose 2020-10-29 7:53 ` [PATCH v3 00/26] coresight: Support for ETM system instructions Mike Leach 2020-10-29 7:53 ` Mike Leach 2020-10-29 15:45 ` Suzuki K Poulose 2020-10-29 15:45 ` Suzuki K Poulose
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