From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, ulf.hansson@linaro.org,
linus.walleij@linaro.org, catalin.marinas@arm.com,
will@kernel.org, shawnguo@kernel.org, arnd@arndb.de,
marcel.ziswiler@toradex.com, dmitry.baryshkov@linaro.org,
nfraprado@collabora.com, broonie@kernel.org, robimarko@gmail.com,
quic_gurus@quicinc.com, bhupesh.sharma@linaro.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 09/10] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
Date: Tue, 31 Jan 2023 20:24:49 +0100 [thread overview]
Message-ID: <85ae379d-ee71-7636-1ca1-2fb2baad63f3@linaro.org> (raw)
In-Reply-To: <efe976be-79b9-1f1b-69a1-18dd3b0798df@quicinc.com>
On 30/01/2023 12:56, Kathiravan Thirumoorthy wrote:
>>>> + sdhc: mmc@7804000 {
>>>> + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
>>>> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>>>> +
>>>> + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "hc_irq", "pwr_irq";
>>>> +
>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>>> + <&gcc GCC_SDCC1_APPS_CLK>,
>>>> + <&xo_board>;
>>>> + clock-names = "iface", "core", "xo";
>>>> + mmc-ddr-1_8v;
>>>> + mmc-hs200-1_8v;
>>>> + max-frequency = <192000000>;
>>> As Krzysztof pointed out, this one should go.
>>
>>
>> Ack.
>
> Krzysztof & Konrad,
>
> These are the properties of the SDHC controller present in the SoC. So I
> think no need to move out these properties to board DTS. Please let me
> know if my understanding is otherwise.
Usually max frequency of SDHC controller is depending on the board, so
no, it is not a property of SoC. The same with type of attached memory.
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, ulf.hansson@linaro.org,
linus.walleij@linaro.org, catalin.marinas@arm.com,
will@kernel.org, shawnguo@kernel.org, arnd@arndb.de,
marcel.ziswiler@toradex.com, dmitry.baryshkov@linaro.org,
nfraprado@collabora.com, broonie@kernel.org, robimarko@gmail.com,
quic_gurus@quicinc.com, bhupesh.sharma@linaro.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 09/10] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
Date: Tue, 31 Jan 2023 20:24:49 +0100 [thread overview]
Message-ID: <85ae379d-ee71-7636-1ca1-2fb2baad63f3@linaro.org> (raw)
In-Reply-To: <efe976be-79b9-1f1b-69a1-18dd3b0798df@quicinc.com>
On 30/01/2023 12:56, Kathiravan Thirumoorthy wrote:
>>>> + sdhc: mmc@7804000 {
>>>> + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
>>>> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>>>> +
>>>> + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "hc_irq", "pwr_irq";
>>>> +
>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>>> + <&gcc GCC_SDCC1_APPS_CLK>,
>>>> + <&xo_board>;
>>>> + clock-names = "iface", "core", "xo";
>>>> + mmc-ddr-1_8v;
>>>> + mmc-hs200-1_8v;
>>>> + max-frequency = <192000000>;
>>> As Krzysztof pointed out, this one should go.
>>
>>
>> Ack.
>
> Krzysztof & Konrad,
>
> These are the properties of the SDHC controller present in the SoC. So I
> think no need to move out these properties to board DTS. Please let me
> know if my understanding is otherwise.
Usually max frequency of SDHC controller is depending on the board, so
no, it is not a property of SoC. The same with type of attached memory.
Best regards,
Krzysztof
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next prev parent reply other threads:[~2023-01-31 19:24 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 10:45 [PATCH 00/10] Add minimal boot support for IPQ5332 Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 01/10] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 11:10 ` Krzysztof Kozlowski
2023-01-25 11:10 ` Krzysztof Kozlowski
2023-01-25 15:49 ` Kathiravan Thirumoorthy
2023-01-25 15:49 ` Kathiravan Thirumoorthy
2023-01-25 16:20 ` Krzysztof Kozlowski
2023-01-25 16:20 ` Krzysztof Kozlowski
2023-01-25 16:38 ` Kathiravan Thirumoorthy
2023-01-25 16:38 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 02/10] pinctrl: qcom: Introduce IPQ5332 TLMM driver Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 03/10] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 20:35 ` Stephen Boyd
2023-01-25 20:35 ` Stephen Boyd
2023-01-25 10:45 ` [PATCH 04/10] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 11:13 ` Krzysztof Kozlowski
2023-01-25 11:13 ` Krzysztof Kozlowski
2023-01-25 15:50 ` Kathiravan Thirumoorthy
2023-01-25 15:50 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 05/10] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Kathiravan Thirumoorthy
2023-01-25 11:14 ` Krzysztof Kozlowski
2023-01-25 11:14 ` Krzysztof Kozlowski
2023-01-25 15:53 ` Kathiravan Thirumoorthy
2023-01-25 15:53 ` Kathiravan Thirumoorthy
2023-01-25 20:54 ` Stephen Boyd
2023-01-25 20:54 ` Stephen Boyd
2023-01-26 16:45 ` Kathiravan Thirumoorthy
2023-01-26 16:45 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 06/10] dt-bindings: qcom: add ipq5332 boards Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 11:15 ` Krzysztof Kozlowski
2023-01-25 11:15 ` Krzysztof Kozlowski
2023-01-25 15:55 ` Kathiravan Thirumoorthy
2023-01-25 15:55 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 07/10] dt-bindings: firmware: document IPQ5332 SCM Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 11:16 ` Krzysztof Kozlowski
2023-01-25 11:16 ` Krzysztof Kozlowski
2023-01-25 15:55 ` Kathiravan Thirumoorthy
2023-01-25 15:55 ` Kathiravan Thirumoorthy
2023-01-25 10:45 ` [PATCH 08/10] dt-bindings: mmc: sdhci-msm: add IPQ5332 compatible Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 11:17 ` Krzysztof Kozlowski
2023-01-25 11:17 ` Krzysztof Kozlowski
2023-01-27 10:56 ` Ulf Hansson
2023-01-27 10:56 ` Ulf Hansson
2023-01-25 10:45 ` [PATCH 09/10] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
2023-01-25 11:22 ` Krzysztof Kozlowski
2023-01-25 11:22 ` Krzysztof Kozlowski
2023-01-25 16:05 ` Kathiravan Thirumoorthy
2023-01-25 16:05 ` Kathiravan Thirumoorthy
2023-01-25 21:59 ` Konrad Dybcio
2023-01-25 21:59 ` Konrad Dybcio
2023-01-26 16:50 ` Kathiravan Thirumoorthy
2023-01-26 16:50 ` Kathiravan Thirumoorthy
2023-01-30 11:56 ` Kathiravan Thirumoorthy
2023-01-30 11:56 ` Kathiravan Thirumoorthy
2023-01-31 19:24 ` Krzysztof Kozlowski [this message]
2023-01-31 19:24 ` Krzysztof Kozlowski
2023-01-25 10:45 ` [PATCH 10/10] arm64: defconfig: Enable IPQ5332 SoC base configs Kathiravan Thirumoorthy
2023-01-25 10:45 ` Kathiravan Thirumoorthy
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