From: Thomas Gleixner <tglx@linutronix.de> To: David Woodhouse <dwmw2@infradead.org>, x86@kernel.org Cc: iommu <iommu@lists.linux-foundation.org>, kvm <kvm@vger.kernel.org>, linux-hyperv@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com> Subject: Re: [PATCH 10/13] x86/irq: Limit IOAPIC and MSI domains' affinity without IR Date: Tue, 06 Oct 2020 23:54:27 +0200 [thread overview] Message-ID: <87d01v58bw.fsf@nanos.tec.linutronix.de> (raw) In-Reply-To: <20201005152856.974112-10-dwmw2@infradead.org> On Mon, Oct 05 2020 at 16:28, David Woodhouse wrote: > From: David Woodhouse <dwmw@amazon.co.uk> > > When interrupt remapping isn't enabled, only the first 255 CPUs can No, only CPUs with an APICid < 255 .... > receive external interrupts. Set the appropriate max affinity for > the IOAPIC and MSI IRQ domains accordingly. > > This also fixes the case where interrupt remapping is enabled but some > devices are not within the scope of any active IOMMU. What? If this fixes an pre-existing problem then 1) Explain the problem proper 2) Have a patch at the beginning of the series which fixes it independently of this pile If it's fixing a problem in your pile, then you got the ordering wrong. You didn't start kernel programming as of yesterday, so you really know how that works. > ip->irqdomain->parent = parent; > + if (parent == x86_vector_domain) > + irq_domain_set_affinity(ip->irqdomain, &x86_non_ir_cpumask); OMG > if (cfg->type == IOAPIC_DOMAIN_LEGACY || > cfg->type == IOAPIC_DOMAIN_STRICT) > diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c > index 4d891967bea4..af5ce5c4da02 100644 > --- a/arch/x86/kernel/apic/msi.c > +++ b/arch/x86/kernel/apic/msi.c > @@ -259,6 +259,7 @@ struct irq_domain * __init native_create_pci_msi_domain(void) > pr_warn("Failed to initialize PCI-MSI irqdomain.\n"); > } else { > d->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK; > + irq_domain_set_affinity(d, &x86_non_ir_cpumask); So here it's unconditional > } > return d; > } > @@ -479,6 +480,8 @@ struct irq_domain *hpet_create_irq_domain(int hpet_id) > irq_domain_free_fwnode(fn); > kfree(domain_info); > } > + if (parent == x86_vector_domain) > + irq_domain_set_affinity(d, &x86_non_ir_cpumask); And here we need a condition again. Completely obvious and reviewable - NOT. Thanks, tglx
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de> To: David Woodhouse <dwmw2@infradead.org>, x86@kernel.org Cc: Paolo Bonzini <pbonzini@redhat.com>, iommu <iommu@lists.linux-foundation.org>, linux-hyperv@vger.kernel.org, kvm <kvm@vger.kernel.org> Subject: Re: [PATCH 10/13] x86/irq: Limit IOAPIC and MSI domains' affinity without IR Date: Tue, 06 Oct 2020 23:54:27 +0200 [thread overview] Message-ID: <87d01v58bw.fsf@nanos.tec.linutronix.de> (raw) In-Reply-To: <20201005152856.974112-10-dwmw2@infradead.org> On Mon, Oct 05 2020 at 16:28, David Woodhouse wrote: > From: David Woodhouse <dwmw@amazon.co.uk> > > When interrupt remapping isn't enabled, only the first 255 CPUs can No, only CPUs with an APICid < 255 .... > receive external interrupts. Set the appropriate max affinity for > the IOAPIC and MSI IRQ domains accordingly. > > This also fixes the case where interrupt remapping is enabled but some > devices are not within the scope of any active IOMMU. What? If this fixes an pre-existing problem then 1) Explain the problem proper 2) Have a patch at the beginning of the series which fixes it independently of this pile If it's fixing a problem in your pile, then you got the ordering wrong. You didn't start kernel programming as of yesterday, so you really know how that works. > ip->irqdomain->parent = parent; > + if (parent == x86_vector_domain) > + irq_domain_set_affinity(ip->irqdomain, &x86_non_ir_cpumask); OMG > if (cfg->type == IOAPIC_DOMAIN_LEGACY || > cfg->type == IOAPIC_DOMAIN_STRICT) > diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c > index 4d891967bea4..af5ce5c4da02 100644 > --- a/arch/x86/kernel/apic/msi.c > +++ b/arch/x86/kernel/apic/msi.c > @@ -259,6 +259,7 @@ struct irq_domain * __init native_create_pci_msi_domain(void) > pr_warn("Failed to initialize PCI-MSI irqdomain.\n"); > } else { > d->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK; > + irq_domain_set_affinity(d, &x86_non_ir_cpumask); So here it's unconditional > } > return d; > } > @@ -479,6 +480,8 @@ struct irq_domain *hpet_create_irq_domain(int hpet_id) > irq_domain_free_fwnode(fn); > kfree(domain_info); > } > + if (parent == x86_vector_domain) > + irq_domain_set_affinity(d, &x86_non_ir_cpumask); And here we need a condition again. Completely obvious and reviewable - NOT. Thanks, tglx _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-10-06 21:54 UTC|newest] Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-05 15:28 [PATCH 0/13] Fix per-domain IRQ affinity, allow >255 CPUs on x86 without IRQ remapping David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 01/13] x86/apic: Use x2apic in guest kernels even with unusable CPUs David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 02/13] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 20:45 ` Thomas Gleixner 2020-10-06 20:45 ` Thomas Gleixner 2020-10-05 15:28 ` [PATCH 03/13] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 04/13] x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where available David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 05/13] genirq: Prepare for default affinity to be passed to __irq_alloc_descs() David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 21:01 ` Thomas Gleixner 2020-10-06 21:01 ` Thomas Gleixner 2020-10-06 21:07 ` David Woodhouse 2020-10-06 21:07 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 06/13] genirq: Add default_affinity argument " David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 21:06 ` Thomas Gleixner 2020-10-06 21:06 ` Thomas Gleixner 2020-10-05 15:28 ` [PATCH 07/13] irqdomain: Add max_affinity argument to irq_domain_alloc_descs() David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 21:26 ` Thomas Gleixner 2020-10-06 21:26 ` Thomas Gleixner 2020-10-07 7:19 ` David Woodhouse 2020-10-07 7:19 ` David Woodhouse 2020-10-07 13:37 ` Thomas Gleixner 2020-10-07 13:37 ` Thomas Gleixner 2020-10-07 14:10 ` David Woodhouse 2020-10-07 14:10 ` David Woodhouse 2020-10-07 15:57 ` Thomas Gleixner 2020-10-07 15:57 ` Thomas Gleixner 2020-10-07 16:11 ` David Woodhouse 2020-10-07 16:11 ` David Woodhouse 2020-10-07 20:53 ` Thomas Gleixner 2020-10-07 20:53 ` Thomas Gleixner 2020-10-08 7:21 ` David Woodhouse 2020-10-08 7:21 ` David Woodhouse 2020-10-08 9:34 ` Thomas Gleixner 2020-10-08 9:34 ` Thomas Gleixner 2020-10-08 11:10 ` David Woodhouse 2020-10-08 11:10 ` David Woodhouse 2020-10-08 12:40 ` Thomas Gleixner 2020-10-08 12:40 ` Thomas Gleixner 2020-10-09 7:54 ` David Woodhouse 2020-10-09 7:54 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 08/13] genirq: Add irq_domain_set_affinity() David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 21:32 ` Thomas Gleixner 2020-10-06 21:32 ` Thomas Gleixner 2020-10-07 7:22 ` David Woodhouse 2020-10-07 7:22 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 09/13] x86/irq: Add x86_non_ir_cpumask David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 21:42 ` Thomas Gleixner 2020-10-06 21:42 ` Thomas Gleixner 2020-10-07 7:25 ` David Woodhouse 2020-10-07 7:25 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 10/13] x86/irq: Limit IOAPIC and MSI domains' affinity without IR David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-06 21:54 ` Thomas Gleixner [this message] 2020-10-06 21:54 ` Thomas Gleixner 2020-10-07 7:48 ` David Woodhouse 2020-10-07 7:48 ` David Woodhouse 2020-10-07 12:59 ` Thomas Gleixner 2020-10-07 12:59 ` Thomas Gleixner 2020-10-07 13:08 ` David Woodhouse 2020-10-07 13:08 ` David Woodhouse 2020-10-07 14:05 ` Thomas Gleixner 2020-10-07 14:05 ` Thomas Gleixner 2020-10-07 14:23 ` David Woodhouse 2020-10-07 14:23 ` David Woodhouse 2020-10-07 16:02 ` Thomas Gleixner 2020-10-07 16:02 ` Thomas Gleixner 2020-10-07 16:15 ` David Woodhouse 2020-10-07 16:15 ` David Woodhouse 2020-10-07 15:05 ` David Woodhouse 2020-10-07 15:05 ` David Woodhouse 2020-10-07 15:25 ` Thomas Gleixner 2020-10-07 15:25 ` Thomas Gleixner 2020-10-07 15:46 ` David Woodhouse 2020-10-07 15:46 ` David Woodhouse 2020-10-07 17:23 ` Thomas Gleixner 2020-10-07 17:23 ` Thomas Gleixner 2020-10-07 17:34 ` David Woodhouse 2020-10-07 17:34 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 11/13] x86/smp: Allow more than 255 CPUs even without interrupt remapping David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 12/13] iommu/irq_remapping: Kill most of hyperv-iommu.c now it's redundant David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 13/13] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse 2020-10-05 15:28 ` David Woodhouse 2020-10-07 8:14 ` Paolo Bonzini 2020-10-07 8:14 ` Paolo Bonzini 2020-10-07 8:59 ` David Woodhouse 2020-10-07 8:59 ` David Woodhouse 2020-10-07 11:15 ` Paolo Bonzini 2020-10-07 11:15 ` Paolo Bonzini 2020-10-07 12:04 ` David Woodhouse 2020-10-07 12:04 ` David Woodhouse
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