From: "Björn Töpel" <bjorn@kernel.org> To: Vineet Gupta <vineetg@rivosinc.com>, Andy Chiu <andy.chiu@sifive.com>, linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, guoren@linux.alibaba.com, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Andrew Jones <ajones@ventanamicro.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Conor Dooley <conor.dooley@microchip.com>, Jisheng Zhang <jszhang@kernel.org>, Vincent Chen <vincent.chen@sifive.com>, Guo Ren <guoren@kernel.org>, Li Zhengyu <lizhengyu3@huawei.com>, Masahiro Yamada <masahiroy@kernel.org>, Richard Henderson <richard.henderson@linaro.org> Subject: Re: [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Date: Tue, 14 Feb 2023 07:43:21 +0100 [thread overview] Message-ID: <87sff8ags6.fsf@all.your.base.are.belong.to.us> (raw) In-Reply-To: <82551518-7b7e-8ac9-7325-5d99d3be0406@rivosinc.com> Vineet Gupta <vineetg@rivosinc.com> writes: > On 2/7/23 06:36, Björn Töpel wrote: >>> +bool rvv_first_use_handler(struct pt_regs *regs) >>> +{ >>> + __user u32 *epc = (u32 *)regs->epc; >>> + u32 tval = (u32)regs->badaddr; >>> + >>> + /* If V has been enabled then it is not the first-use trap */ >>> + if (vstate_query(regs)) >>> + return false; >>> + /* Get the instruction */ >>> + if (!tval) { >>> + if (__get_user(tval, epc)) >>> + return false; >>> + } >>> + /* Filter out non-V instructions */ >>> + if (!insn_is_vector(tval)) >>> + return false; >>> + /* Sanity check. datap should be null by the time of the first-use trap */ >>> + WARN_ON(current->thread.vstate.datap); >>> + /* >>> + * Now we sure that this is a V instruction. And it executes in the >>> + * context where VS has been off. So, try to allocate the user's V >>> + * context and resume execution. >>> + */ >>> + if (rvv_thread_zalloc()) { >>> + force_sig(SIGKILL); >>> + return true; >>> + } >> Should the altstack size be taken into consideration, like x86 does in >> validate_sigaltstack() (see __xstate_request_perm()). > > For a preexisting alternate stack ? Yes. > Otherwise there is no > "configuration" like x86 to cross-check against and V fault implies > large'ish signal stack. > See below as well. > >> Related; Would it make sense to implement sigaltstack_size_valid() for >> riscv, analogous to x86? > > Indeed we need to do that for the case where alt stack is being setup, > *after* V fault-on-first use. > But how to handle an existing alt stack which might not be big enough to > handle V state ? What I'm getting at is a stricter check at the time of fault (SIGILL/enable V) handling. If the *existing* altstack is not big enough, kill the process -- similar to the rvv_thread_zalloc() handling above. So, two changes: 1. Disallow V-enablement if the existing altstack does not fit a V-sized frame. 2. Sanitize altstack changes when V is enabled. Other than the altstack handling, I think the series is a good state! It would great if we could see a v14 land in -next... Björn
WARNING: multiple messages have this Message-ID (diff)
From: "Björn Töpel" <bjorn@kernel.org> To: Vineet Gupta <vineetg@rivosinc.com>, Andy Chiu <andy.chiu@sifive.com>, linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, guoren@linux.alibaba.com, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Andrew Jones <ajones@ventanamicro.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Conor Dooley <conor.dooley@microchip.com>, Jisheng Zhang <jszhang@kernel.org>, Vincent Chen <vincent.chen@sifive.com>, Guo Ren <guoren@kernel.org>, Li Zhengyu <lizhengyu3@huawei.com>, Masahiro Yamada <masahiroy@kernel.org>, Richard Henderson <richard.henderson@linaro.org> Subject: Re: [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Date: Tue, 14 Feb 2023 07:43:21 +0100 [thread overview] Message-ID: <87sff8ags6.fsf@all.your.base.are.belong.to.us> (raw) In-Reply-To: <82551518-7b7e-8ac9-7325-5d99d3be0406@rivosinc.com> Vineet Gupta <vineetg@rivosinc.com> writes: > On 2/7/23 06:36, Björn Töpel wrote: >>> +bool rvv_first_use_handler(struct pt_regs *regs) >>> +{ >>> + __user u32 *epc = (u32 *)regs->epc; >>> + u32 tval = (u32)regs->badaddr; >>> + >>> + /* If V has been enabled then it is not the first-use trap */ >>> + if (vstate_query(regs)) >>> + return false; >>> + /* Get the instruction */ >>> + if (!tval) { >>> + if (__get_user(tval, epc)) >>> + return false; >>> + } >>> + /* Filter out non-V instructions */ >>> + if (!insn_is_vector(tval)) >>> + return false; >>> + /* Sanity check. datap should be null by the time of the first-use trap */ >>> + WARN_ON(current->thread.vstate.datap); >>> + /* >>> + * Now we sure that this is a V instruction. And it executes in the >>> + * context where VS has been off. So, try to allocate the user's V >>> + * context and resume execution. >>> + */ >>> + if (rvv_thread_zalloc()) { >>> + force_sig(SIGKILL); >>> + return true; >>> + } >> Should the altstack size be taken into consideration, like x86 does in >> validate_sigaltstack() (see __xstate_request_perm()). > > For a preexisting alternate stack ? Yes. > Otherwise there is no > "configuration" like x86 to cross-check against and V fault implies > large'ish signal stack. > See below as well. > >> Related; Would it make sense to implement sigaltstack_size_valid() for >> riscv, analogous to x86? > > Indeed we need to do that for the case where alt stack is being setup, > *after* V fault-on-first use. > But how to handle an existing alt stack which might not be big enough to > handle V state ? What I'm getting at is a stricter check at the time of fault (SIGILL/enable V) handling. If the *existing* altstack is not big enough, kill the process -- similar to the rvv_thread_zalloc() handling above. So, two changes: 1. Disallow V-enablement if the existing altstack does not fit a V-sized frame. 2. Sanitize altstack changes when V is enabled. Other than the altstack handling, I think the series is a good state! It would great if we could see a v14 land in -next... Björn _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-14 6:43 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:15 ` Conor Dooley 2023-01-25 21:15 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:33 ` Conor Dooley 2023-01-25 21:33 ` Conor Dooley 2023-01-28 7:09 ` Guo Ren 2023-01-28 7:09 ` Guo Ren 2023-01-28 10:28 ` Conor Dooley 2023-01-28 10:28 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 22:16 ` Conor Dooley 2023-01-25 22:16 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 22:18 ` Conor Dooley 2023-01-25 22:18 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:51 ` Conor Dooley 2023-01-25 21:51 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:06 ` Conor Dooley 2023-01-26 21:06 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:24 ` Conor Dooley 2023-01-26 21:24 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:32 ` Conor Dooley 2023-01-26 21:32 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:44 ` Conor Dooley 2023-01-26 21:44 ` Conor Dooley 2023-01-31 2:55 ` Vineet Gupta 2023-01-31 2:55 ` Vineet Gupta 2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:11 ` Conor Dooley 2023-01-26 23:11 ` Conor Dooley 2023-02-06 12:00 ` Andy Chiu 2023-02-06 12:00 ` Andy Chiu 2023-02-06 13:40 ` Conor Dooley 2023-02-06 13:40 ` Conor Dooley 2023-02-10 12:00 ` Andy Chiu 2023-02-10 12:00 ` Andy Chiu 2023-02-07 14:36 ` Björn Töpel 2023-02-07 14:36 ` Björn Töpel 2023-02-13 22:54 ` Vineet Gupta 2023-02-13 22:54 ` Vineet Gupta 2023-02-14 6:43 ` Björn Töpel [this message] 2023-02-14 6:43 ` Björn Töpel 2023-02-14 15:36 ` Andy Chiu 2023-02-14 15:36 ` Andy Chiu 2023-02-14 16:50 ` Björn Töpel 2023-02-14 16:50 ` Björn Töpel 2023-02-14 17:24 ` Vineet Gupta 2023-02-14 17:24 ` Vineet Gupta 2023-02-15 7:14 ` Björn Töpel 2023-02-15 7:14 ` Björn Töpel 2023-02-15 14:39 ` Andy Chiu 2023-02-15 14:39 ` Andy Chiu 2023-02-07 21:18 ` Vineet Gupta 2023-02-07 21:18 ` Vineet Gupta 2023-02-08 9:20 ` Björn Töpel 2023-02-08 9:20 ` Björn Töpel 2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:19 ` Conor Dooley 2023-01-26 23:19 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:31 ` Conor Dooley 2023-01-27 20:31 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:43 ` Conor Dooley 2023-01-27 20:43 ` Conor Dooley 2023-01-30 9:58 ` Andy Chiu 2023-01-30 9:58 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 11:28 ` Anup Patel 2023-01-27 11:28 ` Anup Patel 2023-01-30 8:18 ` Andy Chiu 2023-01-30 8:18 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 22:24 ` Conor Dooley 2023-01-25 22:24 ` Conor Dooley 2023-01-30 6:38 ` Andy Chiu 2023-01-30 6:38 ` Andy Chiu 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 7:46 ` Andy Chiu 2023-01-30 7:46 ` Andy Chiu 2023-01-30 8:13 ` Conor Dooley 2023-01-30 8:13 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley
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