From: Conor Dooley <conor@kernel.org> To: Jessica Clarke <jrtc27@jrtc27.com> Cc: Andy Chiu <andy.chiu@sifive.com>, linux-riscv <linux-riscv@lists.infradead.org>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Vineet Gupta <vineetg@rivosinc.com>, Greentime Hu <greentime.hu@sifive.com>, Guo Ren <guoren@linux.alibaba.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: Re: [PATCH -next v13 19/19] riscv: Enable Vector code to be built Date: Wed, 25 Jan 2023 22:24:00 +0000 [thread overview] Message-ID: <Y9GsAOPMVX4qGero@spud> (raw) In-Reply-To: <08DF16C6-1D76-4FBE-871C-3A37C5349C87@jrtc27.com> [-- Attachment #1: Type: text/plain, Size: 3111 bytes --] On Wed, Jan 25, 2023 at 09:38:00PM +0000, Jessica Clarke wrote: > On 25 Jan 2023, at 21:04, Conor Dooley <conor@kernel.org> wrote: > > On Wed, Jan 25, 2023 at 02:20:56PM +0000, Andy Chiu wrote: > > > >> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > >> index 12d91b0a73d8..67411cdc836f 100644 > >> --- a/arch/riscv/Makefile > >> +++ b/arch/riscv/Makefile > >> @@ -52,6 +52,13 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > >> riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > >> riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > >> riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > >> +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v > >> + > >> +ifeq ($(CONFIG_RISCV_ISA_V), y) > >> +ifeq ($(CONFIG_CC_IS_CLANG), y) > >> + riscv-march-y += -mno-implicit-float -menable-experimental-extensions > >> +endif > >> +endif > > > > Uh, so I don't think this was actually tested with (a recent version of) > > clang: > > clang-15: error: unknown argument: '-menable-experimental-extensions_zicbom_zihintpause' > > > > Firstly, no-implicit-float is a CFLAG, so why add it to march? > > There is an existing patch on the list for enabling this flag, but I > > recall Palmer saying that it was not actually needed? > > Palmer, do you remember why that was? > > > > I dunno what enable-experimental-extensions is, but I can guess. Do we > > really want to enable vector for toolchains where the support is > > considered experimental? I'm not au fait with the details of clang > > versions nor versions of the Vector spec, so take the following with a > > bit of a pinch of salt... > > Since you've allowed this to be built with anything later than clang 13, > > does that mean that different versions of clang may generate vector code > > that are not compatible? > > I'm especially concerned by: > > https://github.com/riscv/riscv-v-spec/releases/tag/0.9 > > which appears to be most recently released version of the spec, prior to > > clang/llvm 13 being released. > > For implementations of unratified extensions you both have to enable > them with -menable-experimental-extensions and have to explicitly > specify the version in the -march string specifically so this isn’t a > concern. Only once ratified can you use the unversioned extension, > which is implicitly the ratified version (ignoring the whole i2p0 vs > i2p1 fiasco). Ahh, thanks for the clarification Jess. > But no, you probably don’t want experimental implementations, which can > exist when the ratified version is implemented in theory (so there’s no > compatibility concern based on ISA changes) but isn’t deemed > production-ready (e.g. potential ABI instability in the case of > something like V). And I guess, if you turn it on for one, it's on for all. While the vector extension might be okay in that regard, another extension well not be okay to use the "unversioned" experimental version of. Sounds like removing that option and picking the version of clang that adds the actual implementation is a better approach, at least IMO. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
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From: Conor Dooley <conor@kernel.org> To: Jessica Clarke <jrtc27@jrtc27.com> Cc: Andy Chiu <andy.chiu@sifive.com>, linux-riscv <linux-riscv@lists.infradead.org>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Vineet Gupta <vineetg@rivosinc.com>, Greentime Hu <greentime.hu@sifive.com>, Guo Ren <guoren@linux.alibaba.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: Re: [PATCH -next v13 19/19] riscv: Enable Vector code to be built Date: Wed, 25 Jan 2023 22:24:00 +0000 [thread overview] Message-ID: <Y9GsAOPMVX4qGero@spud> (raw) In-Reply-To: <08DF16C6-1D76-4FBE-871C-3A37C5349C87@jrtc27.com> [-- Attachment #1.1: Type: text/plain, Size: 3111 bytes --] On Wed, Jan 25, 2023 at 09:38:00PM +0000, Jessica Clarke wrote: > On 25 Jan 2023, at 21:04, Conor Dooley <conor@kernel.org> wrote: > > On Wed, Jan 25, 2023 at 02:20:56PM +0000, Andy Chiu wrote: > > > >> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > >> index 12d91b0a73d8..67411cdc836f 100644 > >> --- a/arch/riscv/Makefile > >> +++ b/arch/riscv/Makefile > >> @@ -52,6 +52,13 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > >> riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > >> riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > >> riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > >> +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v > >> + > >> +ifeq ($(CONFIG_RISCV_ISA_V), y) > >> +ifeq ($(CONFIG_CC_IS_CLANG), y) > >> + riscv-march-y += -mno-implicit-float -menable-experimental-extensions > >> +endif > >> +endif > > > > Uh, so I don't think this was actually tested with (a recent version of) > > clang: > > clang-15: error: unknown argument: '-menable-experimental-extensions_zicbom_zihintpause' > > > > Firstly, no-implicit-float is a CFLAG, so why add it to march? > > There is an existing patch on the list for enabling this flag, but I > > recall Palmer saying that it was not actually needed? > > Palmer, do you remember why that was? > > > > I dunno what enable-experimental-extensions is, but I can guess. Do we > > really want to enable vector for toolchains where the support is > > considered experimental? I'm not au fait with the details of clang > > versions nor versions of the Vector spec, so take the following with a > > bit of a pinch of salt... > > Since you've allowed this to be built with anything later than clang 13, > > does that mean that different versions of clang may generate vector code > > that are not compatible? > > I'm especially concerned by: > > https://github.com/riscv/riscv-v-spec/releases/tag/0.9 > > which appears to be most recently released version of the spec, prior to > > clang/llvm 13 being released. > > For implementations of unratified extensions you both have to enable > them with -menable-experimental-extensions and have to explicitly > specify the version in the -march string specifically so this isn’t a > concern. Only once ratified can you use the unversioned extension, > which is implicitly the ratified version (ignoring the whole i2p0 vs > i2p1 fiasco). Ahh, thanks for the clarification Jess. > But no, you probably don’t want experimental implementations, which can > exist when the ratified version is implemented in theory (so there’s no > compatibility concern based on ISA changes) but isn’t deemed > production-ready (e.g. potential ABI instability in the case of > something like V). And I guess, if you turn it on for one, it's on for all. While the vector extension might be okay in that regard, another extension well not be okay to use the "unversioned" experimental version of. Sounds like removing that option and picking the version of clang that adds the actual implementation is a better approach, at least IMO. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-25 22:24 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:15 ` Conor Dooley 2023-01-25 21:15 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:33 ` Conor Dooley 2023-01-25 21:33 ` Conor Dooley 2023-01-28 7:09 ` Guo Ren 2023-01-28 7:09 ` Guo Ren 2023-01-28 10:28 ` Conor Dooley 2023-01-28 10:28 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 22:16 ` Conor Dooley 2023-01-25 22:16 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 22:18 ` Conor Dooley 2023-01-25 22:18 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:51 ` Conor Dooley 2023-01-25 21:51 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:06 ` Conor Dooley 2023-01-26 21:06 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:24 ` Conor Dooley 2023-01-26 21:24 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:32 ` Conor Dooley 2023-01-26 21:32 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:44 ` Conor Dooley 2023-01-26 21:44 ` Conor Dooley 2023-01-31 2:55 ` Vineet Gupta 2023-01-31 2:55 ` Vineet Gupta 2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:11 ` Conor Dooley 2023-01-26 23:11 ` Conor Dooley 2023-02-06 12:00 ` Andy Chiu 2023-02-06 12:00 ` Andy Chiu 2023-02-06 13:40 ` Conor Dooley 2023-02-06 13:40 ` Conor Dooley 2023-02-10 12:00 ` Andy Chiu 2023-02-10 12:00 ` Andy Chiu 2023-02-07 14:36 ` Björn Töpel 2023-02-07 14:36 ` Björn Töpel 2023-02-13 22:54 ` Vineet Gupta 2023-02-13 22:54 ` Vineet Gupta 2023-02-14 6:43 ` Björn Töpel 2023-02-14 6:43 ` Björn Töpel 2023-02-14 15:36 ` Andy Chiu 2023-02-14 15:36 ` Andy Chiu 2023-02-14 16:50 ` Björn Töpel 2023-02-14 16:50 ` Björn Töpel 2023-02-14 17:24 ` Vineet Gupta 2023-02-14 17:24 ` Vineet Gupta 2023-02-15 7:14 ` Björn Töpel 2023-02-15 7:14 ` Björn Töpel 2023-02-15 14:39 ` Andy Chiu 2023-02-15 14:39 ` Andy Chiu 2023-02-07 21:18 ` Vineet Gupta 2023-02-07 21:18 ` Vineet Gupta 2023-02-08 9:20 ` Björn Töpel 2023-02-08 9:20 ` Björn Töpel 2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:19 ` Conor Dooley 2023-01-26 23:19 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:31 ` Conor Dooley 2023-01-27 20:31 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:43 ` Conor Dooley 2023-01-27 20:43 ` Conor Dooley 2023-01-30 9:58 ` Andy Chiu 2023-01-30 9:58 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 11:28 ` Anup Patel 2023-01-27 11:28 ` Anup Patel 2023-01-30 8:18 ` Andy Chiu 2023-01-30 8:18 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 22:24 ` Conor Dooley [this message] 2023-01-25 22:24 ` Conor Dooley 2023-01-30 6:38 ` Andy Chiu 2023-01-30 6:38 ` Andy Chiu 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 7:46 ` Andy Chiu 2023-01-30 7:46 ` Andy Chiu 2023-01-30 8:13 ` Conor Dooley 2023-01-30 8:13 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley
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