From: Rob Clark <robdclark@gmail.com>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
freedreno <freedreno@lists.freedesktop.org>,
"Kristian H . Kristensen" <hoegsberg@google.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
"list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>,
Joerg Roedel <joro@8bytes.org>,"
<iommu@lists.linux-foundation.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCHv8 0/8] System Cache support for GPU and required SMMU support
Date: Mon, 23 Nov 2020 11:22:31 -0800 [thread overview]
Message-ID: <CAF6AEGse=WBAC1WbTi6aD5_m1_NBg91f=veYm-7V=Uds7NA0Lw@mail.gmail.com> (raw)
In-Reply-To: <50b68f2bdf9413b896fbe816ba4ddbc9@codeaurora.org>
On Mon, Nov 23, 2020 at 9:01 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2020-11-23 20:51, Will Deacon wrote:
> > On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
> >> Some hardware variants contain a system cache or the last level
> >> cache(llc). This cache is typically a large block which is shared
> >> by multiple clients on the SOC. GPU uses the system cache to cache
> >> both the GPU data buffers(like textures) as well the SMMU pagetables.
> >> This helps with improved render performance as well as lower power
> >> consumption by reducing the bus traffic to the system memory.
> >>
> >> The system cache architecture allows the cache to be split into slices
> >> which then be used by multiple SOC clients. This patch series is an
> >> effort to enable and use two of those slices preallocated for the GPU,
> >> one for the GPU data buffers and another for the GPU SMMU hardware
> >> pagetables.
> >>
> >> Patch 1 - Patch 6 adds system cache support in SMMU and GPU driver.
> >> Patch 7 and 8 are minor cleanups for arm-smmu impl.
> >>
> >> Changes in v8:
> >> * Introduce a generic domain attribute for pagetable config (Will)
> >> * Rename quirk to more generic IO_PGTABLE_QUIRK_ARM_OUTER_WBWA (Will)
> >> * Move non-strict mode to use new struct domain_attr_io_pgtbl_config
> >> (Will)
> >
> > Modulo some minor comments I've made, this looks good to me. What is
> > the
> > plan for merging it? I can take the IOMMU parts, but patches 4-6 touch
> > the
> > MSM GPU driver and I'd like to avoid conflicts with that.
> >
>
> SMMU bits are pretty much independent and GPU relies on the domain
> attribute
> and the quirk exposed, so as long as SMMU changes go in first it should
> be good.
> Rob?
I suppose one option would be to split out the patch that adds the
attribute into it's own patch, and merge that both thru drm and iommu?
If Will/Robin dislike that approach, I'll pick up the parts of the drm
patches which don't depend on the new attribute for v5.11 and the rest
for v5.12.. or possibly a second late v5.11 pull req if airlied
doesn't hate me too much for it.
Going forward, I think we will have one or two more co-dependent
series, like the smmu iova fault handler improvements that Jordan
posted. So I would like to hear how Will and Robin prefer to handle
those.
BR,
-R
> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: Rob Clark <robdclark@gmail.com>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Will Deacon <will@kernel.org>,
freedreno <freedreno@lists.freedesktop.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>,
Joerg Roedel <joro@8bytes.org>,
" <iommu@lists.linux-foundation.org>,
"Kristian H . Kristensen" <hoegsberg@google.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCHv8 0/8] System Cache support for GPU and required SMMU support
Date: Mon, 23 Nov 2020 11:22:31 -0800 [thread overview]
Message-ID: <CAF6AEGse=WBAC1WbTi6aD5_m1_NBg91f=veYm-7V=Uds7NA0Lw@mail.gmail.com> (raw)
In-Reply-To: <50b68f2bdf9413b896fbe816ba4ddbc9@codeaurora.org>
On Mon, Nov 23, 2020 at 9:01 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2020-11-23 20:51, Will Deacon wrote:
> > On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
> >> Some hardware variants contain a system cache or the last level
> >> cache(llc). This cache is typically a large block which is shared
> >> by multiple clients on the SOC. GPU uses the system cache to cache
> >> both the GPU data buffers(like textures) as well the SMMU pagetables.
> >> This helps with improved render performance as well as lower power
> >> consumption by reducing the bus traffic to the system memory.
> >>
> >> The system cache architecture allows the cache to be split into slices
> >> which then be used by multiple SOC clients. This patch series is an
> >> effort to enable and use two of those slices preallocated for the GPU,
> >> one for the GPU data buffers and another for the GPU SMMU hardware
> >> pagetables.
> >>
> >> Patch 1 - Patch 6 adds system cache support in SMMU and GPU driver.
> >> Patch 7 and 8 are minor cleanups for arm-smmu impl.
> >>
> >> Changes in v8:
> >> * Introduce a generic domain attribute for pagetable config (Will)
> >> * Rename quirk to more generic IO_PGTABLE_QUIRK_ARM_OUTER_WBWA (Will)
> >> * Move non-strict mode to use new struct domain_attr_io_pgtbl_config
> >> (Will)
> >
> > Modulo some minor comments I've made, this looks good to me. What is
> > the
> > plan for merging it? I can take the IOMMU parts, but patches 4-6 touch
> > the
> > MSM GPU driver and I'd like to avoid conflicts with that.
> >
>
> SMMU bits are pretty much independent and GPU relies on the domain
> attribute
> and the quirk exposed, so as long as SMMU changes go in first it should
> be good.
> Rob?
I suppose one option would be to split out the patch that adds the
attribute into it's own patch, and merge that both thru drm and iommu?
If Will/Robin dislike that approach, I'll pick up the parts of the drm
patches which don't depend on the new attribute for v5.11 and the rest
for v5.12.. or possibly a second late v5.11 pull req if airlied
doesn't hate me too much for it.
Going forward, I think we will have one or two more co-dependent
series, like the smmu iova fault handler improvements that Jordan
posted. So I would like to hear how Will and Robin prefer to handle
those.
BR,
-R
> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Rob Clark <robdclark@gmail.com>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Will Deacon <will@kernel.org>,
freedreno <freedreno@lists.freedesktop.org>,
Joerg Roedel <joro@8bytes.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
"list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>,
Joerg Roedel <joro@8bytes.org>,
" <iommu@lists.linux-foundation.org>,
"Kristian H . Kristensen" <hoegsberg@google.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCHv8 0/8] System Cache support for GPU and required SMMU support
Date: Mon, 23 Nov 2020 11:22:31 -0800 [thread overview]
Message-ID: <CAF6AEGse=WBAC1WbTi6aD5_m1_NBg91f=veYm-7V=Uds7NA0Lw@mail.gmail.com> (raw)
In-Reply-To: <50b68f2bdf9413b896fbe816ba4ddbc9@codeaurora.org>
On Mon, Nov 23, 2020 at 9:01 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2020-11-23 20:51, Will Deacon wrote:
> > On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
> >> Some hardware variants contain a system cache or the last level
> >> cache(llc). This cache is typically a large block which is shared
> >> by multiple clients on the SOC. GPU uses the system cache to cache
> >> both the GPU data buffers(like textures) as well the SMMU pagetables.
> >> This helps with improved render performance as well as lower power
> >> consumption by reducing the bus traffic to the system memory.
> >>
> >> The system cache architecture allows the cache to be split into slices
> >> which then be used by multiple SOC clients. This patch series is an
> >> effort to enable and use two of those slices preallocated for the GPU,
> >> one for the GPU data buffers and another for the GPU SMMU hardware
> >> pagetables.
> >>
> >> Patch 1 - Patch 6 adds system cache support in SMMU and GPU driver.
> >> Patch 7 and 8 are minor cleanups for arm-smmu impl.
> >>
> >> Changes in v8:
> >> * Introduce a generic domain attribute for pagetable config (Will)
> >> * Rename quirk to more generic IO_PGTABLE_QUIRK_ARM_OUTER_WBWA (Will)
> >> * Move non-strict mode to use new struct domain_attr_io_pgtbl_config
> >> (Will)
> >
> > Modulo some minor comments I've made, this looks good to me. What is
> > the
> > plan for merging it? I can take the IOMMU parts, but patches 4-6 touch
> > the
> > MSM GPU driver and I'd like to avoid conflicts with that.
> >
>
> SMMU bits are pretty much independent and GPU relies on the domain
> attribute
> and the quirk exposed, so as long as SMMU changes go in first it should
> be good.
> Rob?
I suppose one option would be to split out the patch that adds the
attribute into it's own patch, and merge that both thru drm and iommu?
If Will/Robin dislike that approach, I'll pick up the parts of the drm
patches which don't depend on the new attribute for v5.11 and the rest
for v5.12.. or possibly a second late v5.11 pull req if airlied
doesn't hate me too much for it.
Going forward, I think we will have one or two more co-dependent
series, like the smmu iova fault handler improvements that Jordan
posted. So I would like to hear how Will and Robin prefer to handle
those.
BR,
-R
> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Rob Clark <robdclark@gmail.com>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Will Deacon <will@kernel.org>,
freedreno <freedreno@lists.freedesktop.org>,
Joerg Roedel <joro@8bytes.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>,
Joerg Roedel <joro@8bytes.org>,
" <iommu@lists.linux-foundation.org>,
"Kristian H . Kristensen" <hoegsberg@google.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCHv8 0/8] System Cache support for GPU and required SMMU support
Date: Mon, 23 Nov 2020 11:22:31 -0800 [thread overview]
Message-ID: <CAF6AEGse=WBAC1WbTi6aD5_m1_NBg91f=veYm-7V=Uds7NA0Lw@mail.gmail.com> (raw)
In-Reply-To: <50b68f2bdf9413b896fbe816ba4ddbc9@codeaurora.org>
On Mon, Nov 23, 2020 at 9:01 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2020-11-23 20:51, Will Deacon wrote:
> > On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
> >> Some hardware variants contain a system cache or the last level
> >> cache(llc). This cache is typically a large block which is shared
> >> by multiple clients on the SOC. GPU uses the system cache to cache
> >> both the GPU data buffers(like textures) as well the SMMU pagetables.
> >> This helps with improved render performance as well as lower power
> >> consumption by reducing the bus traffic to the system memory.
> >>
> >> The system cache architecture allows the cache to be split into slices
> >> which then be used by multiple SOC clients. This patch series is an
> >> effort to enable and use two of those slices preallocated for the GPU,
> >> one for the GPU data buffers and another for the GPU SMMU hardware
> >> pagetables.
> >>
> >> Patch 1 - Patch 6 adds system cache support in SMMU and GPU driver.
> >> Patch 7 and 8 are minor cleanups for arm-smmu impl.
> >>
> >> Changes in v8:
> >> * Introduce a generic domain attribute for pagetable config (Will)
> >> * Rename quirk to more generic IO_PGTABLE_QUIRK_ARM_OUTER_WBWA (Will)
> >> * Move non-strict mode to use new struct domain_attr_io_pgtbl_config
> >> (Will)
> >
> > Modulo some minor comments I've made, this looks good to me. What is
> > the
> > plan for merging it? I can take the IOMMU parts, but patches 4-6 touch
> > the
> > MSM GPU driver and I'd like to avoid conflicts with that.
> >
>
> SMMU bits are pretty much independent and GPU relies on the domain
> attribute
> and the quirk exposed, so as long as SMMU changes go in first it should
> be good.
> Rob?
I suppose one option would be to split out the patch that adds the
attribute into it's own patch, and merge that both thru drm and iommu?
If Will/Robin dislike that approach, I'll pick up the parts of the drm
patches which don't depend on the new attribute for v5.11 and the rest
for v5.12.. or possibly a second late v5.11 pull req if airlied
doesn't hate me too much for it.
Going forward, I think we will have one or two more co-dependent
series, like the smmu iova fault handler improvements that Jordan
posted. So I would like to hear how Will and Robin prefer to handle
those.
BR,
-R
> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-11-23 19:20 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-17 14:30 [PATCHv8 0/8] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 1/8] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-23 15:06 ` Will Deacon
2020-11-23 15:06 ` Will Deacon
2020-11-23 15:06 ` Will Deacon
2020-11-23 15:06 ` Will Deacon
2020-11-23 16:41 ` Sai Prakash Ranjan
2020-11-23 16:41 ` Sai Prakash Ranjan
2020-11-23 16:41 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 2/8] iommu/arm-smmu: Add domain attribute for pagetable configuration Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-23 15:18 ` Will Deacon
2020-11-23 15:18 ` Will Deacon
2020-11-23 15:18 ` Will Deacon
2020-11-23 15:18 ` Will Deacon
2020-11-23 16:42 ` Sai Prakash Ranjan
2020-11-23 16:42 ` Sai Prakash Ranjan
2020-11-23 16:42 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 3/8] iommu/arm-smmu: Move non-strict mode to use domain_attr_io_pgtbl_cfg Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-23 15:19 ` Will Deacon
2020-11-23 15:19 ` Will Deacon
2020-11-23 15:19 ` Will Deacon
2020-11-23 15:19 ` Will Deacon
2020-11-23 16:43 ` Sai Prakash Ranjan
2020-11-23 16:43 ` Sai Prakash Ranjan
2020-11-23 16:43 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 4/8] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 5/8] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 6/8] drm/msm/a6xx: Add support for using system cache on MMU500 based targets Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 7/8] iommu: arm-smmu-impl: Use table to list QCOM implementations Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` [PATCHv8 8/8] iommu: arm-smmu-impl: Add a space before open parenthesis Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-17 14:30 ` Sai Prakash Ranjan
2020-11-23 15:21 ` [PATCHv8 0/8] System Cache support for GPU and required SMMU support Will Deacon
2020-11-23 15:21 ` Will Deacon
2020-11-23 15:21 ` Will Deacon
2020-11-23 15:21 ` Will Deacon
2020-11-23 17:01 ` Sai Prakash Ranjan
2020-11-23 17:01 ` Sai Prakash Ranjan
2020-11-23 17:01 ` Sai Prakash Ranjan
2020-11-23 19:22 ` Rob Clark [this message]
2020-11-23 19:22 ` Rob Clark
2020-11-23 19:22 ` Rob Clark
2020-11-23 19:22 ` Rob Clark
2020-11-24 4:02 ` Sai Prakash Ranjan
2020-11-24 4:02 ` Sai Prakash Ranjan
2020-11-24 4:02 ` Sai Prakash Ranjan
2020-11-24 11:10 ` Will Deacon
2020-11-24 11:10 ` Will Deacon
2020-11-24 11:10 ` Will Deacon
2020-11-24 11:10 ` Will Deacon
2020-11-24 19:05 ` Rob Clark
2020-11-24 19:05 ` Rob Clark
2020-11-24 19:05 ` Rob Clark
2020-11-24 19:05 ` Rob Clark
2020-11-24 21:43 ` Will Deacon
2020-11-24 21:43 ` Will Deacon
2020-11-24 21:43 ` Will Deacon
2020-11-24 21:43 ` Will Deacon
2020-11-24 22:08 ` Rob Clark
2020-11-24 22:08 ` Rob Clark
2020-11-24 22:08 ` Rob Clark
2020-11-24 22:08 ` Rob Clark
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