All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mark Brown <broonie@kernel.org>
To: Serge Semin <fancer.lancer@gmail.com>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	nandhini.srikandan@intel.com, robh+dt@kernel.org,
	linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, mgross@linux.intel.com,
	kris.pan@intel.com, kenchappa.demakkanavar@intel.com,
	furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com,
	mahesh.r.vaidya@intel.com, rashmi.a@intel.com
Subject: Re: [PATCH v3 3/5] spi: dw: Add support for master mode selection for DWC SSI controller
Date: Thu, 11 Nov 2021 16:25:02 +0000	[thread overview]
Message-ID: <YY1D3tM4fg8h6mmj@sirena.org.uk> (raw)
In-Reply-To: <20211111160627.fcgrvj2k7x3lwtkp@mobilestation>

[-- Attachment #1: Type: text/plain, Size: 1946 bytes --]

On Thu, Nov 11, 2021 at 07:06:27PM +0300, Serge Semin wrote:
> On Thu, Nov 11, 2021 at 03:14:26PM +0000, Mark Brown wrote:

> > Given that people seem to frequently customise these IPs when
> > integrating them I wouldn't trust people not to have added some other
> > control into that reserved bit doing some magic stuff that's useful in
> > their system.

> In that case the corresponding platform code would have needed to have
> that peculiarity properly handled and not to use a generic compatibles
> like "snps,dwc-ssi-1.01a" or "snps,dw-apb-ssi", which are supposed to
> be utilized for the default IP-core configs only. For the sake of the
> code simplification I'd stick to setting that flag for each generic
> DWC SSI-compatible device. That will be also helpful for DWC SSIs
> which for some reason have the slave-mode enabled by default.

That's easier right up until the point where it explodes - I'd prefer to
be more conservative here.  Fixing things up after the fact gets painful
when people end up only finding the bug in released kernels, especially
if it's distro end users or similar rather than developers.

> Alternatively the driver could read the IP-core version from the
> DW_SPI_VERSION register, parse it (since it's in ASCII) and then use
> it in the conditional Master mode activation here. But that could have
> been a better solution in case if the older IP-cores would have used
> that bit for something special, while Nandhini claims it was reserved.
> So in this case I would stick with a simpler approach until we get to
> face any problem in this matter, especially seeing we already pocking
> the reserved bits of the CTRL0 register in this driver in the
> spi_hw_init() method when it comes to the DFS field width detection.

If the device has a version register checking that seems ideal - the
infrastructure will most likely be useful in future anyway.  A bit of a
shame that it's an ASCII string though.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

  reply	other threads:[~2021-11-11 16:25 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-11  6:51 [PATCH v3 0/5] Add support for Intel Thunder Bay SPI controller nandhini.srikandan
2021-11-11  6:51 ` [PATCH v3 1/5] dt-bindings: spi: Add SSTE support for DWC SSI controller nandhini.srikandan
2021-11-11 13:53   ` Mark Brown
2021-11-11 14:31   ` Serge Semin
2021-11-11 15:01     ` Mark Brown
2021-11-11 15:06       ` Serge Semin
2021-11-17 12:05         ` Srikandan, Nandhini
2021-11-11  6:51 ` [PATCH v3 2/5] spi: dw: " nandhini.srikandan
2021-11-11 13:56   ` Mark Brown
2021-11-11 14:16     ` Serge Semin
2021-11-11 14:42   ` Serge Semin
2021-11-11  6:51 ` [PATCH v3 3/5] spi: dw: Add support for master mode selection " nandhini.srikandan
2021-11-11 14:16   ` Mark Brown
2021-11-11 14:52     ` Serge Semin
2021-11-11 15:14       ` Mark Brown
2021-11-11 16:06         ` Serge Semin
2021-11-11 16:25           ` Mark Brown [this message]
2021-11-16 19:15             ` Serge Semin
2021-11-17 11:59               ` Srikandan, Nandhini
2021-12-08 11:03                 ` Srikandan, Nandhini
2021-12-09  8:40                   ` Serge Semin
2021-11-11  6:52 ` [PATCH v3 4/5] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC nandhini.srikandan
2021-11-19 16:55   ` Rob Herring
2021-11-11  6:52 ` [PATCH v3 5/5] spi: dw: Add support for Intel Thunder Bay SPI controller nandhini.srikandan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YY1D3tM4fg8h6mmj@sirena.org.uk \
    --to=broonie@kernel.org \
    --cc=Sergey.Semin@baikalelectronics.ru \
    --cc=devicetree@vger.kernel.org \
    --cc=fancer.lancer@gmail.com \
    --cc=furong.zhou@intel.com \
    --cc=kenchappa.demakkanavar@intel.com \
    --cc=kris.pan@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-spi@vger.kernel.org \
    --cc=mahesh.r.vaidya@intel.com \
    --cc=mallikarjunappa.sangannavar@intel.com \
    --cc=mgross@linux.intel.com \
    --cc=nandhini.srikandan@intel.com \
    --cc=rashmi.a@intel.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.