All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andi Shyti <andi.shyti@linux.intel.com>
To: fei.yang@intel.com
Cc: Matt Roper <matthew.d.roper@intel.com>,
	intel-gfx@lists.freedesktop.org,
	Chris Wilson <chris.p.wilson@linux.intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 6/8] drm/i915: preparation for using PAT index
Date: Wed, 19 Apr 2023 13:17:23 +0200	[thread overview]
Message-ID: <ZD/Nw3lb5G7nvqps@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230417062503.1884465-7-fei.yang@intel.com>

Hi Fei,

[...]

> @@ -180,6 +182,14 @@ struct drm_i915_private *mock_gem_device(void)
>  		I915_GTT_PAGE_SIZE_2M;
>  
>  	RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
> +
> +

double space here, otherwise:

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Andi

> +	/* simply use legacy cache level for mock device */
> +	i915_info = (struct intel_device_info *)INTEL_INFO(i915);
> +	i915_info->max_pat_index = 3;
> +	for (i = 0; i < I915_MAX_CACHE_LEVEL; i++)
> +		i915_info->cachelevel_to_pat[i] = i;
> +
>  	intel_memory_regions_hw_probe(i915);
>  
>  	spin_lock_init(&i915->gpu_error.lock);
> -- 
> 2.25.1

WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: fei.yang@intel.com
Cc: Matt Roper <matthew.d.roper@intel.com>,
	intel-gfx@lists.freedesktop.org,
	Chris Wilson <chris.p.wilson@linux.intel.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/8] drm/i915: preparation for using PAT index
Date: Wed, 19 Apr 2023 13:17:23 +0200	[thread overview]
Message-ID: <ZD/Nw3lb5G7nvqps@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230417062503.1884465-7-fei.yang@intel.com>

Hi Fei,

[...]

> @@ -180,6 +182,14 @@ struct drm_i915_private *mock_gem_device(void)
>  		I915_GTT_PAGE_SIZE_2M;
>  
>  	RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
> +
> +

double space here, otherwise:

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Andi

> +	/* simply use legacy cache level for mock device */
> +	i915_info = (struct intel_device_info *)INTEL_INFO(i915);
> +	i915_info->max_pat_index = 3;
> +	for (i = 0; i < I915_MAX_CACHE_LEVEL; i++)
> +		i915_info->cachelevel_to_pat[i] = i;
> +
>  	intel_memory_regions_hw_probe(i915);
>  
>  	spin_lock_init(&i915->gpu_error.lock);
> -- 
> 2.25.1

  reply	other threads:[~2023-04-19 11:17 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-17  6:24 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-17  6:24 ` [Intel-gfx] " fei.yang
2023-04-17  6:24 ` [PATCH 1/8] drm/i915/mtl: Set has_llc=0 fei.yang
2023-04-17  6:24   ` [Intel-gfx] " fei.yang
2023-04-19 10:59   ` Andi Shyti
2023-04-19 12:50   ` Andrzej Hajda
2023-04-19 14:10   ` Das, Nirmoy
2023-04-17  6:24 ` [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-17  6:24   ` [Intel-gfx] " fei.yang
2023-04-19 11:01   ` Andi Shyti
2023-04-19 16:00     ` Yang, Fei
2023-04-19 16:00       ` Yang, Fei
2023-04-19 13:59   ` Andrzej Hajda
2023-04-19 16:03     ` Yang, Fei
2023-04-19 16:03       ` Yang, Fei
2023-04-19 14:36   ` Das, Nirmoy
2023-04-19 16:05     ` Yang, Fei
2023-04-19 16:05       ` Yang, Fei
2023-04-17  6:24 ` [PATCH 3/8] drm/i915/mtl: Add PTE encode function fei.yang
2023-04-17  6:24   ` [Intel-gfx] " fei.yang
2023-04-19 11:02   ` Andi Shyti
2023-04-19 12:51   ` Andrzej Hajda
2023-04-19 15:11   ` Das, Nirmoy
2023-04-19 15:11     ` [Intel-gfx] " Das, Nirmoy
2023-04-17  6:24 ` [PATCH 4/8] drm/i915/mtl: workaround coherency issue for Media fei.yang
2023-04-17  6:24   ` [Intel-gfx] " fei.yang
2023-04-19 10:59   ` Andi Shyti
2023-04-19 12:38     ` Andi Shyti
2023-04-19 15:14   ` Das, Nirmoy
2023-04-19 15:14     ` [Intel-gfx] " Das, Nirmoy
2023-04-19 15:40   ` Andrzej Hajda
2023-04-19 16:37     ` Yang, Fei
2023-04-19 16:37       ` Yang, Fei
2023-04-19 18:49       ` Yang, Fei
2023-04-19 18:49         ` Yang, Fei
2023-04-17  6:25 ` [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang
2023-04-17  6:25   ` [Intel-gfx] " fei.yang
2023-04-19 11:08   ` Andi Shyti
2023-04-19 13:05   ` Andrzej Hajda
2023-04-19 16:56     ` Yang, Fei
2023-04-19 16:56       ` Yang, Fei
2023-04-17  6:25 ` [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang
2023-04-17  6:25   ` [Intel-gfx] " fei.yang
2023-04-19 11:17   ` Andi Shyti [this message]
2023-04-19 11:17     ` Andi Shyti
2023-04-17  6:25 ` [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang
2023-04-17  6:25   ` [Intel-gfx] " fei.yang
2023-04-19 12:16   ` Andi Shyti
2023-04-17  6:25 ` [PATCH 8/8] drm/i915: Allow user to set cache at BO creation fei.yang
2023-04-17  6:25   ` [Intel-gfx] " fei.yang
2023-04-19 12:23   ` Andi Shyti
2023-04-19 12:23     ` [Intel-gfx] " Andi Shyti
2023-04-17  6:32 ` [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL Timo Aaltonen
2023-04-17  6:43   ` Yang, Fei
2023-04-17  6:43     ` Yang, Fei
2023-04-24 20:00     ` Jordan Justen
2023-04-24 20:00       ` Jordan Justen
2023-04-17 11:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev5) Patchwork
2023-04-17 11:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-17 12:15 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-19 18:09 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-19 18:09 ` [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang
2023-04-19 21:12 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-19 21:12 ` [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang
2023-04-19 22:12   ` Andi Shyti
2023-04-19 23:00 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-19 23:00 ` [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZD/Nw3lb5G7nvqps@ashyti-mobl2.lan \
    --to=andi.shyti@linux.intel.com \
    --cc=chris.p.wilson@linux.intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=fei.yang@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.d.roper@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.