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From: David Hildenbrand <david@redhat.com>
To: debug@rivosinc.com, rick.p.edgecombe@intel.com,
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Subject: Re: [RFC PATCH v1 08/28] mm: Define VM_SHADOW_STACK for RISC-V
Date: Thu, 25 Jan 2024 09:17:01 +0100	[thread overview]
Message-ID: <a6f3ccf5-26a0-45f1-adaa-56a8df569548@redhat.com> (raw)
In-Reply-To: <20240125062739.1339782-9-debug@rivosinc.com>

On 25.01.24 07:21, debug@rivosinc.com wrote:
> From: Deepak Gupta <debug@rivosinc.com>
> 
> VM_SHADOW_STACK is defined by x86 as vm flag to mark a shadow stack vma.
> 
> x86 uses VM_HIGH_ARCH_5 bit but that limits shadow stack vma to 64bit only.
> arm64 follows same path
> https://lore.kernel.org/lkml/20231009-arm64-gcs-v6-12-78e55deaa4dd@kernel.org/#r
> 
> On RISC-V, write-only page table encodings are shadow stack pages. This patch
> re-defines VM_WRITE only to be VM_SHADOW_STACK.
> 
> Next set of patches will set guard rail that no other mm flow can set VM_WRITE
> only in vma except when specifically creating shadow stack.
> 
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
>   include/linux/mm.h | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index 418d26608ece..dfe0e8118669 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -352,7 +352,19 @@ extern unsigned int kobjsize(const void *objp);
>    * for more details on the guard size.
>    */
>   # define VM_SHADOW_STACK	VM_HIGH_ARCH_5
> -#else
> +#endif
> +
> +#ifdef CONFIG_RISCV_USER_CFI
> +/*
> + * On RISC-V pte encodings for shadow stack is R=0, W=1, X=0 and thus RISCV
> + * choosing to use similar mechanism on vm_flags where VM_WRITE only means
> + * VM_SHADOW_STACK. RISCV as well doesn't support VM_SHADOW_STACK to be set
> + * with VM_SHARED.
> + */
> +#define VM_SHADOW_STACK	VM_WRITE
> +#endif
> +
> +#ifndef VM_SHADOW_STACK
>   # define VM_SHADOW_STACK	VM_NONE
>   #endif
>   

That just screams for trouble. Can we find a less hacky way, please?

Maybe just start with 64bit support only and do it like the other archs. 
No need to be special.

When wanting to support 32bit, we'll just finally clean up this high 
flag mess and allow for more vm flags on 32bit as well.

-- 
Cheers,

David / dhildenb


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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: David Hildenbrand <david@redhat.com>
To: debug@rivosinc.com, rick.p.edgecombe@intel.com,
	broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com,
	keescook@chromium.org, ajones@ventanamicro.com,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	conor.dooley@microchip.com, cleger@rivosinc.com,
	atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com,
	alexghiti@rivosinc.com
Cc: corbet@lwn.net, aou@eecs.berkeley.edu, oleg@redhat.com,
	akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com,
	shuah@kernel.org, brauner@kernel.org, guoren@kernel.org,
	samitolvanen@google.com, evan@rivosinc.com,
	xiao.w.wang@intel.com, apatel@ventanamicro.com,
	mchitale@ventanamicro.com, waylingii@gmail.com,
	greentime.hu@sifive.com, heiko@sntech.de, jszhang@kernel.org,
	shikemeng@huaweicloud.com, charlie@rivosinc.com,
	panqinglin2020@iscas.ac.cn, willy@infradead.org,
	vincent.chen@sifive.com, andy.chiu@sifive.com, gerg@kernel.org,
	jeeheng.sia@starfivetech.com, mason.huo@starfivetech.com,
	ancientmodern4@gmail.com, mathis.salmen@matsal.de,
	cuiyunhui@bytedance.com, bhe@redhat.com, chenjiahao16@huawei.com,
	ruscur@russell.cc, bgray@linux.ibm.com, alx@kernel.org,
	baruch@tkos.co.il, zhangqing@loongson.cn,
	catalin.marinas@arm.com, revest@chromium.org,
	josh@joshtriplett.org, joey.gouly@arm.com, shr@devkernel.io,
	omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com,
	linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [RFC PATCH v1 08/28] mm: Define VM_SHADOW_STACK for RISC-V
Date: Thu, 25 Jan 2024 09:17:01 +0100	[thread overview]
Message-ID: <a6f3ccf5-26a0-45f1-adaa-56a8df569548@redhat.com> (raw)
In-Reply-To: <20240125062739.1339782-9-debug@rivosinc.com>

On 25.01.24 07:21, debug@rivosinc.com wrote:
> From: Deepak Gupta <debug@rivosinc.com>
> 
> VM_SHADOW_STACK is defined by x86 as vm flag to mark a shadow stack vma.
> 
> x86 uses VM_HIGH_ARCH_5 bit but that limits shadow stack vma to 64bit only.
> arm64 follows same path
> https://lore.kernel.org/lkml/20231009-arm64-gcs-v6-12-78e55deaa4dd@kernel.org/#r
> 
> On RISC-V, write-only page table encodings are shadow stack pages. This patch
> re-defines VM_WRITE only to be VM_SHADOW_STACK.
> 
> Next set of patches will set guard rail that no other mm flow can set VM_WRITE
> only in vma except when specifically creating shadow stack.
> 
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
>   include/linux/mm.h | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index 418d26608ece..dfe0e8118669 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -352,7 +352,19 @@ extern unsigned int kobjsize(const void *objp);
>    * for more details on the guard size.
>    */
>   # define VM_SHADOW_STACK	VM_HIGH_ARCH_5
> -#else
> +#endif
> +
> +#ifdef CONFIG_RISCV_USER_CFI
> +/*
> + * On RISC-V pte encodings for shadow stack is R=0, W=1, X=0 and thus RISCV
> + * choosing to use similar mechanism on vm_flags where VM_WRITE only means
> + * VM_SHADOW_STACK. RISCV as well doesn't support VM_SHADOW_STACK to be set
> + * with VM_SHARED.
> + */
> +#define VM_SHADOW_STACK	VM_WRITE
> +#endif
> +
> +#ifndef VM_SHADOW_STACK
>   # define VM_SHADOW_STACK	VM_NONE
>   #endif
>   

That just screams for trouble. Can we find a less hacky way, please?

Maybe just start with 64bit support only and do it like the other archs. 
No need to be special.

When wanting to support 32bit, we'll just finally clean up this high 
flag mess and allow for more vm flags on 32bit as well.

-- 
Cheers,

David / dhildenb


  reply	other threads:[~2024-01-25  8:17 UTC|newest]

Thread overview: 122+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-25  6:21 [RFC PATCH v1 00/28] riscv control-flow integrity for usermode debug
2024-01-25  6:21 ` debug
2024-01-25  6:21 ` [RFC PATCH v1 01/28] riscv: abstract envcfg CSR debug
2024-01-25  6:21   ` debug
2024-02-12 10:23   ` Andrew Jones
2024-02-12 10:23     ` Andrew Jones
2024-01-25  6:21 ` [RFC PATCH v1 02/28] riscv: envcfg save and restore on trap entry/exit debug
2024-01-25  6:21   ` debug
2024-01-25  7:19   ` Stefan O'Rear
2024-01-25  7:19     ` Stefan O'Rear
2024-01-25 17:09     ` Deepak Gupta
2024-01-25 17:09       ` Deepak Gupta
2024-01-25 17:54       ` Deepak Gupta
2024-01-25 17:54         ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 03/28] riscv: define default value for envcfg debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 04/28] riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 05/28] riscv: zicfiss/zicfilp enumeration debug
2024-01-25  6:21   ` debug
2024-01-25 17:59   ` Conor Dooley
2024-01-25 17:59     ` Conor Dooley
2024-01-25 18:26     ` Deepak Gupta
2024-01-25 18:26       ` Deepak Gupta
2024-01-25 18:46       ` Conor Dooley
2024-01-25 18:46         ` Conor Dooley
2024-01-25  6:21 ` [RFC PATCH v1 06/28] riscv: zicfiss/zicfilp extension csr and bit definitions debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 07/28] riscv: kernel handling on trap entry/exit for user cfi debug
2024-01-25  6:21   ` debug
2024-01-25  7:29   ` Stefan O'Rear
2024-01-25  7:29     ` Stefan O'Rear
2024-01-25 17:30     ` Deepak Gupta
2024-01-25 17:30       ` Deepak Gupta
2024-01-25 19:47       ` Stefan O'Rear
2024-01-25 19:47         ` Stefan O'Rear
2024-01-26  0:25         ` Deepak Gupta
2024-01-26  0:25           ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 08/28] mm: Define VM_SHADOW_STACK for RISC-V debug
2024-01-25  6:21   ` debug
2024-01-25  8:17   ` David Hildenbrand [this message]
2024-01-25  8:17     ` David Hildenbrand
2024-01-25 17:05     ` Deepak Gupta
2024-01-25 17:05       ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 09/28] mm: abstract shadow stack vma behind `arch_is_shadow_stack` debug
2024-01-25  6:21   ` debug
2024-01-25  8:18   ` David Hildenbrand
2024-01-25  8:18     ` David Hildenbrand
2024-01-25 17:07     ` Deepak Gupta
2024-01-25 17:07       ` Deepak Gupta
2024-02-13 10:34       ` David Hildenbrand
2024-02-13 10:34         ` David Hildenbrand
2024-02-22  1:32         ` Deepak Gupta
2024-02-22  1:32           ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 10/28] riscv/mm : Introducing new protection flag "PROT_SHADOWSTACK" debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 11/28] riscv: Implementing "PROT_SHADOWSTACK" on riscv debug
2024-01-25  6:21   ` debug
2024-02-09 20:44   ` Edgecombe, Rick P
2024-02-09 20:44     ` Edgecombe, Rick P
2024-02-22  0:39     ` Deepak Gupta
2024-02-22  0:39       ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 12/28] riscv mm: manufacture shadow stack pte debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 13/28] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 14/28] riscv mmu: write protect and shadow stack debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 15/28] riscv/mm: Implement map_shadow_stack() syscall debug
2024-01-25  6:21   ` debug
2024-01-25 21:24   ` Charlie Jenkins
2024-01-25 21:24     ` Charlie Jenkins
2024-01-26  0:44     ` Deepak Gupta
2024-01-26  0:44       ` Deepak Gupta
2024-02-06 16:01   ` Mark Brown
2024-02-06 16:01     ` Mark Brown
2024-02-22  0:47     ` Deepak Gupta
2024-02-22  0:47       ` Deepak Gupta
2024-02-22 13:33       ` Mark Brown
2024-02-22 13:33         ` Mark Brown
2024-02-09 20:44   ` Edgecombe, Rick P
2024-02-09 20:44     ` Edgecombe, Rick P
2024-02-22  0:50     ` Deepak Gupta
2024-02-22  0:50       ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 16/28] riscv/shstk: If needed allocate a new shadow stack on clone debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 17/28] prctl: arch-agnostic prctl for shadow stack debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 18/28] prctl: arch-agnostic prtcl for indirect branch tracking debug
2024-01-25  6:21   ` debug
2024-02-06 16:13   ` Mark Brown
2024-02-06 16:13     ` Mark Brown
2024-02-22  0:42     ` Deepak Gupta
2024-02-22  0:42       ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 19/28] riscv: Implements arch agnostic shadow stack prctls debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 20/28] riscv: Implements arch argnostic indirect branch tracking prctls debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 21/28] riscv/traps: Introduce software check exception debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 22/28] riscv sigcontext: adding cfi state field in sigcontext debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 23/28] riscv signal: Save and restore of shadow stack for signal debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 24/28] riscv: select config for shadow stack and landing pad instr support debug
2024-01-25  6:21   ` debug
2024-01-25 18:04   ` Conor Dooley
2024-01-25 18:04     ` Conor Dooley
2024-01-25 18:12     ` Deepak Gupta
2024-01-25 18:12       ` Deepak Gupta
2024-01-25 18:44       ` Conor Dooley
2024-01-25 18:44         ` Conor Dooley
2024-01-25 19:26         ` Deepak Gupta
2024-01-25 19:26           ` Deepak Gupta
2024-01-25  6:21 ` [RFC PATCH v1 25/28] riscv/ptrace: riscv cfi status and state via ptrace and in core files debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 26/28] riscv: Documentation for landing pad / indirect branch tracking debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 27/28] riscv: Documentation for shadow stack on riscv debug
2024-01-25  6:21   ` debug
2024-01-25  6:21 ` [RFC PATCH v1 28/28] kselftest/riscv: kselftest for user mode cfi debug
2024-01-25  6:21   ` debug

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