* [PATCH V2 0/7] Add device tree based discovery support for drm-fimd
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
The patches are created against "for-next" branch of Kukjin Kim's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
This patch set adds Backlight, LCD support and device tree based discovery
support for drm-fimd.
This patchset has been tested on smdk5250 board and seen the bootup logo on LCD.
The documentation for bindings has been posted to mainline. Please refer to the
link http://www.spinics.net/lists/dri-devel/msg24862.html
Changes since V1:
- Removed unwanted empty lines for below patches
ARM: EXYNOS5: add machine specific support for backlight
ARM: EXYNOS5: add machine specific support for LCD
ARM: EXYNOS5: Set parent clock to fimd
Leela Krishna Amudala (7):
ARM: SAMSUNG: add additional registers and SFR definitions for
writeback
ARM: EXYNOS5: add machine specific support for backlight
ARM: EXYNOS5: add machine specific support for LCD
ARM: EXYNOS: Adding DRM platform device
ARM: EXYNOS: add device tree based discovery support for FIMD
ARM: EXYNOS5: Add the bus clock for FIMD
ARM: EXYNOS5: Set parent clock to fimd
arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 +++
arch/arm/boot/dts/exynos5250.dtsi | 7 ++
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/clock-exynos5.c | 30 ++++--
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 123 +++++++++++++++++++++++
arch/arm/plat-samsung/include/plat/clock.h | 2 +
arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++
arch/arm/plat-samsung/include/plat/regs-fb.h | 51 ++++++++++
drivers/video/Kconfig | 6 +
10 files changed, 237 insertions(+), 10 deletions(-)
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
This patch updates the register address offsets and adds SFR definitions
for writeback for Samsung's V8 display controller.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
drivers/video/Kconfig | 6 +++
3 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
index 4c3647f..1639c17 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
@@ -30,9 +30,16 @@
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDTCON0 (0x20010)
+#define VIDTCON1 (0x20014)
+#define VIDTCON3 (0x2001C)
+#else
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
+#define VIDTCON3 (0x1C)
+#endif
/* Window position controls */
@@ -43,9 +50,12 @@
#define VIDOSD_BASE (0x40)
#define VIDINTCON0 (0x130)
+#define VIDINTCON1 (0x134)
/* WINCONx */
+#define WINCONx_CSC_CON_EQ709 (1 << 28)
+#define WINCONx_CSC_CON_EQ601 (0 << 28)
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 9a78012..6d2ee16 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -32,12 +32,28 @@
#define VIDCON0 (0x00)
#define VIDCON0_INTERLACE (1 << 29)
+
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDOUT_CON (0x20000)
+#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
+#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
+#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
+#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
+#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
+#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
+#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
+#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
+#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
+#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
+#endif
+
#define VIDCON0_VIDOUT_MASK (0x3 << 26)
#define VIDCON0_VIDOUT_SHIFT (26)
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
+#define VIDCON0_VIDOUT_WB (0x4 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT (23)
@@ -81,7 +97,13 @@
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDOUT_CON (0x20000)
+#define VIDCON1 (0x20004)
+#else
#define VIDCON1 (0x04)
+#endif
+
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT (16)
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
@@ -111,6 +133,14 @@
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
+#define VIDCON2_TVFMTSEL1_SHIFT (12)
+#define VIDCON2_TVFMTSEL_SW (1 << 14)
+#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
+
+#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
+#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
+#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
+#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
#define VIDCON2_ORGYCbCr (1 << 8)
#define VIDCON2_YUVORDCrCb (1 << 7)
@@ -165,8 +195,15 @@
#define VIDTCON1_HSPW_SHIFT (0)
#define VIDTCON1_HSPW_LIMIT (0xff)
#define VIDTCON1_HSPW(_x) ((_x) << 0)
+#define VIDCON1_VCLK_MASK (0x3 << 9)
+#define VIDCON1_VCLK_HOLD (0x0 << 9)
+#define VIDCON1_VCLK_RUN (0x1 << 9)
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDTCON2 (0x20018)
+#else
#define VIDTCON2 (0x18)
+#endif
#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT (11)
@@ -186,6 +223,9 @@
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_WSWP (1 << 15)
+#define WINCONx_ENLOCAL_MASK (0xf << 15)
+#define WINCONx_INRGB_RGB (0 << 13)
+#define WINCONx_INRGB_YCBCR (1 << 13)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT (9)
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
@@ -205,6 +245,7 @@
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BLD_PIX (1 << 6)
+#define WINCON1_BLD_PLANE (0 << 6)
#define WINCON1_ALPHA_SEL (1 << 1)
#define WINCON1_BPPMODE_MASK (0xf << 2)
@@ -395,9 +436,19 @@
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
+/* Clock gate mode control */
+#define REG_CLKGATE_MODE (0x1b0)
+#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
+#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
+
/* Blending equation control */
#define BLENDCON (0x260)
#define BLENDCON_NEW_MASK (1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
+/* Window alpha control */
+#define VIDW0ALPHA0 (0x200)
+#define VIDW0ALPHA1 (0x204)
+#define DPCLKCON (0x27c)
+#define DPCLKCON_ENABLE (1 << 1)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..f81bf55 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2053,6 +2053,12 @@ config FB_S3C
Currently the support is only for the S3C6400 and S3C6410 SoCs.
+config FB_EXYNOS_FIMD_V8
+ bool "register extensions for FIMD version 8"
+ depends on ARCH_EXYNOS5
+ ---help---
+ This uses register extensions for FIMD version 8
+
config FB_S3C_DEBUG_REGWRITE
bool "Debug register writes"
depends on FB_S3C
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the register address offsets and adds SFR definitions
for writeback for Samsung's V8 display controller.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
drivers/video/Kconfig | 6 +++
3 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
index 4c3647f..1639c17 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
@@ -30,9 +30,16 @@
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDTCON0 (0x20010)
+#define VIDTCON1 (0x20014)
+#define VIDTCON3 (0x2001C)
+#else
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
+#define VIDTCON3 (0x1C)
+#endif
/* Window position controls */
@@ -43,9 +50,12 @@
#define VIDOSD_BASE (0x40)
#define VIDINTCON0 (0x130)
+#define VIDINTCON1 (0x134)
/* WINCONx */
+#define WINCONx_CSC_CON_EQ709 (1 << 28)
+#define WINCONx_CSC_CON_EQ601 (0 << 28)
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 9a78012..6d2ee16 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -32,12 +32,28 @@
#define VIDCON0 (0x00)
#define VIDCON0_INTERLACE (1 << 29)
+
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDOUT_CON (0x20000)
+#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
+#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
+#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
+#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
+#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
+#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
+#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
+#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
+#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
+#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
+#endif
+
#define VIDCON0_VIDOUT_MASK (0x3 << 26)
#define VIDCON0_VIDOUT_SHIFT (26)
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
+#define VIDCON0_VIDOUT_WB (0x4 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT (23)
@@ -81,7 +97,13 @@
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDOUT_CON (0x20000)
+#define VIDCON1 (0x20004)
+#else
#define VIDCON1 (0x04)
+#endif
+
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT (16)
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
@@ -111,6 +133,14 @@
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
+#define VIDCON2_TVFMTSEL1_SHIFT (12)
+#define VIDCON2_TVFMTSEL_SW (1 << 14)
+#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
+
+#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
+#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
+#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
+#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
#define VIDCON2_ORGYCbCr (1 << 8)
#define VIDCON2_YUVORDCrCb (1 << 7)
@@ -165,8 +195,15 @@
#define VIDTCON1_HSPW_SHIFT (0)
#define VIDTCON1_HSPW_LIMIT (0xff)
#define VIDTCON1_HSPW(_x) ((_x) << 0)
+#define VIDCON1_VCLK_MASK (0x3 << 9)
+#define VIDCON1_VCLK_HOLD (0x0 << 9)
+#define VIDCON1_VCLK_RUN (0x1 << 9)
+#ifdef CONFIG_FB_EXYNOS_FIMD_V8
+#define VIDTCON2 (0x20018)
+#else
#define VIDTCON2 (0x18)
+#endif
#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT (11)
@@ -186,6 +223,9 @@
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_WSWP (1 << 15)
+#define WINCONx_ENLOCAL_MASK (0xf << 15)
+#define WINCONx_INRGB_RGB (0 << 13)
+#define WINCONx_INRGB_YCBCR (1 << 13)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT (9)
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
@@ -205,6 +245,7 @@
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BLD_PIX (1 << 6)
+#define WINCON1_BLD_PLANE (0 << 6)
#define WINCON1_ALPHA_SEL (1 << 1)
#define WINCON1_BPPMODE_MASK (0xf << 2)
@@ -395,9 +436,19 @@
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
+/* Clock gate mode control */
+#define REG_CLKGATE_MODE (0x1b0)
+#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
+#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
+
/* Blending equation control */
#define BLENDCON (0x260)
#define BLENDCON_NEW_MASK (1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
+/* Window alpha control */
+#define VIDW0ALPHA0 (0x200)
+#define VIDW0ALPHA1 (0x204)
+#define DPCLKCON (0x27c)
+#define DPCLKCON_ENABLE (1 << 1)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..f81bf55 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2053,6 +2053,12 @@ config FB_S3C
Currently the support is only for the S3C6400 and S3C6410 SoCs.
+config FB_EXYNOS_FIMD_V8
+ bool "register extensions for FIMD version 8"
+ depends on ARCH_EXYNOS5
+ ---help---
+ This uses register extensions for FIMD version 8
+
config FB_S3C_DEBUG_REGWRITE
bool "Debug register writes"
depends on FB_S3C
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* RE: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 6:51 ` Marek Szyprowski
-1 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-18 6:51 UTC (permalink / raw)
To: 'Leela Krishna Amudala', devicetree-discuss, linux-arm-kernel
Cc: kgene.kim, jg1.han, joshi, grant.likely, linux-samsung-soc,
thomas.ab, olofj
Hello,
On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> This patch updates the register address offsets and adds SFR definitions
> for writeback for Samsung's V8 display controller.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
> drivers/video/Kconfig | 6 +++
> 3 files changed, 67 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
> samsung/include/plat/regs-fb-v4.h
> index 4c3647f..1639c17 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> @@ -30,9 +30,16 @@
> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>
> /* Video timing controls */
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON0 (0x20010)
> +#define VIDTCON1 (0x20014)
> +#define VIDTCON3 (0x2001C)
> +#else
> #define VIDTCON0 (0x10)
> #define VIDTCON1 (0x14)
> #define VIDTCON2 (0x18)
> +#define VIDTCON3 (0x1C)
> +#endif
>
> /* Window position controls */
>
> @@ -43,9 +50,12 @@
> #define VIDOSD_BASE (0x40)
>
> #define VIDINTCON0 (0x130)
> +#define VIDINTCON1 (0x134)
>
> /* WINCONx */
>
> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> #define WINCONx_CSCWIDTH_SHIFT (26)
> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
> samsung/include/plat/regs-fb.h
> index 9a78012..6d2ee16 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> @@ -32,12 +32,28 @@
>
> #define VIDCON0 (0x00)
> #define VIDCON0_INTERLACE (1 << 29)
> +
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> +#endif
> +
> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> #define VIDCON0_VIDOUT_SHIFT (26)
> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>
> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> #define VIDCON0_L1_DATA_SHIFT (23)
> @@ -81,7 +97,13 @@
> #define VIDCON0_ENVID (1 << 1)
> #define VIDCON0_ENVID_F (1 << 0)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDCON1 (0x20004)
> +#else
> #define VIDCON1 (0x04)
> +#endif
> +
> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> #define VIDCON1_LINECNT_SHIFT (16)
> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> @@ -111,6 +133,14 @@
> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> +
> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>
> #define VIDCON2_ORGYCbCr (1 << 8)
> #define VIDCON2_YUVORDCrCb (1 << 7)
> @@ -165,8 +195,15 @@
> #define VIDTCON1_HSPW_SHIFT (0)
> #define VIDTCON1_HSPW_LIMIT (0xff)
> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON2 (0x20018)
> +#else
> #define VIDTCON2 (0x18)
> +#endif
> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> #define VIDTCON2_LINEVAL_SHIFT (11)
> @@ -186,6 +223,9 @@
> #define WINCONx_BYTSWP (1 << 17)
> #define WINCONx_HAWSWP (1 << 16)
> #define WINCONx_WSWP (1 << 15)
> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> +#define WINCONx_INRGB_RGB (0 << 13)
> +#define WINCONx_INRGB_YCBCR (1 << 13)
> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> #define WINCONx_BURSTLEN_SHIFT (9)
> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> @@ -205,6 +245,7 @@
> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>
> #define WINCON1_BLD_PIX (1 << 6)
> +#define WINCON1_BLD_PLANE (0 << 6)
>
> #define WINCON1_ALPHA_SEL (1 << 1)
> #define WINCON1_BPPMODE_MASK (0xf << 2)
> @@ -395,9 +436,19 @@
> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>
> +/* Clock gate mode control */
> +#define REG_CLKGATE_MODE (0x1b0)
> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> +
> /* Blending equation control */
> #define BLENDCON (0x260)
> #define BLENDCON_NEW_MASK (1 << 0)
> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>
> +/* Window alpha control */
> +#define VIDW0ALPHA0 (0x200)
> +#define VIDW0ALPHA1 (0x204)
> +#define DPCLKCON (0x27c)
> +#define DPCLKCON_ENABLE (1 << 1)
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 0217f74..f81bf55 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -2053,6 +2053,12 @@ config FB_S3C
>
> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>
> +config FB_EXYNOS_FIMD_V8
> + bool "register extensions for FIMD version 8"
> + depends on ARCH_EXYNOS5
> + ---help---
> + This uses register extensions for FIMD version 8
> +
> config FB_S3C_DEBUG_REGWRITE
> bool "Debug register writes"
> depends on FB_S3C
Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
They are not a part of core platform code. I thought that there have been some patches
cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
mainline.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-18 6:51 ` Marek Szyprowski
0 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-18 6:51 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> This patch updates the register address offsets and adds SFR definitions
> for writeback for Samsung's V8 display controller.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
> drivers/video/Kconfig | 6 +++
> 3 files changed, 67 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
> samsung/include/plat/regs-fb-v4.h
> index 4c3647f..1639c17 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> @@ -30,9 +30,16 @@
> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>
> /* Video timing controls */
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON0 (0x20010)
> +#define VIDTCON1 (0x20014)
> +#define VIDTCON3 (0x2001C)
> +#else
> #define VIDTCON0 (0x10)
> #define VIDTCON1 (0x14)
> #define VIDTCON2 (0x18)
> +#define VIDTCON3 (0x1C)
> +#endif
>
> /* Window position controls */
>
> @@ -43,9 +50,12 @@
> #define VIDOSD_BASE (0x40)
>
> #define VIDINTCON0 (0x130)
> +#define VIDINTCON1 (0x134)
>
> /* WINCONx */
>
> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> #define WINCONx_CSCWIDTH_SHIFT (26)
> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
> samsung/include/plat/regs-fb.h
> index 9a78012..6d2ee16 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> @@ -32,12 +32,28 @@
>
> #define VIDCON0 (0x00)
> #define VIDCON0_INTERLACE (1 << 29)
> +
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> +#endif
> +
> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> #define VIDCON0_VIDOUT_SHIFT (26)
> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>
> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> #define VIDCON0_L1_DATA_SHIFT (23)
> @@ -81,7 +97,13 @@
> #define VIDCON0_ENVID (1 << 1)
> #define VIDCON0_ENVID_F (1 << 0)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDCON1 (0x20004)
> +#else
> #define VIDCON1 (0x04)
> +#endif
> +
> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> #define VIDCON1_LINECNT_SHIFT (16)
> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> @@ -111,6 +133,14 @@
> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> +
> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>
> #define VIDCON2_ORGYCbCr (1 << 8)
> #define VIDCON2_YUVORDCrCb (1 << 7)
> @@ -165,8 +195,15 @@
> #define VIDTCON1_HSPW_SHIFT (0)
> #define VIDTCON1_HSPW_LIMIT (0xff)
> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON2 (0x20018)
> +#else
> #define VIDTCON2 (0x18)
> +#endif
> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> #define VIDTCON2_LINEVAL_SHIFT (11)
> @@ -186,6 +223,9 @@
> #define WINCONx_BYTSWP (1 << 17)
> #define WINCONx_HAWSWP (1 << 16)
> #define WINCONx_WSWP (1 << 15)
> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> +#define WINCONx_INRGB_RGB (0 << 13)
> +#define WINCONx_INRGB_YCBCR (1 << 13)
> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> #define WINCONx_BURSTLEN_SHIFT (9)
> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> @@ -205,6 +245,7 @@
> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>
> #define WINCON1_BLD_PIX (1 << 6)
> +#define WINCON1_BLD_PLANE (0 << 6)
>
> #define WINCON1_ALPHA_SEL (1 << 1)
> #define WINCON1_BPPMODE_MASK (0xf << 2)
> @@ -395,9 +436,19 @@
> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>
> +/* Clock gate mode control */
> +#define REG_CLKGATE_MODE (0x1b0)
> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> +
> /* Blending equation control */
> #define BLENDCON (0x260)
> #define BLENDCON_NEW_MASK (1 << 0)
> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>
> +/* Window alpha control */
> +#define VIDW0ALPHA0 (0x200)
> +#define VIDW0ALPHA1 (0x204)
> +#define DPCLKCON (0x27c)
> +#define DPCLKCON_ENABLE (1 << 1)
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 0217f74..f81bf55 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -2053,6 +2053,12 @@ config FB_S3C
>
> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>
> +config FB_EXYNOS_FIMD_V8
> + bool "register extensions for FIMD version 8"
> + depends on ARCH_EXYNOS5
> + ---help---
> + This uses register extensions for FIMD version 8
> +
> config FB_S3C_DEBUG_REGWRITE
> bool "Debug register writes"
> depends on FB_S3C
Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
They are not a part of core platform code. I thought that there have been some patches
cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
mainline.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 6:51 ` Marek Szyprowski
@ 2012-07-18 7:09 ` Ajay kumar
-1 siblings, 0 replies; 84+ messages in thread
From: Ajay kumar @ 2012-07-18 7:09 UTC (permalink / raw)
To: Marek Szyprowski
Cc: Leela Krishna Amudala, devicetree-discuss, linux-arm-kernel,
kgene.kim, jg1.han, joshi, grant.likely, linux-samsung-soc,
thomas.ab, olofj
Hello Marek,
On Wed, Jul 18, 2012 at 12:21 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>
>> This patch updates the register address offsets and adds SFR definitions
>> for writeback for Samsung's V8 display controller.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
>> drivers/video/Kconfig | 6 +++
>> 3 files changed, 67 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb-v4.h
>> index 4c3647f..1639c17 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> @@ -30,9 +30,16 @@
>> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>>
>> /* Video timing controls */
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON0 (0x20010)
>> +#define VIDTCON1 (0x20014)
>> +#define VIDTCON3 (0x2001C)
>> +#else
>> #define VIDTCON0 (0x10)
>> #define VIDTCON1 (0x14)
>> #define VIDTCON2 (0x18)
>> +#define VIDTCON3 (0x1C)
>> +#endif
>>
>> /* Window position controls */
>>
>> @@ -43,9 +50,12 @@
>> #define VIDOSD_BASE (0x40)
>>
>> #define VIDINTCON0 (0x130)
>> +#define VIDINTCON1 (0x134)
>>
>> /* WINCONx */
>>
>> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> #define WINCONx_CSCWIDTH_SHIFT (26)
>> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb.h
>> index 9a78012..6d2ee16 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> @@ -32,12 +32,28 @@
>>
>> #define VIDCON0 (0x00)
>> #define VIDCON0_INTERLACE (1 << 29)
>> +
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> +#endif
>> +
>> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> #define VIDCON0_VIDOUT_SHIFT (26)
>> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>>
>> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> #define VIDCON0_L1_DATA_SHIFT (23)
>> @@ -81,7 +97,13 @@
>> #define VIDCON0_ENVID (1 << 1)
>> #define VIDCON0_ENVID_F (1 << 0)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDCON1 (0x20004)
>> +#else
>> #define VIDCON1 (0x04)
>> +#endif
>> +
>> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> #define VIDCON1_LINECNT_SHIFT (16)
>> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> @@ -111,6 +133,14 @@
>> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>>
>> #define VIDCON2_ORGYCbCr (1 << 8)
>> #define VIDCON2_YUVORDCrCb (1 << 7)
>> @@ -165,8 +195,15 @@
>> #define VIDTCON1_HSPW_SHIFT (0)
>> #define VIDTCON1_HSPW_LIMIT (0xff)
>> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON2 (0x20018)
>> +#else
>> #define VIDTCON2 (0x18)
>> +#endif
>> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> #define VIDTCON2_LINEVAL_SHIFT (11)
>> @@ -186,6 +223,9 @@
>> #define WINCONx_BYTSWP (1 << 17)
>> #define WINCONx_HAWSWP (1 << 16)
>> #define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> +#define WINCONx_INRGB_RGB (0 << 13)
>> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> #define WINCONx_BURSTLEN_SHIFT (9)
>> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> @@ -205,6 +245,7 @@
>> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>>
>> #define WINCON1_BLD_PIX (1 << 6)
>> +#define WINCON1_BLD_PLANE (0 << 6)
>>
>> #define WINCON1_ALPHA_SEL (1 << 1)
>> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> @@ -395,9 +436,19 @@
>> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>>
>> +/* Clock gate mode control */
>> +#define REG_CLKGATE_MODE (0x1b0)
>> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> +
>> /* Blending equation control */
>> #define BLENDCON (0x260)
>> #define BLENDCON_NEW_MASK (1 << 0)
>> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>>
>> +/* Window alpha control */
>> +#define VIDW0ALPHA0 (0x200)
>> +#define VIDW0ALPHA1 (0x204)
>> +#define DPCLKCON (0x27c)
>> +#define DPCLKCON_ENABLE (1 << 1)
>> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> index 0217f74..f81bf55 100644
>> --- a/drivers/video/Kconfig
>> +++ b/drivers/video/Kconfig
>> @@ -2053,6 +2053,12 @@ config FB_S3C
>>
>> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>>
>> +config FB_EXYNOS_FIMD_V8
>> + bool "register extensions for FIMD version 8"
>> + depends on ARCH_EXYNOS5
>> + ---help---
>> + This uses register extensions for FIMD version 8
>> +
>> config FB_S3C_DEBUG_REGWRITE
>> bool "Debug register writes"
>> depends on FB_S3C
>
> Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
> IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
> They are not a part of core platform code. I thought that there have been some patches
> cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
> mainline.
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/5826
These patches are merged.
I created the patchset. I felt it was redundant to have regs-fb.h in
individual samsung boards(arch/arm/mach-s*),
so I moved them to plat-samsung. We still need to move plat/regs-fb.h
to driver side.
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-18 7:09 ` Ajay kumar
0 siblings, 0 replies; 84+ messages in thread
From: Ajay kumar @ 2012-07-18 7:09 UTC (permalink / raw)
To: linux-arm-kernel
Hello Marek,
On Wed, Jul 18, 2012 at 12:21 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>
>> This patch updates the register address offsets and adds SFR definitions
>> for writeback for Samsung's V8 display controller.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
>> drivers/video/Kconfig | 6 +++
>> 3 files changed, 67 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb-v4.h
>> index 4c3647f..1639c17 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> @@ -30,9 +30,16 @@
>> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>>
>> /* Video timing controls */
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON0 (0x20010)
>> +#define VIDTCON1 (0x20014)
>> +#define VIDTCON3 (0x2001C)
>> +#else
>> #define VIDTCON0 (0x10)
>> #define VIDTCON1 (0x14)
>> #define VIDTCON2 (0x18)
>> +#define VIDTCON3 (0x1C)
>> +#endif
>>
>> /* Window position controls */
>>
>> @@ -43,9 +50,12 @@
>> #define VIDOSD_BASE (0x40)
>>
>> #define VIDINTCON0 (0x130)
>> +#define VIDINTCON1 (0x134)
>>
>> /* WINCONx */
>>
>> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> #define WINCONx_CSCWIDTH_SHIFT (26)
>> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb.h
>> index 9a78012..6d2ee16 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> @@ -32,12 +32,28 @@
>>
>> #define VIDCON0 (0x00)
>> #define VIDCON0_INTERLACE (1 << 29)
>> +
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> +#endif
>> +
>> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> #define VIDCON0_VIDOUT_SHIFT (26)
>> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>>
>> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> #define VIDCON0_L1_DATA_SHIFT (23)
>> @@ -81,7 +97,13 @@
>> #define VIDCON0_ENVID (1 << 1)
>> #define VIDCON0_ENVID_F (1 << 0)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDCON1 (0x20004)
>> +#else
>> #define VIDCON1 (0x04)
>> +#endif
>> +
>> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> #define VIDCON1_LINECNT_SHIFT (16)
>> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> @@ -111,6 +133,14 @@
>> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>>
>> #define VIDCON2_ORGYCbCr (1 << 8)
>> #define VIDCON2_YUVORDCrCb (1 << 7)
>> @@ -165,8 +195,15 @@
>> #define VIDTCON1_HSPW_SHIFT (0)
>> #define VIDTCON1_HSPW_LIMIT (0xff)
>> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON2 (0x20018)
>> +#else
>> #define VIDTCON2 (0x18)
>> +#endif
>> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> #define VIDTCON2_LINEVAL_SHIFT (11)
>> @@ -186,6 +223,9 @@
>> #define WINCONx_BYTSWP (1 << 17)
>> #define WINCONx_HAWSWP (1 << 16)
>> #define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> +#define WINCONx_INRGB_RGB (0 << 13)
>> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> #define WINCONx_BURSTLEN_SHIFT (9)
>> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> @@ -205,6 +245,7 @@
>> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>>
>> #define WINCON1_BLD_PIX (1 << 6)
>> +#define WINCON1_BLD_PLANE (0 << 6)
>>
>> #define WINCON1_ALPHA_SEL (1 << 1)
>> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> @@ -395,9 +436,19 @@
>> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>>
>> +/* Clock gate mode control */
>> +#define REG_CLKGATE_MODE (0x1b0)
>> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> +
>> /* Blending equation control */
>> #define BLENDCON (0x260)
>> #define BLENDCON_NEW_MASK (1 << 0)
>> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>>
>> +/* Window alpha control */
>> +#define VIDW0ALPHA0 (0x200)
>> +#define VIDW0ALPHA1 (0x204)
>> +#define DPCLKCON (0x27c)
>> +#define DPCLKCON_ENABLE (1 << 1)
>> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> index 0217f74..f81bf55 100644
>> --- a/drivers/video/Kconfig
>> +++ b/drivers/video/Kconfig
>> @@ -2053,6 +2053,12 @@ config FB_S3C
>>
>> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>>
>> +config FB_EXYNOS_FIMD_V8
>> + bool "register extensions for FIMD version 8"
>> + depends on ARCH_EXYNOS5
>> + ---help---
>> + This uses register extensions for FIMD version 8
>> +
>> config FB_S3C_DEBUG_REGWRITE
>> bool "Debug register writes"
>> depends on FB_S3C
>
> Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
> IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
> They are not a part of core platform code. I thought that there have been some patches
> cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
> mainline.
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/5826
These patches are merged.
I created the patchset. I felt it was redundant to have regs-fb.h in
individual samsung boards(arch/arm/mach-s*),
so I moved them to plat-samsung. We still need to move plat/regs-fb.h
to driver side.
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
[parent not found: <CAEC9eQP01q+ddhA9Q4VQcm8wuvJXmR5KvAVZgX6MEdFLstST0g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 7:09 ` Ajay kumar
@ 2012-07-20 10:09 ` Sylwester Nawrocki
-1 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-20 10:09 UTC (permalink / raw)
To: Ajay kumar
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, Leela Krishna Amudala,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
jg1.han-Sze3O3UU22JBDgjK7y7TUQ, joshi-Sze3O3UU22JBDgjK7y7TUQ,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
thomas.ab-Sze3O3UU22JBDgjK7y7TUQ, olofj-hpIqsD4AKlfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Marek Szyprowski
On 07/18/2012 09:09 AM, Ajay kumar wrote:
>>> +config FB_EXYNOS_FIMD_V8
>>> + bool "register extensions for FIMD version 8"
>>> + depends on ARCH_EXYNOS5
>>> + ---help---
>>> + This uses register extensions for FIMD version 8
>>> +
>>> config FB_S3C_DEBUG_REGWRITE
>>> bool "Debug register writes"
>>> depends on FB_S3C
>>
>> Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
>> IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
>> They are not a part of core platform code. I thought that there have been some patches
>> cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
>> mainline.
>
> http://comments.gmane.org/gmane.linux.kernel.samsung-soc/5826
>
> These patches are merged.
> I created the patchset. I felt it was redundant to have regs-fb.h in
> individual samsung boards(arch/arm/mach-s*),
> so I moved them to plat-samsung. We still need to move plat/regs-fb.h
> to driver side.
Great. These headers are now used by drivers/video/s3c-fb.c and
drivers/gpu/drm/exynos/exynos_drm_fimd.c, so we probably need to merge
them into one file under include/video.
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 10:09 ` Sylwester Nawrocki
0 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-20 10:09 UTC (permalink / raw)
To: linux-arm-kernel
On 07/18/2012 09:09 AM, Ajay kumar wrote:
>>> +config FB_EXYNOS_FIMD_V8
>>> + bool "register extensions for FIMD version 8"
>>> + depends on ARCH_EXYNOS5
>>> + ---help---
>>> + This uses register extensions for FIMD version 8
>>> +
>>> config FB_S3C_DEBUG_REGWRITE
>>> bool "Debug register writes"
>>> depends on FB_S3C
>>
>> Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
>> IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
>> They are not a part of core platform code. I thought that there have been some patches
>> cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
>> mainline.
>
> http://comments.gmane.org/gmane.linux.kernel.samsung-soc/5826
>
> These patches are merged.
> I created the patchset. I felt it was redundant to have regs-fb.h in
> individual samsung boards(arch/arm/mach-s*),
> so I moved them to plat-samsung. We still need to move plat/regs-fb.h
> to driver side.
Great. These headers are now used by drivers/video/s3c-fb.c and
drivers/gpu/drm/exynos/exynos_drm_fimd.c, so we probably need to merge
them into one file under include/video.
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 6:51 ` Marek Szyprowski
@ 2012-07-19 12:43 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-19 12:43 UTC (permalink / raw)
To: Marek Szyprowski
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
Hello Marek,
On Wed, Jul 18, 2012 at 12:21 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>
>> This patch updates the register address offsets and adds SFR definitions
>> for writeback for Samsung's V8 display controller.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
>> drivers/video/Kconfig | 6 +++
>> 3 files changed, 67 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb-v4.h
>> index 4c3647f..1639c17 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> @@ -30,9 +30,16 @@
>> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>>
>> /* Video timing controls */
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON0 (0x20010)
>> +#define VIDTCON1 (0x20014)
>> +#define VIDTCON3 (0x2001C)
>> +#else
>> #define VIDTCON0 (0x10)
>> #define VIDTCON1 (0x14)
>> #define VIDTCON2 (0x18)
>> +#define VIDTCON3 (0x1C)
>> +#endif
>>
>> /* Window position controls */
>>
>> @@ -43,9 +50,12 @@
>> #define VIDOSD_BASE (0x40)
>>
>> #define VIDINTCON0 (0x130)
>> +#define VIDINTCON1 (0x134)
>>
>> /* WINCONx */
>>
>> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> #define WINCONx_CSCWIDTH_SHIFT (26)
>> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb.h
>> index 9a78012..6d2ee16 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> @@ -32,12 +32,28 @@
>>
>> #define VIDCON0 (0x00)
>> #define VIDCON0_INTERLACE (1 << 29)
>> +
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> +#endif
>> +
>> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> #define VIDCON0_VIDOUT_SHIFT (26)
>> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>>
>> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> #define VIDCON0_L1_DATA_SHIFT (23)
>> @@ -81,7 +97,13 @@
>> #define VIDCON0_ENVID (1 << 1)
>> #define VIDCON0_ENVID_F (1 << 0)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDCON1 (0x20004)
>> +#else
>> #define VIDCON1 (0x04)
>> +#endif
>> +
>> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> #define VIDCON1_LINECNT_SHIFT (16)
>> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> @@ -111,6 +133,14 @@
>> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>>
>> #define VIDCON2_ORGYCbCr (1 << 8)
>> #define VIDCON2_YUVORDCrCb (1 << 7)
>> @@ -165,8 +195,15 @@
>> #define VIDTCON1_HSPW_SHIFT (0)
>> #define VIDTCON1_HSPW_LIMIT (0xff)
>> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON2 (0x20018)
>> +#else
>> #define VIDTCON2 (0x18)
>> +#endif
>> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> #define VIDTCON2_LINEVAL_SHIFT (11)
>> @@ -186,6 +223,9 @@
>> #define WINCONx_BYTSWP (1 << 17)
>> #define WINCONx_HAWSWP (1 << 16)
>> #define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> +#define WINCONx_INRGB_RGB (0 << 13)
>> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> #define WINCONx_BURSTLEN_SHIFT (9)
>> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> @@ -205,6 +245,7 @@
>> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>>
>> #define WINCON1_BLD_PIX (1 << 6)
>> +#define WINCON1_BLD_PLANE (0 << 6)
>>
>> #define WINCON1_ALPHA_SEL (1 << 1)
>> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> @@ -395,9 +436,19 @@
>> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>>
>> +/* Clock gate mode control */
>> +#define REG_CLKGATE_MODE (0x1b0)
>> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> +
>> /* Blending equation control */
>> #define BLENDCON (0x260)
>> #define BLENDCON_NEW_MASK (1 << 0)
>> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>>
>> +/* Window alpha control */
>> +#define VIDW0ALPHA0 (0x200)
>> +#define VIDW0ALPHA1 (0x204)
>> +#define DPCLKCON (0x27c)
>> +#define DPCLKCON_ENABLE (1 << 1)
>> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> index 0217f74..f81bf55 100644
>> --- a/drivers/video/Kconfig
>> +++ b/drivers/video/Kconfig
>> @@ -2053,6 +2053,12 @@ config FB_S3C
>>
>> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>>
>> +config FB_EXYNOS_FIMD_V8
>> + bool "register extensions for FIMD version 8"
>> + depends on ARCH_EXYNOS5
>> + ---help---
>> + This uses register extensions for FIMD version 8
>> +
>> config FB_S3C_DEBUG_REGWRITE
>> bool "Debug register writes"
>> depends on FB_S3C
>
> Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
> IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
> They are not a part of core platform code. I thought that there have been some patches
> cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
> mainline.
>
The defines I had given in these headers are specific to exynos5
platform and are using by both drm-fimd and
s3c-fb. I'm not understanding the need to move these defines from
arch/arm to drivers/video. Can you please tell me why we have to do
that.
Best Wishes,
Leela Krishna Amudala.
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-19 12:43 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-19 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Hello Marek,
On Wed, Jul 18, 2012 at 12:21 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>
>> This patch updates the register address offsets and adds SFR definitions
>> for writeback for Samsung's V8 display controller.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
>> drivers/video/Kconfig | 6 +++
>> 3 files changed, 67 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb-v4.h
>> index 4c3647f..1639c17 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> @@ -30,9 +30,16 @@
>> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>>
>> /* Video timing controls */
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON0 (0x20010)
>> +#define VIDTCON1 (0x20014)
>> +#define VIDTCON3 (0x2001C)
>> +#else
>> #define VIDTCON0 (0x10)
>> #define VIDTCON1 (0x14)
>> #define VIDTCON2 (0x18)
>> +#define VIDTCON3 (0x1C)
>> +#endif
>>
>> /* Window position controls */
>>
>> @@ -43,9 +50,12 @@
>> #define VIDOSD_BASE (0x40)
>>
>> #define VIDINTCON0 (0x130)
>> +#define VIDINTCON1 (0x134)
>>
>> /* WINCONx */
>>
>> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> #define WINCONx_CSCWIDTH_SHIFT (26)
>> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
>> samsung/include/plat/regs-fb.h
>> index 9a78012..6d2ee16 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> @@ -32,12 +32,28 @@
>>
>> #define VIDCON0 (0x00)
>> #define VIDCON0_INTERLACE (1 << 29)
>> +
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> +#endif
>> +
>> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> #define VIDCON0_VIDOUT_SHIFT (26)
>> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>>
>> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> #define VIDCON0_L1_DATA_SHIFT (23)
>> @@ -81,7 +97,13 @@
>> #define VIDCON0_ENVID (1 << 1)
>> #define VIDCON0_ENVID_F (1 << 0)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDCON1 (0x20004)
>> +#else
>> #define VIDCON1 (0x04)
>> +#endif
>> +
>> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> #define VIDCON1_LINECNT_SHIFT (16)
>> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> @@ -111,6 +133,14 @@
>> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>>
>> #define VIDCON2_ORGYCbCr (1 << 8)
>> #define VIDCON2_YUVORDCrCb (1 << 7)
>> @@ -165,8 +195,15 @@
>> #define VIDTCON1_HSPW_SHIFT (0)
>> #define VIDTCON1_HSPW_LIMIT (0xff)
>> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON2 (0x20018)
>> +#else
>> #define VIDTCON2 (0x18)
>> +#endif
>> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> #define VIDTCON2_LINEVAL_SHIFT (11)
>> @@ -186,6 +223,9 @@
>> #define WINCONx_BYTSWP (1 << 17)
>> #define WINCONx_HAWSWP (1 << 16)
>> #define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> +#define WINCONx_INRGB_RGB (0 << 13)
>> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> #define WINCONx_BURSTLEN_SHIFT (9)
>> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> @@ -205,6 +245,7 @@
>> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>>
>> #define WINCON1_BLD_PIX (1 << 6)
>> +#define WINCON1_BLD_PLANE (0 << 6)
>>
>> #define WINCON1_ALPHA_SEL (1 << 1)
>> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> @@ -395,9 +436,19 @@
>> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>>
>> +/* Clock gate mode control */
>> +#define REG_CLKGATE_MODE (0x1b0)
>> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> +
>> /* Blending equation control */
>> #define BLENDCON (0x260)
>> #define BLENDCON_NEW_MASK (1 << 0)
>> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>>
>> +/* Window alpha control */
>> +#define VIDW0ALPHA0 (0x200)
>> +#define VIDW0ALPHA1 (0x204)
>> +#define DPCLKCON (0x27c)
>> +#define DPCLKCON_ENABLE (1 << 1)
>> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> index 0217f74..f81bf55 100644
>> --- a/drivers/video/Kconfig
>> +++ b/drivers/video/Kconfig
>> @@ -2053,6 +2053,12 @@ config FB_S3C
>>
>> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>>
>> +config FB_EXYNOS_FIMD_V8
>> + bool "register extensions for FIMD version 8"
>> + depends on ARCH_EXYNOS5
>> + ---help---
>> + This uses register extensions for FIMD version 8
>> +
>> config FB_S3C_DEBUG_REGWRITE
>> bool "Debug register writes"
>> depends on FB_S3C
>
> Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
> IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
> They are not a part of core platform code. I thought that there have been some patches
> cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
> mainline.
>
The defines I had given in these headers are specific to exynos5
platform and are using by both drm-fimd and
s3c-fb. I'm not understanding the need to move these defines from
arch/arm to drivers/video. Can you please tell me why we have to do
that.
Best Wishes,
Leela Krishna Amudala.
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-19 12:43 ` Leela Krishna Amudala
@ 2012-07-20 6:45 ` Marek Szyprowski
-1 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-20 6:45 UTC (permalink / raw)
To: 'Leela Krishna Amudala'
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
Hello,
On Thursday, July 19, 2012 2:44 PM Leela Krishna Amudala
> Hello Marek,
>
> On Wed, Jul 18, 2012 at 12:21 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> >
> >> This patch updates the register address offsets and adds SFR definitions
> >> for writeback for Samsung's V8 display controller.
> >>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
> >> drivers/video/Kconfig | 6 +++
> >> 3 files changed, 67 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
> >> samsung/include/plat/regs-fb-v4.h
> >> index 4c3647f..1639c17 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> @@ -30,9 +30,16 @@
> >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> >>
> >> /* Video timing controls */
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON0 (0x20010)
> >> +#define VIDTCON1 (0x20014)
> >> +#define VIDTCON3 (0x2001C)
> >> +#else
> >> #define VIDTCON0 (0x10)
> >> #define VIDTCON1 (0x14)
> >> #define VIDTCON2 (0x18)
> >> +#define VIDTCON3 (0x1C)
> >> +#endif
> >>
> >> /* Window position controls */
> >>
> >> @@ -43,9 +50,12 @@
> >> #define VIDOSD_BASE (0x40)
> >>
> >> #define VIDINTCON0 (0x130)
> >> +#define VIDINTCON1 (0x134)
> >>
> >> /* WINCONx */
> >>
> >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> #define WINCONx_CSCWIDTH_SHIFT (26)
> >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
> >> samsung/include/plat/regs-fb.h
> >> index 9a78012..6d2ee16 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> @@ -32,12 +32,28 @@
> >>
> >> #define VIDCON0 (0x00)
> >> #define VIDCON0_INTERLACE (1 << 29)
> >> +
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> >> +#endif
> >> +
> >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> #define VIDCON0_VIDOUT_SHIFT (26)
> >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> >>
> >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> #define VIDCON0_L1_DATA_SHIFT (23)
> >> @@ -81,7 +97,13 @@
> >> #define VIDCON0_ENVID (1 << 1)
> >> #define VIDCON0_ENVID_F (1 << 0)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDCON1 (0x20004)
> >> +#else
> >> #define VIDCON1 (0x04)
> >> +#endif
> >> +
> >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> #define VIDCON1_LINECNT_SHIFT (16)
> >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> >> @@ -111,6 +133,14 @@
> >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> >> +
> >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >>
> >> #define VIDCON2_ORGYCbCr (1 << 8)
> >> #define VIDCON2_YUVORDCrCb (1 << 7)
> >> @@ -165,8 +195,15 @@
> >> #define VIDTCON1_HSPW_SHIFT (0)
> >> #define VIDTCON1_HSPW_LIMIT (0xff)
> >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON2 (0x20018)
> >> +#else
> >> #define VIDTCON2 (0x18)
> >> +#endif
> >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> >> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> >> #define VIDTCON2_LINEVAL_SHIFT (11)
> >> @@ -186,6 +223,9 @@
> >> #define WINCONx_BYTSWP (1 << 17)
> >> #define WINCONx_HAWSWP (1 << 16)
> >> #define WINCONx_WSWP (1 << 15)
> >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> >> +#define WINCONx_INRGB_RGB (0 << 13)
> >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> #define WINCONx_BURSTLEN_SHIFT (9)
> >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >> @@ -205,6 +245,7 @@
> >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >>
> >> #define WINCON1_BLD_PIX (1 << 6)
> >> +#define WINCON1_BLD_PLANE (0 << 6)
> >>
> >> #define WINCON1_ALPHA_SEL (1 << 1)
> >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> >> @@ -395,9 +436,19 @@
> >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >>
> >> +/* Clock gate mode control */
> >> +#define REG_CLKGATE_MODE (0x1b0)
> >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> >> +
> >> /* Blending equation control */
> >> #define BLENDCON (0x260)
> >> #define BLENDCON_NEW_MASK (1 << 0)
> >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >>
> >> +/* Window alpha control */
> >> +#define VIDW0ALPHA0 (0x200)
> >> +#define VIDW0ALPHA1 (0x204)
> >> +#define DPCLKCON (0x27c)
> >> +#define DPCLKCON_ENABLE (1 << 1)
> >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> >> index 0217f74..f81bf55 100644
> >> --- a/drivers/video/Kconfig
> >> +++ b/drivers/video/Kconfig
> >> @@ -2053,6 +2053,12 @@ config FB_S3C
> >>
> >> Currently the support is only for the S3C6400 and S3C6410 SoCs.
> >>
> >> +config FB_EXYNOS_FIMD_V8
> >> + bool "register extensions for FIMD version 8"
> >> + depends on ARCH_EXYNOS5
> >> + ---help---
> >> + This uses register extensions for FIMD version 8
> >> +
> >> config FB_S3C_DEBUG_REGWRITE
> >> bool "Debug register writes"
> >> depends on FB_S3C
> >
> > Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
> > IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
> > They are not a part of core platform code. I thought that there have been some patches
> > cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
> > mainline.
> >
>
> The defines I had given in these headers are specific to exynos5
> platform and are using by both drm-fimd and
> s3c-fb. I'm not understanding the need to move these defines from
> arch/arm to drivers/video. Can you please tell me why we have to do
> that.
These defines are not the part of the Samsung platform core, they are used only by the
device drivers. There is no point bloating arch/arm directory with the defines used
only by the device drivers. If they are shared between 2 drivers then /include/video
might be a good place for them.
I'm not really sure if we really need to add another Kconfig for adding support for
V8 of fimd device. There is already runtime support for different variants of the
fimd hw block varing from s3c-2443 to exynos4 based on the platform device name (see
s3c_fb_driver_ids in drivers/video/s3c-fb.c). Another variant for exynos5 looks like
a cleaner approach.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 6:45 ` Marek Szyprowski
0 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-20 6:45 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Thursday, July 19, 2012 2:44 PM Leela Krishna Amudala
> Hello Marek,
>
> On Wed, Jul 18, 2012 at 12:21 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> >
> >> This patch updates the register address offsets and adds SFR definitions
> >> for writeback for Samsung's V8 display controller.
> >>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++
> >> drivers/video/Kconfig | 6 +++
> >> 3 files changed, 67 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-
> >> samsung/include/plat/regs-fb-v4.h
> >> index 4c3647f..1639c17 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> @@ -30,9 +30,16 @@
> >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> >>
> >> /* Video timing controls */
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON0 (0x20010)
> >> +#define VIDTCON1 (0x20014)
> >> +#define VIDTCON3 (0x2001C)
> >> +#else
> >> #define VIDTCON0 (0x10)
> >> #define VIDTCON1 (0x14)
> >> #define VIDTCON2 (0x18)
> >> +#define VIDTCON3 (0x1C)
> >> +#endif
> >>
> >> /* Window position controls */
> >>
> >> @@ -43,9 +50,12 @@
> >> #define VIDOSD_BASE (0x40)
> >>
> >> #define VIDINTCON0 (0x130)
> >> +#define VIDINTCON1 (0x134)
> >>
> >> /* WINCONx */
> >>
> >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> #define WINCONx_CSCWIDTH_SHIFT (26)
> >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-
> >> samsung/include/plat/regs-fb.h
> >> index 9a78012..6d2ee16 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> @@ -32,12 +32,28 @@
> >>
> >> #define VIDCON0 (0x00)
> >> #define VIDCON0_INTERLACE (1 << 29)
> >> +
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> >> +#endif
> >> +
> >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> #define VIDCON0_VIDOUT_SHIFT (26)
> >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> >>
> >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> #define VIDCON0_L1_DATA_SHIFT (23)
> >> @@ -81,7 +97,13 @@
> >> #define VIDCON0_ENVID (1 << 1)
> >> #define VIDCON0_ENVID_F (1 << 0)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDCON1 (0x20004)
> >> +#else
> >> #define VIDCON1 (0x04)
> >> +#endif
> >> +
> >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> #define VIDCON1_LINECNT_SHIFT (16)
> >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> >> @@ -111,6 +133,14 @@
> >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> >> +
> >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >>
> >> #define VIDCON2_ORGYCbCr (1 << 8)
> >> #define VIDCON2_YUVORDCrCb (1 << 7)
> >> @@ -165,8 +195,15 @@
> >> #define VIDTCON1_HSPW_SHIFT (0)
> >> #define VIDTCON1_HSPW_LIMIT (0xff)
> >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON2 (0x20018)
> >> +#else
> >> #define VIDTCON2 (0x18)
> >> +#endif
> >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> >> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> >> #define VIDTCON2_LINEVAL_SHIFT (11)
> >> @@ -186,6 +223,9 @@
> >> #define WINCONx_BYTSWP (1 << 17)
> >> #define WINCONx_HAWSWP (1 << 16)
> >> #define WINCONx_WSWP (1 << 15)
> >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> >> +#define WINCONx_INRGB_RGB (0 << 13)
> >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> #define WINCONx_BURSTLEN_SHIFT (9)
> >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >> @@ -205,6 +245,7 @@
> >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >>
> >> #define WINCON1_BLD_PIX (1 << 6)
> >> +#define WINCON1_BLD_PLANE (0 << 6)
> >>
> >> #define WINCON1_ALPHA_SEL (1 << 1)
> >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> >> @@ -395,9 +436,19 @@
> >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >>
> >> +/* Clock gate mode control */
> >> +#define REG_CLKGATE_MODE (0x1b0)
> >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> >> +
> >> /* Blending equation control */
> >> #define BLENDCON (0x260)
> >> #define BLENDCON_NEW_MASK (1 << 0)
> >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >>
> >> +/* Window alpha control */
> >> +#define VIDW0ALPHA0 (0x200)
> >> +#define VIDW0ALPHA1 (0x204)
> >> +#define DPCLKCON (0x27c)
> >> +#define DPCLKCON_ENABLE (1 << 1)
> >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> >> index 0217f74..f81bf55 100644
> >> --- a/drivers/video/Kconfig
> >> +++ b/drivers/video/Kconfig
> >> @@ -2053,6 +2053,12 @@ config FB_S3C
> >>
> >> Currently the support is only for the S3C6400 and S3C6410 SoCs.
> >>
> >> +config FB_EXYNOS_FIMD_V8
> >> + bool "register extensions for FIMD version 8"
> >> + depends on ARCH_EXYNOS5
> >> + ---help---
> >> + This uses register extensions for FIMD version 8
> >> +
> >> config FB_S3C_DEBUG_REGWRITE
> >> bool "Debug register writes"
> >> depends on FB_S3C
> >
> > Do we really need these defines in arch/arm/plat-samsung/include/plat/regs-fb* ?
> > IMHO they should be moved from arch/arm to drivers/video to live together with the driver.
> > They are not a part of core platform code. I thought that there have been some patches
> > cleaning up regs-fb mess a long time ago, but it looks they didn't get their way to
> > mainline.
> >
>
> The defines I had given in these headers are specific to exynos5
> platform and are using by both drm-fimd and
> s3c-fb. I'm not understanding the need to move these defines from
> arch/arm to drivers/video. Can you please tell me why we have to do
> that.
These defines are not the part of the Samsung platform core, they are used only by the
device drivers. There is no point bloating arch/arm directory with the defines used
only by the device drivers. If they are shared between 2 drivers then /include/video
might be a good place for them.
I'm not really sure if we really need to add another Kconfig for adding support for
V8 of fimd device. There is already runtime support for different variants of the
fimd hw block varing from s3c-2443 to exynos4 based on the platform device name (see
s3c_fb_driver_ids in drivers/video/s3c-fb.c). Another variant for exynos5 looks like
a cleaner approach.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 11:05 ` Tomasz Figa
-1 siblings, 0 replies; 84+ messages in thread
From: Tomasz Figa @ 2012-07-18 11:05 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: devicetree-discuss, linux-arm-kernel, linux-samsung-soc,
grant.likely, olofj, thomas.ab, kgene.kim, joshi, jg1.han
Hi,
On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> This patch updates the register address offsets and adds SFR definitions
> for writeback for Samsung's V8 display controller.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> +++++++++++++++++++++++ drivers/video/Kconfig
> | 6 +++
> 3 files changed, 67 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 4c3647f..1639c17
> 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> @@ -30,9 +30,16 @@
> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>
> /* Video timing controls */
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON0 (0x20010)
> +#define VIDTCON1 (0x20014)
> +#define VIDTCON3 (0x2001C)
> +#else
> #define VIDTCON0 (0x10)
> #define VIDTCON1 (0x14)
> #define VIDTCON2 (0x18)
> +#define VIDTCON3 (0x1C)
> +#endif
Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
kernels, aren't we (i.e support of both V8 and earlier FIMD in one kernel)?
>
> /* Window position controls */
>
> @@ -43,9 +50,12 @@
> #define VIDOSD_BASE (0x40)
>
> #define VIDINTCON0 (0x130)
> +#define VIDINTCON1 (0x134)
>
> /* WINCONx */
>
> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> #define WINCONx_CSCWIDTH_SHIFT (26)
> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
> 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> @@ -32,12 +32,28 @@
>
> #define VIDCON0 (0x00)
> #define VIDCON0_INTERLACE (1 << 29)
> +
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> +#endif
> +
> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> #define VIDCON0_VIDOUT_SHIFT (26)
> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>
> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> #define VIDCON0_L1_DATA_SHIFT (23)
> @@ -81,7 +97,13 @@
> #define VIDCON0_ENVID (1 << 1)
> #define VIDCON0_ENVID_F (1 << 0)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDCON1 (0x20004)
> +#else
> #define VIDCON1 (0x04)
> +#endif
Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
several lines above?
> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> #define VIDCON1_LINECNT_SHIFT (16)
> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> @@ -111,6 +133,14 @@
> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> +
> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>
> #define VIDCON2_ORGYCbCr (1 << 8)
> #define VIDCON2_YUVORDCrCb (1 << 7)
> @@ -165,8 +195,15 @@
> #define VIDTCON1_HSPW_SHIFT (0)
> #define VIDTCON1_HSPW_LIMIT (0xff)
> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON2 (0x20018)
> +#else
> #define VIDTCON2 (0x18)
> +#endif
Same as in my first comment.
> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> #define VIDTCON2_LINEVAL_SHIFT (11)
> @@ -186,6 +223,9 @@
> #define WINCONx_BYTSWP (1 << 17)
> #define WINCONx_HAWSWP (1 << 16)
> #define WINCONx_WSWP (1 << 15)
> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> +#define WINCONx_INRGB_RGB (0 << 13)
> +#define WINCONx_INRGB_YCBCR (1 << 13)
> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> #define WINCONx_BURSTLEN_SHIFT (9)
> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> @@ -205,6 +245,7 @@
> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>
> #define WINCON1_BLD_PIX (1 << 6)
> +#define WINCON1_BLD_PLANE (0 << 6)
>
> #define WINCON1_ALPHA_SEL (1 << 1)
> #define WINCON1_BPPMODE_MASK (0xf << 2)
> @@ -395,9 +436,19 @@
> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>
> +/* Clock gate mode control */
> +#define REG_CLKGATE_MODE (0x1b0)
> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> +
> /* Blending equation control */
> #define BLENDCON (0x260)
> #define BLENDCON_NEW_MASK (1 << 0)
> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>
> +/* Window alpha control */
> +#define VIDW0ALPHA0 (0x200)
> +#define VIDW0ALPHA1 (0x204)
> +#define DPCLKCON (0x27c)
> +#define DPCLKCON_ENABLE (1 << 1)
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 0217f74..f81bf55 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -2053,6 +2053,12 @@ config FB_S3C
>
> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>
> +config FB_EXYNOS_FIMD_V8
> + bool "register extensions for FIMD version 8"
> + depends on ARCH_EXYNOS5
> + ---help---
> + This uses register extensions for FIMD version 8
> +
> config FB_S3C_DEBUG_REGWRITE
> bool "Debug register writes"
> depends on FB_S3C
Best regards,
Tomasz Figa
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-18 11:05 ` Tomasz Figa
0 siblings, 0 replies; 84+ messages in thread
From: Tomasz Figa @ 2012-07-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> This patch updates the register address offsets and adds SFR definitions
> for writeback for Samsung's V8 display controller.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> +++++++++++++++++++++++ drivers/video/Kconfig
> | 6 +++
> 3 files changed, 67 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 4c3647f..1639c17
> 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> @@ -30,9 +30,16 @@
> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>
> /* Video timing controls */
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON0 (0x20010)
> +#define VIDTCON1 (0x20014)
> +#define VIDTCON3 (0x2001C)
> +#else
> #define VIDTCON0 (0x10)
> #define VIDTCON1 (0x14)
> #define VIDTCON2 (0x18)
> +#define VIDTCON3 (0x1C)
> +#endif
Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
kernels, aren't we (i.e support of both V8 and earlier FIMD in one kernel)?
>
> /* Window position controls */
>
> @@ -43,9 +50,12 @@
> #define VIDOSD_BASE (0x40)
>
> #define VIDINTCON0 (0x130)
> +#define VIDINTCON1 (0x134)
>
> /* WINCONx */
>
> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> #define WINCONx_CSCWIDTH_SHIFT (26)
> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
> 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> @@ -32,12 +32,28 @@
>
> #define VIDCON0 (0x00)
> #define VIDCON0_INTERLACE (1 << 29)
> +
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> +#endif
> +
> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> #define VIDCON0_VIDOUT_SHIFT (26)
> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>
> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> #define VIDCON0_L1_DATA_SHIFT (23)
> @@ -81,7 +97,13 @@
> #define VIDCON0_ENVID (1 << 1)
> #define VIDCON0_ENVID_F (1 << 0)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDOUT_CON (0x20000)
> +#define VIDCON1 (0x20004)
> +#else
> #define VIDCON1 (0x04)
> +#endif
Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
several lines above?
> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> #define VIDCON1_LINECNT_SHIFT (16)
> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> @@ -111,6 +133,14 @@
> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> +
> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>
> #define VIDCON2_ORGYCbCr (1 << 8)
> #define VIDCON2_YUVORDCrCb (1 << 7)
> @@ -165,8 +195,15 @@
> #define VIDTCON1_HSPW_SHIFT (0)
> #define VIDTCON1_HSPW_LIMIT (0xff)
> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>
> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> +#define VIDTCON2 (0x20018)
> +#else
> #define VIDTCON2 (0x18)
> +#endif
Same as in my first comment.
> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> #define VIDTCON2_LINEVAL_SHIFT (11)
> @@ -186,6 +223,9 @@
> #define WINCONx_BYTSWP (1 << 17)
> #define WINCONx_HAWSWP (1 << 16)
> #define WINCONx_WSWP (1 << 15)
> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> +#define WINCONx_INRGB_RGB (0 << 13)
> +#define WINCONx_INRGB_YCBCR (1 << 13)
> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> #define WINCONx_BURSTLEN_SHIFT (9)
> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> @@ -205,6 +245,7 @@
> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>
> #define WINCON1_BLD_PIX (1 << 6)
> +#define WINCON1_BLD_PLANE (0 << 6)
>
> #define WINCON1_ALPHA_SEL (1 << 1)
> #define WINCON1_BPPMODE_MASK (0xf << 2)
> @@ -395,9 +436,19 @@
> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>
> +/* Clock gate mode control */
> +#define REG_CLKGATE_MODE (0x1b0)
> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> +
> /* Blending equation control */
> #define BLENDCON (0x260)
> #define BLENDCON_NEW_MASK (1 << 0)
> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>
> +/* Window alpha control */
> +#define VIDW0ALPHA0 (0x200)
> +#define VIDW0ALPHA1 (0x204)
> +#define DPCLKCON (0x27c)
> +#define DPCLKCON_ENABLE (1 << 1)
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 0217f74..f81bf55 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -2053,6 +2053,12 @@ config FB_S3C
>
> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>
> +config FB_EXYNOS_FIMD_V8
> + bool "register extensions for FIMD version 8"
> + depends on ARCH_EXYNOS5
> + ---help---
> + This uses register extensions for FIMD version 8
> +
> config FB_S3C_DEBUG_REGWRITE
> bool "Debug register writes"
> depends on FB_S3C
Best regards,
Tomasz Figa
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-18 11:05 ` Tomasz Figa
@ 2012-07-19 13:00 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-19 13:00 UTC (permalink / raw)
To: Tomasz Figa
Cc: devicetree-discuss, linux-arm-kernel, linux-samsung-soc,
grant.likely, olofj, thomas.ab, kgene.kim, joshi, jg1.han
Hi Tomasz,
On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi,
>
> On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
>> This patch updates the register address offsets and adds SFR definitions
>> for writeback for Samsung's V8 display controller.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
>> +++++++++++++++++++++++ drivers/video/Kconfig
>> | 6 +++
>> 3 files changed, 67 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 4c3647f..1639c17
>> 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> @@ -30,9 +30,16 @@
>> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>>
>> /* Video timing controls */
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON0 (0x20010)
>> +#define VIDTCON1 (0x20014)
>> +#define VIDTCON3 (0x2001C)
>> +#else
>> #define VIDTCON0 (0x10)
>> #define VIDTCON1 (0x14)
>> #define VIDTCON2 (0x18)
>> +#define VIDTCON3 (0x1C)
>> +#endif
>
> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> kernels, aren't we (i.e support of both V8 and earlier FIMD in one kernel)?
>
Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
As address offsets for certain registers has changed in FIMD_V8, we
introduced these defines.
So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
and deselect for other SoCs.
>>
>> /* Window position controls */
>>
>> @@ -43,9 +50,12 @@
>> #define VIDOSD_BASE (0x40)
>>
>> #define VIDINTCON0 (0x130)
>> +#define VIDINTCON1 (0x134)
>>
>> /* WINCONx */
>>
>> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> #define WINCONx_CSCWIDTH_SHIFT (26)
>> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
>> 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> @@ -32,12 +32,28 @@
>>
>> #define VIDCON0 (0x00)
>> #define VIDCON0_INTERLACE (1 << 29)
>> +
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> +#endif
>> +
>> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> #define VIDCON0_VIDOUT_SHIFT (26)
>> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>>
>> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> #define VIDCON0_L1_DATA_SHIFT (23)
>> @@ -81,7 +97,13 @@
>> #define VIDCON0_ENVID (1 << 1)
>> #define VIDCON0_ENVID_F (1 << 0)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDCON1 (0x20004)
>> +#else
>> #define VIDCON1 (0x04)
>> +#endif
>
> Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
> several lines above?
>
Will be corrected in the next version patch set.
Best Wishes,
Leela Krishna Amudala.
>> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> #define VIDCON1_LINECNT_SHIFT (16)
>> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> @@ -111,6 +133,14 @@
>> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>>
>> #define VIDCON2_ORGYCbCr (1 << 8)
>> #define VIDCON2_YUVORDCrCb (1 << 7)
>> @@ -165,8 +195,15 @@
>> #define VIDTCON1_HSPW_SHIFT (0)
>> #define VIDTCON1_HSPW_LIMIT (0xff)
>> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON2 (0x20018)
>> +#else
>> #define VIDTCON2 (0x18)
>> +#endif
>
> Same as in my first comment.
>
>> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> #define VIDTCON2_LINEVAL_SHIFT (11)
>> @@ -186,6 +223,9 @@
>> #define WINCONx_BYTSWP (1 << 17)
>> #define WINCONx_HAWSWP (1 << 16)
>> #define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> +#define WINCONx_INRGB_RGB (0 << 13)
>> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> #define WINCONx_BURSTLEN_SHIFT (9)
>> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> @@ -205,6 +245,7 @@
>> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>>
>> #define WINCON1_BLD_PIX (1 << 6)
>> +#define WINCON1_BLD_PLANE (0 << 6)
>>
>> #define WINCON1_ALPHA_SEL (1 << 1)
>> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> @@ -395,9 +436,19 @@
>> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>>
>> +/* Clock gate mode control */
>> +#define REG_CLKGATE_MODE (0x1b0)
>> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> +
>> /* Blending equation control */
>> #define BLENDCON (0x260)
>> #define BLENDCON_NEW_MASK (1 << 0)
>> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>>
>> +/* Window alpha control */
>> +#define VIDW0ALPHA0 (0x200)
>> +#define VIDW0ALPHA1 (0x204)
>> +#define DPCLKCON (0x27c)
>> +#define DPCLKCON_ENABLE (1 << 1)
>> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> index 0217f74..f81bf55 100644
>> --- a/drivers/video/Kconfig
>> +++ b/drivers/video/Kconfig
>> @@ -2053,6 +2053,12 @@ config FB_S3C
>>
>> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>>
>> +config FB_EXYNOS_FIMD_V8
>> + bool "register extensions for FIMD version 8"
>> + depends on ARCH_EXYNOS5
>> + ---help---
>> + This uses register extensions for FIMD version 8
>> +
>> config FB_S3C_DEBUG_REGWRITE
>> bool "Debug register writes"
>> depends on FB_S3C
>
> Best regards,
> Tomasz Figa
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-19 13:00 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-19 13:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi,
>
> On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
>> This patch updates the register address offsets and adds SFR definitions
>> for writeback for Samsung's V8 display controller.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
>> +++++++++++++++++++++++ drivers/video/Kconfig
>> | 6 +++
>> 3 files changed, 67 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 4c3647f..1639c17
>> 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> @@ -30,9 +30,16 @@
>> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>>
>> /* Video timing controls */
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON0 (0x20010)
>> +#define VIDTCON1 (0x20014)
>> +#define VIDTCON3 (0x2001C)
>> +#else
>> #define VIDTCON0 (0x10)
>> #define VIDTCON1 (0x14)
>> #define VIDTCON2 (0x18)
>> +#define VIDTCON3 (0x1C)
>> +#endif
>
> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> kernels, aren't we (i.e support of both V8 and earlier FIMD in one kernel)?
>
Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
As address offsets for certain registers has changed in FIMD_V8, we
introduced these defines.
So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
and deselect for other SoCs.
>>
>> /* Window position controls */
>>
>> @@ -43,9 +50,12 @@
>> #define VIDOSD_BASE (0x40)
>>
>> #define VIDINTCON0 (0x130)
>> +#define VIDINTCON1 (0x134)
>>
>> /* WINCONx */
>>
>> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> #define WINCONx_CSCWIDTH_SHIFT (26)
>> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
>> 100644
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> @@ -32,12 +32,28 @@
>>
>> #define VIDCON0 (0x00)
>> #define VIDCON0_INTERLACE (1 << 29)
>> +
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> +#endif
>> +
>> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> #define VIDCON0_VIDOUT_SHIFT (26)
>> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>>
>> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> #define VIDCON0_L1_DATA_SHIFT (23)
>> @@ -81,7 +97,13 @@
>> #define VIDCON0_ENVID (1 << 1)
>> #define VIDCON0_ENVID_F (1 << 0)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDOUT_CON (0x20000)
>> +#define VIDCON1 (0x20004)
>> +#else
>> #define VIDCON1 (0x04)
>> +#endif
>
> Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
> several lines above?
>
Will be corrected in the next version patch set.
Best Wishes,
Leela Krishna Amudala.
>> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> #define VIDCON1_LINECNT_SHIFT (16)
>> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> @@ -111,6 +133,14 @@
>> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>>
>> #define VIDCON2_ORGYCbCr (1 << 8)
>> #define VIDCON2_YUVORDCrCb (1 << 7)
>> @@ -165,8 +195,15 @@
>> #define VIDTCON1_HSPW_SHIFT (0)
>> #define VIDTCON1_HSPW_LIMIT (0xff)
>> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>>
>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> +#define VIDTCON2 (0x20018)
>> +#else
>> #define VIDTCON2 (0x18)
>> +#endif
>
> Same as in my first comment.
>
>> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> #define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> #define VIDTCON2_LINEVAL_SHIFT (11)
>> @@ -186,6 +223,9 @@
>> #define WINCONx_BYTSWP (1 << 17)
>> #define WINCONx_HAWSWP (1 << 16)
>> #define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> +#define WINCONx_INRGB_RGB (0 << 13)
>> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> #define WINCONx_BURSTLEN_SHIFT (9)
>> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> @@ -205,6 +245,7 @@
>> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>>
>> #define WINCON1_BLD_PIX (1 << 6)
>> +#define WINCON1_BLD_PLANE (0 << 6)
>>
>> #define WINCON1_ALPHA_SEL (1 << 1)
>> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> @@ -395,9 +436,19 @@
>> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>>
>> +/* Clock gate mode control */
>> +#define REG_CLKGATE_MODE (0x1b0)
>> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> +
>> /* Blending equation control */
>> #define BLENDCON (0x260)
>> #define BLENDCON_NEW_MASK (1 << 0)
>> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>>
>> +/* Window alpha control */
>> +#define VIDW0ALPHA0 (0x200)
>> +#define VIDW0ALPHA1 (0x204)
>> +#define DPCLKCON (0x27c)
>> +#define DPCLKCON_ENABLE (1 << 1)
>> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> index 0217f74..f81bf55 100644
>> --- a/drivers/video/Kconfig
>> +++ b/drivers/video/Kconfig
>> @@ -2053,6 +2053,12 @@ config FB_S3C
>>
>> Currently the support is only for the S3C6400 and S3C6410 SoCs.
>>
>> +config FB_EXYNOS_FIMD_V8
>> + bool "register extensions for FIMD version 8"
>> + depends on ARCH_EXYNOS5
>> + ---help---
>> + This uses register extensions for FIMD version 8
>> +
>> config FB_S3C_DEBUG_REGWRITE
>> bool "Debug register writes"
>> depends on FB_S3C
>
> Best regards,
> Tomasz Figa
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-19 13:00 ` Leela Krishna Amudala
@ 2012-07-19 13:35 ` Tomasz Figa
-1 siblings, 0 replies; 84+ messages in thread
From: Tomasz Figa @ 2012-07-19 13:35 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: devicetree-discuss, linux-arm-kernel, linux-samsung-soc,
grant.likely, olofj, thomas.ab, kgene.kim, joshi, jg1.han
Hi Leela,
On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
> Hi Tomasz,
>
> On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
wrote:
> > Hi,
> >
> > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> >> This patch updates the register address offsets and adds SFR
> >> definitions
> >> for writeback for Samsung's V8 display controller.
> >>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >>
> >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> >>
> >> +++++++++++++++++++++++ drivers/video/Kconfig
> >>
> >> | 6 +++
> >>
> >> 3 files changed, 67 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
> >> 4c3647f..1639c17
> >> 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> @@ -30,9 +30,16 @@
> >>
> >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> >>
> >> /* Video timing controls */
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON0 (0x20010)
> >> +#define VIDTCON1 (0x20014)
> >> +#define VIDTCON3 (0x2001C)
> >> +#else
> >>
> >> #define VIDTCON0 (0x10)
> >> #define VIDTCON1 (0x14)
> >> #define VIDTCON2 (0x18)
> >>
> >> +#define VIDTCON3 (0x1C)
> >> +#endif
> >
> > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> > kernel)?
> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> As address offsets for certain registers has changed in FIMD_V8, we
> introduced these defines.
> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
> and deselect for other SoCs.
Yes, I'm aware of different FIMD versions in different SoCs. My point is
that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
support other SoCs than Exynos5, i.e. additional config options should be
incremental - should not break other setups. Ideally there should not be
any new config option for FIMD v8.
The detection of FIMD version and selection of appropriate register offsets
should be done in the driver at runtime, based for example on
platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
and s3c_fb_win_variant structs).
Best regards,
Tomasz Figa
>
> >> /* Window position controls */
> >>
> >> @@ -43,9 +50,12 @@
> >>
> >> #define VIDOSD_BASE (0x40)
> >>
> >> #define VIDINTCON0 (0x130)
> >>
> >> +#define VIDINTCON1 (0x134)
> >>
> >> /* WINCONx */
> >>
> >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> >>
> >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> #define WINCONx_CSCWIDTH_SHIFT (26)
> >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
> >> 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> @@ -32,12 +32,28 @@
> >>
> >> #define VIDCON0 (0x00)
> >> #define VIDCON0_INTERLACE (1 << 29)
> >>
> >> +
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> >> +#endif
> >> +
> >>
> >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> #define VIDCON0_VIDOUT_SHIFT (26)
> >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >>
> >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> >>
> >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> #define VIDCON0_L1_DATA_SHIFT (23)
> >>
> >> @@ -81,7 +97,13 @@
> >>
> >> #define VIDCON0_ENVID (1 << 1)
> >> #define VIDCON0_ENVID_F (1 << 0)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDCON1 (0x20004)
> >> +#else
> >>
> >> #define VIDCON1 (0x04)
> >>
> >> +#endif
> >
> > Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
> > several lines above?
>
> Will be corrected in the next version patch set.
>
> Best Wishes,
> Leela Krishna Amudala.
>
> >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> #define VIDCON1_LINECNT_SHIFT (16)
> >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
> >> 0x7ff)>>
> >> @@ -111,6 +133,14 @@
> >>
> >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >>
> >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> >> +
> >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >>
> >> #define VIDCON2_ORGYCbCr (1 << 8)
> >> #define VIDCON2_YUVORDCrCb (1 << 7)
> >>
> >> @@ -165,8 +195,15 @@
> >>
> >> #define VIDTCON1_HSPW_SHIFT (0)
> >> #define VIDTCON1_HSPW_LIMIT (0xff)
> >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> >>
> >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON2 (0x20018)
> >> +#else
> >>
> >> #define VIDTCON2 (0x18)
> >>
> >> +#endif
> >
> > Same as in my first comment.
> >
> >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800)
> >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
> >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
> >> (11)
> >>
> >> @@ -186,6 +223,9 @@
> >>
> >> #define WINCONx_BYTSWP (1 << 17)
> >> #define WINCONx_HAWSWP (1 << 16)
> >> #define WINCONx_WSWP (1 << 15)
> >>
> >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> >> +#define WINCONx_INRGB_RGB (0 << 13)
> >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> >>
> >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> #define WINCONx_BURSTLEN_SHIFT (9)
> >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >>
> >> @@ -205,6 +245,7 @@
> >>
> >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >>
> >> #define WINCON1_BLD_PIX (1 << 6)
> >>
> >> +#define WINCON1_BLD_PLANE (0 << 6)
> >>
> >> #define WINCON1_ALPHA_SEL (1 << 1)
> >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> >>
> >> @@ -395,9 +436,19 @@
> >>
> >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >>
> >> +/* Clock gate mode control */
> >> +#define REG_CLKGATE_MODE (0x1b0)
> >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> >> +
> >>
> >> /* Blending equation control */
> >> #define BLENDCON (0x260)
> >> #define BLENDCON_NEW_MASK (1 << 0)
> >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >>
> >> +/* Window alpha control */
> >> +#define VIDW0ALPHA0 (0x200)
> >> +#define VIDW0ALPHA1 (0x204)
> >> +#define DPCLKCON (0x27c)
> >> +#define DPCLKCON_ENABLE (1 << 1)
> >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> >> index 0217f74..f81bf55 100644
> >> --- a/drivers/video/Kconfig
> >> +++ b/drivers/video/Kconfig
> >> @@ -2053,6 +2053,12 @@ config FB_S3C
> >>
> >> Currently the support is only for the S3C6400 and S3C6410
> >> SoCs.
> >>
> >> +config FB_EXYNOS_FIMD_V8
> >> + bool "register extensions for FIMD version 8"
> >> + depends on ARCH_EXYNOS5
> >> + ---help---
> >> + This uses register extensions for FIMD version 8
> >> +
> >>
> >> config FB_S3C_DEBUG_REGWRITE
> >>
> >> bool "Debug register writes"
> >> depends on FB_S3C
> >
> > Best regards,
> > Tomasz Figa
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in the body of a message to
> > majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-19 13:35 ` Tomasz Figa
0 siblings, 0 replies; 84+ messages in thread
From: Tomasz Figa @ 2012-07-19 13:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Leela,
On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
> Hi Tomasz,
>
> On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
wrote:
> > Hi,
> >
> > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> >> This patch updates the register address offsets and adds SFR
> >> definitions
> >> for writeback for Samsung's V8 display controller.
> >>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >>
> >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> >>
> >> +++++++++++++++++++++++ drivers/video/Kconfig
> >>
> >> | 6 +++
> >>
> >> 3 files changed, 67 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
> >> 4c3647f..1639c17
> >> 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> @@ -30,9 +30,16 @@
> >>
> >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> >>
> >> /* Video timing controls */
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON0 (0x20010)
> >> +#define VIDTCON1 (0x20014)
> >> +#define VIDTCON3 (0x2001C)
> >> +#else
> >>
> >> #define VIDTCON0 (0x10)
> >> #define VIDTCON1 (0x14)
> >> #define VIDTCON2 (0x18)
> >>
> >> +#define VIDTCON3 (0x1C)
> >> +#endif
> >
> > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> > kernel)?
> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> As address offsets for certain registers has changed in FIMD_V8, we
> introduced these defines.
> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
> and deselect for other SoCs.
Yes, I'm aware of different FIMD versions in different SoCs. My point is
that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
support other SoCs than Exynos5, i.e. additional config options should be
incremental - should not break other setups. Ideally there should not be
any new config option for FIMD v8.
The detection of FIMD version and selection of appropriate register offsets
should be done in the driver at runtime, based for example on
platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
and s3c_fb_win_variant structs).
Best regards,
Tomasz Figa
>
> >> /* Window position controls */
> >>
> >> @@ -43,9 +50,12 @@
> >>
> >> #define VIDOSD_BASE (0x40)
> >>
> >> #define VIDINTCON0 (0x130)
> >>
> >> +#define VIDINTCON1 (0x134)
> >>
> >> /* WINCONx */
> >>
> >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> >>
> >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> #define WINCONx_CSCWIDTH_SHIFT (26)
> >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
> >> 100644
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> @@ -32,12 +32,28 @@
> >>
> >> #define VIDCON0 (0x00)
> >> #define VIDCON0_INTERLACE (1 << 29)
> >>
> >> +
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> >> +#endif
> >> +
> >>
> >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> #define VIDCON0_VIDOUT_SHIFT (26)
> >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >>
> >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> >>
> >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> #define VIDCON0_L1_DATA_SHIFT (23)
> >>
> >> @@ -81,7 +97,13 @@
> >>
> >> #define VIDCON0_ENVID (1 << 1)
> >> #define VIDCON0_ENVID_F (1 << 0)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDOUT_CON (0x20000)
> >> +#define VIDCON1 (0x20004)
> >> +#else
> >>
> >> #define VIDCON1 (0x04)
> >>
> >> +#endif
> >
> > Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
> > several lines above?
>
> Will be corrected in the next version patch set.
>
> Best Wishes,
> Leela Krishna Amudala.
>
> >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> #define VIDCON1_LINECNT_SHIFT (16)
> >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
> >> 0x7ff)>>
> >> @@ -111,6 +133,14 @@
> >>
> >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >>
> >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> >> +
> >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >>
> >> #define VIDCON2_ORGYCbCr (1 << 8)
> >> #define VIDCON2_YUVORDCrCb (1 << 7)
> >>
> >> @@ -165,8 +195,15 @@
> >>
> >> #define VIDTCON1_HSPW_SHIFT (0)
> >> #define VIDTCON1_HSPW_LIMIT (0xff)
> >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> >>
> >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >>
> >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> +#define VIDTCON2 (0x20018)
> >> +#else
> >>
> >> #define VIDTCON2 (0x18)
> >>
> >> +#endif
> >
> > Same as in my first comment.
> >
> >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800)
> >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
> >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
> >> (11)
> >>
> >> @@ -186,6 +223,9 @@
> >>
> >> #define WINCONx_BYTSWP (1 << 17)
> >> #define WINCONx_HAWSWP (1 << 16)
> >> #define WINCONx_WSWP (1 << 15)
> >>
> >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> >> +#define WINCONx_INRGB_RGB (0 << 13)
> >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> >>
> >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> #define WINCONx_BURSTLEN_SHIFT (9)
> >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >>
> >> @@ -205,6 +245,7 @@
> >>
> >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >>
> >> #define WINCON1_BLD_PIX (1 << 6)
> >>
> >> +#define WINCON1_BLD_PLANE (0 << 6)
> >>
> >> #define WINCON1_ALPHA_SEL (1 << 1)
> >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> >>
> >> @@ -395,9 +436,19 @@
> >>
> >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >>
> >> +/* Clock gate mode control */
> >> +#define REG_CLKGATE_MODE (0x1b0)
> >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> >> +
> >>
> >> /* Blending equation control */
> >> #define BLENDCON (0x260)
> >> #define BLENDCON_NEW_MASK (1 << 0)
> >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >>
> >> +/* Window alpha control */
> >> +#define VIDW0ALPHA0 (0x200)
> >> +#define VIDW0ALPHA1 (0x204)
> >> +#define DPCLKCON (0x27c)
> >> +#define DPCLKCON_ENABLE (1 << 1)
> >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> >> index 0217f74..f81bf55 100644
> >> --- a/drivers/video/Kconfig
> >> +++ b/drivers/video/Kconfig
> >> @@ -2053,6 +2053,12 @@ config FB_S3C
> >>
> >> Currently the support is only for the S3C6400 and S3C6410
> >> SoCs.
> >>
> >> +config FB_EXYNOS_FIMD_V8
> >> + bool "register extensions for FIMD version 8"
> >> + depends on ARCH_EXYNOS5
> >> + ---help---
> >> + This uses register extensions for FIMD version 8
> >> +
> >>
> >> config FB_S3C_DEBUG_REGWRITE
> >>
> >> bool "Debug register writes"
> >> depends on FB_S3C
> >
> > Best regards,
> > Tomasz Figa
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in the body of a message to
> > majordomo at vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-19 13:35 ` Tomasz Figa
@ 2012-07-20 2:21 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-20 2:21 UTC (permalink / raw)
To: 'Tomasz Figa', 'Leela Krishna Amudala'
Cc: devicetree-discuss, linux-arm-kernel, linux-samsung-soc,
grant.likely, olofj, thomas.ab, kgene.kim, joshi
On Thursday, July 19, 2012 10:35 PM, Tomasz Figa wrote:
>
> Hi Leela,
>
> On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
> > Hi Tomasz,
> >
> > On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
> wrote:
> > > Hi,
> > >
> > > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> > >> This patch updates the register address offsets and adds SFR
> > >> definitions
> > >> for writeback for Samsung's V8 display controller.
> > >>
> > >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> > >> ---
> > >>
> > >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> > >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> > >>
> > >> +++++++++++++++++++++++ drivers/video/Kconfig
> > >>
> > >> | 6 +++
> > >>
> > >> 3 files changed, 67 insertions(+), 0 deletions(-)
> > >>
> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
> > >> 4c3647f..1639c17
> > >> 100644
> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > >> @@ -30,9 +30,16 @@
> > >>
> > >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> > >>
> > >> /* Video timing controls */
> > >>
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDTCON0 (0x20010)
> > >> +#define VIDTCON1 (0x20014)
> > >> +#define VIDTCON3 (0x2001C)
> > >> +#else
> > >>
> > >> #define VIDTCON0 (0x10)
> > >> #define VIDTCON1 (0x14)
> > >> #define VIDTCON2 (0x18)
> > >>
> > >> +#define VIDTCON3 (0x1C)
> > >> +#endif
> > >
> > > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> > > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> > > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> > > kernel)?
> > Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> > As address offsets for certain registers has changed in FIMD_V8, we
> > introduced these defines.
> > So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
> > and deselect for other SoCs.
>
> Yes, I'm aware of different FIMD versions in different SoCs. My point is
> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
> support other SoCs than Exynos5, i.e. additional config options should be
> incremental - should not break other setups. Ideally there should not be
> any new config option for FIMD v8.
>
> The detection of FIMD version and selection of appropriate register offsets
> should be done in the driver at runtime, based for example on
> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
> and s3c_fb_win_variant structs).
I could not agree with Tomasz Figa more.
FIMD register offset should be selected at runtime.
Leela Krishna Amudala,
Please, don't use ugly "#ifdef".
Best regards,
Jingoo Han
>
> Best regards,
> Tomasz Figa
>
> >
> > >> /* Window position controls */
> > >>
> > >> @@ -43,9 +50,12 @@
> > >>
> > >> #define VIDOSD_BASE (0x40)
> > >>
> > >> #define VIDINTCON0 (0x130)
> > >>
> > >> +#define VIDINTCON1 (0x134)
> > >>
> > >> /* WINCONx */
> > >>
> > >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> > >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> > >>
> > >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> > >> #define WINCONx_CSCWIDTH_SHIFT (26)
> > >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> > >>
> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> > >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
> > >> 100644
> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> > >> @@ -32,12 +32,28 @@
> > >>
> > >> #define VIDCON0 (0x00)
> > >> #define VIDCON0_INTERLACE (1 << 29)
> > >>
> > >> +
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDOUT_CON (0x20000)
> > >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> > >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> > >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> > >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> > >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> > >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> > >> +#endif
> > >> +
> > >>
> > >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> > >> #define VIDCON0_VIDOUT_SHIFT (26)
> > >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> > >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> > >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> > >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> > >>
> > >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> > >>
> > >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> > >> #define VIDCON0_L1_DATA_SHIFT (23)
> > >>
> > >> @@ -81,7 +97,13 @@
> > >>
> > >> #define VIDCON0_ENVID (1 << 1)
> > >> #define VIDCON0_ENVID_F (1 << 0)
> > >>
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDOUT_CON (0x20000)
> > >> +#define VIDCON1 (0x20004)
> > >> +#else
> > >>
> > >> #define VIDCON1 (0x04)
> > >>
> > >> +#endif
> > >
> > > Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
> > > several lines above?
> >
> > Will be corrected in the next version patch set.
> >
> > Best Wishes,
> > Leela Krishna Amudala.
> >
> > >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> > >> #define VIDCON1_LINECNT_SHIFT (16)
> > >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
> > >> 0x7ff)>>
> > >> @@ -111,6 +133,14 @@
> > >>
> > >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> > >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> > >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> > >>
> > >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> > >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> > >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> > >> +
> > >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> > >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> > >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> > >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> > >>
> > >> #define VIDCON2_ORGYCbCr (1 << 8)
> > >> #define VIDCON2_YUVORDCrCb (1 << 7)
> > >>
> > >> @@ -165,8 +195,15 @@
> > >>
> > >> #define VIDTCON1_HSPW_SHIFT (0)
> > >> #define VIDTCON1_HSPW_LIMIT (0xff)
> > >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> > >>
> > >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> > >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> > >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> > >>
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDTCON2 (0x20018)
> > >> +#else
> > >>
> > >> #define VIDTCON2 (0x18)
> > >>
> > >> +#endif
> > >
> > > Same as in my first comment.
> > >
> > >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800)
> > >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
> > >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
> > >> (11)
> > >>
> > >> @@ -186,6 +223,9 @@
> > >>
> > >> #define WINCONx_BYTSWP (1 << 17)
> > >> #define WINCONx_HAWSWP (1 << 16)
> > >> #define WINCONx_WSWP (1 << 15)
> > >>
> > >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> > >> +#define WINCONx_INRGB_RGB (0 << 13)
> > >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> > >>
> > >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> > >> #define WINCONx_BURSTLEN_SHIFT (9)
> > >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> > >>
> > >> @@ -205,6 +245,7 @@
> > >>
> > >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> > >>
> > >> #define WINCON1_BLD_PIX (1 << 6)
> > >>
> > >> +#define WINCON1_BLD_PLANE (0 << 6)
> > >>
> > >> #define WINCON1_ALPHA_SEL (1 << 1)
> > >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> > >>
> > >> @@ -395,9 +436,19 @@
> > >>
> > >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> > >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> > >>
> > >> +/* Clock gate mode control */
> > >> +#define REG_CLKGATE_MODE (0x1b0)
> > >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> > >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> > >> +
> > >>
> > >> /* Blending equation control */
> > >> #define BLENDCON (0x260)
> > >> #define BLENDCON_NEW_MASK (1 << 0)
> > >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> > >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> > >>
> > >> +/* Window alpha control */
> > >> +#define VIDW0ALPHA0 (0x200)
> > >> +#define VIDW0ALPHA1 (0x204)
> > >> +#define DPCLKCON (0x27c)
> > >> +#define DPCLKCON_ENABLE (1 << 1)
> > >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> > >> index 0217f74..f81bf55 100644
> > >> --- a/drivers/video/Kconfig
> > >> +++ b/drivers/video/Kconfig
> > >> @@ -2053,6 +2053,12 @@ config FB_S3C
> > >>
> > >> Currently the support is only for the S3C6400 and S3C6410
> > >> SoCs.
> > >>
> > >> +config FB_EXYNOS_FIMD_V8
> > >> + bool "register extensions for FIMD version 8"
> > >> + depends on ARCH_EXYNOS5
> > >> + ---help---
> > >> + This uses register extensions for FIMD version 8
> > >> +
> > >>
> > >> config FB_S3C_DEBUG_REGWRITE
> > >>
> > >> bool "Debug register writes"
> > >> depends on FB_S3C
> > >
> > > Best regards,
> > > Tomasz Figa
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe
> > > linux-samsung-soc" in the body of a message to
> > > majordomo@vger.kernel.org
> > > More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 2:21 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-20 2:21 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday, July 19, 2012 10:35 PM, Tomasz Figa wrote:
>
> Hi Leela,
>
> On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
> > Hi Tomasz,
> >
> > On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
> wrote:
> > > Hi,
> > >
> > > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> > >> This patch updates the register address offsets and adds SFR
> > >> definitions
> > >> for writeback for Samsung's V8 display controller.
> > >>
> > >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> > >> ---
> > >>
> > >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> > >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> > >>
> > >> +++++++++++++++++++++++ drivers/video/Kconfig
> > >>
> > >> | 6 +++
> > >>
> > >> 3 files changed, 67 insertions(+), 0 deletions(-)
> > >>
> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
> > >> 4c3647f..1639c17
> > >> 100644
> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > >> @@ -30,9 +30,16 @@
> > >>
> > >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> > >>
> > >> /* Video timing controls */
> > >>
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDTCON0 (0x20010)
> > >> +#define VIDTCON1 (0x20014)
> > >> +#define VIDTCON3 (0x2001C)
> > >> +#else
> > >>
> > >> #define VIDTCON0 (0x10)
> > >> #define VIDTCON1 (0x14)
> > >> #define VIDTCON2 (0x18)
> > >>
> > >> +#define VIDTCON3 (0x1C)
> > >> +#endif
> > >
> > > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> > > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> > > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> > > kernel)?
> > Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> > As address offsets for certain registers has changed in FIMD_V8, we
> > introduced these defines.
> > So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
> > and deselect for other SoCs.
>
> Yes, I'm aware of different FIMD versions in different SoCs. My point is
> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
> support other SoCs than Exynos5, i.e. additional config options should be
> incremental - should not break other setups. Ideally there should not be
> any new config option for FIMD v8.
>
> The detection of FIMD version and selection of appropriate register offsets
> should be done in the driver at runtime, based for example on
> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
> and s3c_fb_win_variant structs).
I could not agree with Tomasz Figa more.
FIMD register offset should be selected at runtime.
Leela Krishna Amudala,
Please, don't use ugly "#ifdef".
Best regards,
Jingoo Han
>
> Best regards,
> Tomasz Figa
>
> >
> > >> /* Window position controls */
> > >>
> > >> @@ -43,9 +50,12 @@
> > >>
> > >> #define VIDOSD_BASE (0x40)
> > >>
> > >> #define VIDINTCON0 (0x130)
> > >>
> > >> +#define VIDINTCON1 (0x134)
> > >>
> > >> /* WINCONx */
> > >>
> > >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> > >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> > >>
> > >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> > >> #define WINCONx_CSCWIDTH_SHIFT (26)
> > >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> > >>
> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> > >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
> > >> 100644
> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> > >> @@ -32,12 +32,28 @@
> > >>
> > >> #define VIDCON0 (0x00)
> > >> #define VIDCON0_INTERLACE (1 << 29)
> > >>
> > >> +
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDOUT_CON (0x20000)
> > >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> > >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> > >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> > >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> > >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> > >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> > >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> > >> +#endif
> > >> +
> > >>
> > >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> > >> #define VIDCON0_VIDOUT_SHIFT (26)
> > >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> > >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> > >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> > >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> > >>
> > >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> > >>
> > >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> > >> #define VIDCON0_L1_DATA_SHIFT (23)
> > >>
> > >> @@ -81,7 +97,13 @@
> > >>
> > >> #define VIDCON0_ENVID (1 << 1)
> > >> #define VIDCON0_ENVID_F (1 << 0)
> > >>
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDOUT_CON (0x20000)
> > >> +#define VIDCON1 (0x20004)
> > >> +#else
> > >>
> > >> #define VIDCON1 (0x04)
> > >>
> > >> +#endif
> > >
> > > Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
> > > several lines above?
> >
> > Will be corrected in the next version patch set.
> >
> > Best Wishes,
> > Leela Krishna Amudala.
> >
> > >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> > >> #define VIDCON1_LINECNT_SHIFT (16)
> > >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
> > >> 0x7ff)>>
> > >> @@ -111,6 +133,14 @@
> > >>
> > >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> > >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> > >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> > >>
> > >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> > >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> > >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> > >> +
> > >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> > >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> > >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> > >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> > >>
> > >> #define VIDCON2_ORGYCbCr (1 << 8)
> > >> #define VIDCON2_YUVORDCrCb (1 << 7)
> > >>
> > >> @@ -165,8 +195,15 @@
> > >>
> > >> #define VIDTCON1_HSPW_SHIFT (0)
> > >> #define VIDTCON1_HSPW_LIMIT (0xff)
> > >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> > >>
> > >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> > >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> > >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> > >>
> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> > >> +#define VIDTCON2 (0x20018)
> > >> +#else
> > >>
> > >> #define VIDTCON2 (0x18)
> > >>
> > >> +#endif
> > >
> > > Same as in my first comment.
> > >
> > >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800)
> > >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
> > >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
> > >> (11)
> > >>
> > >> @@ -186,6 +223,9 @@
> > >>
> > >> #define WINCONx_BYTSWP (1 << 17)
> > >> #define WINCONx_HAWSWP (1 << 16)
> > >> #define WINCONx_WSWP (1 << 15)
> > >>
> > >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> > >> +#define WINCONx_INRGB_RGB (0 << 13)
> > >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> > >>
> > >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> > >> #define WINCONx_BURSTLEN_SHIFT (9)
> > >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> > >>
> > >> @@ -205,6 +245,7 @@
> > >>
> > >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> > >>
> > >> #define WINCON1_BLD_PIX (1 << 6)
> > >>
> > >> +#define WINCON1_BLD_PLANE (0 << 6)
> > >>
> > >> #define WINCON1_ALPHA_SEL (1 << 1)
> > >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> > >>
> > >> @@ -395,9 +436,19 @@
> > >>
> > >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> > >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> > >>
> > >> +/* Clock gate mode control */
> > >> +#define REG_CLKGATE_MODE (0x1b0)
> > >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> > >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> > >> +
> > >>
> > >> /* Blending equation control */
> > >> #define BLENDCON (0x260)
> > >> #define BLENDCON_NEW_MASK (1 << 0)
> > >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> > >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> > >>
> > >> +/* Window alpha control */
> > >> +#define VIDW0ALPHA0 (0x200)
> > >> +#define VIDW0ALPHA1 (0x204)
> > >> +#define DPCLKCON (0x27c)
> > >> +#define DPCLKCON_ENABLE (1 << 1)
> > >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> > >> index 0217f74..f81bf55 100644
> > >> --- a/drivers/video/Kconfig
> > >> +++ b/drivers/video/Kconfig
> > >> @@ -2053,6 +2053,12 @@ config FB_S3C
> > >>
> > >> Currently the support is only for the S3C6400 and S3C6410
> > >> SoCs.
> > >>
> > >> +config FB_EXYNOS_FIMD_V8
> > >> + bool "register extensions for FIMD version 8"
> > >> + depends on ARCH_EXYNOS5
> > >> + ---help---
> > >> + This uses register extensions for FIMD version 8
> > >> +
> > >>
> > >> config FB_S3C_DEBUG_REGWRITE
> > >>
> > >> bool "Debug register writes"
> > >> depends on FB_S3C
> > >
> > > Best regards,
> > > Tomasz Figa
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe
> > > linux-samsung-soc" in the body of a message to
> > > majordomo at vger.kernel.org
> > > More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-20 2:21 ` Jingoo Han
@ 2012-07-20 2:59 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-20 2:59 UTC (permalink / raw)
To: Jingoo Han, Tomasz Figa
Cc: linux-samsung-soc, devicetree-discuss, joshi, thomas.ab,
kgene.kim, olofj, linux-arm-kernel
On Fri, Jul 20, 2012 at 7:51 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> On Thursday, July 19, 2012 10:35 PM, Tomasz Figa wrote:
>>
>> Hi Leela,
>>
>> On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
>> > Hi Tomasz,
>> >
>> > On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
>> wrote:
>> > > Hi,
>> > >
>> > > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
>> > >> This patch updates the register address offsets and adds SFR
>> > >> definitions
>> > >> for writeback for Samsung's V8 display controller.
>> > >>
>> > >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> > >> ---
>> > >>
>> > >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> > >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
>> > >>
>> > >> +++++++++++++++++++++++ drivers/video/Kconfig
>> > >>
>> > >> | 6 +++
>> > >>
>> > >> 3 files changed, 67 insertions(+), 0 deletions(-)
>> > >>
>> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> > >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
>> > >> 4c3647f..1639c17
>> > >> 100644
>> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> > >> @@ -30,9 +30,16 @@
>> > >>
>> > >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>> > >>
>> > >> /* Video timing controls */
>> > >>
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDTCON0 (0x20010)
>> > >> +#define VIDTCON1 (0x20014)
>> > >> +#define VIDTCON3 (0x2001C)
>> > >> +#else
>> > >>
>> > >> #define VIDTCON0 (0x10)
>> > >> #define VIDTCON1 (0x14)
>> > >> #define VIDTCON2 (0x18)
>> > >>
>> > >> +#define VIDTCON3 (0x1C)
>> > >> +#endif
>> > >
>> > > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
>> > > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
>> > > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
>> > > kernel)?
>> > Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
>> > As address offsets for certain registers has changed in FIMD_V8, we
>> > introduced these defines.
>> > So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
>> > and deselect for other SoCs.
>>
>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
>> support other SoCs than Exynos5, i.e. additional config options should be
>> incremental - should not break other setups. Ideally there should not be
>> any new config option for FIMD v8.
>>
>> The detection of FIMD version and selection of appropriate register offsets
>> should be done in the driver at runtime, based for example on
>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
>> and s3c_fb_win_variant structs).
>
> I could not agree with Tomasz Figa more.
> FIMD register offset should be selected at runtime.
>
> Leela Krishna Amudala,
> Please, don't use ugly "#ifdef".
>
> Best regards,
> Jingoo Han
>
Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
exynos5_defconfig etc.,)
So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
it won't affect the other SoCs.
Best Wishes,
Leela Krishna Amudala.
>>
>> Best regards,
>> Tomasz Figa
>>
>> >
>> > >> /* Window position controls */
>> > >>
>> > >> @@ -43,9 +50,12 @@
>> > >>
>> > >> #define VIDOSD_BASE (0x40)
>> > >>
>> > >> #define VIDINTCON0 (0x130)
>> > >>
>> > >> +#define VIDINTCON1 (0x134)
>> > >>
>> > >> /* WINCONx */
>> > >>
>> > >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> > >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> > >>
>> > >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> > >> #define WINCONx_CSCWIDTH_SHIFT (26)
>> > >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> > >>
>> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> > >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
>> > >> 100644
>> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> > >> @@ -32,12 +32,28 @@
>> > >>
>> > >> #define VIDCON0 (0x00)
>> > >> #define VIDCON0_INTERLACE (1 << 29)
>> > >>
>> > >> +
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDOUT_CON (0x20000)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> > >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> > >> +#endif
>> > >> +
>> > >>
>> > >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> > >> #define VIDCON0_VIDOUT_SHIFT (26)
>> > >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> > >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> > >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> > >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> > >>
>> > >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>> > >>
>> > >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> > >> #define VIDCON0_L1_DATA_SHIFT (23)
>> > >>
>> > >> @@ -81,7 +97,13 @@
>> > >>
>> > >> #define VIDCON0_ENVID (1 << 1)
>> > >> #define VIDCON0_ENVID_F (1 << 0)
>> > >>
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDOUT_CON (0x20000)
>> > >> +#define VIDCON1 (0x20004)
>> > >> +#else
>> > >>
>> > >> #define VIDCON1 (0x04)
>> > >>
>> > >> +#endif
>> > >
>> > > Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
>> > > several lines above?
>> >
>> > Will be corrected in the next version patch set.
>> >
>> > Best Wishes,
>> > Leela Krishna Amudala.
>> >
>> > >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> > >> #define VIDCON1_LINECNT_SHIFT (16)
>> > >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
>> > >> 0x7ff)>>
>> > >> @@ -111,6 +133,14 @@
>> > >>
>> > >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> > >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> > >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> > >>
>> > >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> > >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> > >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> > >> +
>> > >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> > >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> > >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> > >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> > >>
>> > >> #define VIDCON2_ORGYCbCr (1 << 8)
>> > >> #define VIDCON2_YUVORDCrCb (1 << 7)
>> > >>
>> > >> @@ -165,8 +195,15 @@
>> > >>
>> > >> #define VIDTCON1_HSPW_SHIFT (0)
>> > >> #define VIDTCON1_HSPW_LIMIT (0xff)
>> > >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> > >>
>> > >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> > >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> > >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>> > >>
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDTCON2 (0x20018)
>> > >> +#else
>> > >>
>> > >> #define VIDTCON2 (0x18)
>> > >>
>> > >> +#endif
>> > >
>> > > Same as in my first comment.
>> > >
>> > >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800)
>> > >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
>> > >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
>> > >> (11)
>> > >>
>> > >> @@ -186,6 +223,9 @@
>> > >>
>> > >> #define WINCONx_BYTSWP (1 << 17)
>> > >> #define WINCONx_HAWSWP (1 << 16)
>> > >> #define WINCONx_WSWP (1 << 15)
>> > >>
>> > >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> > >> +#define WINCONx_INRGB_RGB (0 << 13)
>> > >> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> > >>
>> > >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> > >> #define WINCONx_BURSTLEN_SHIFT (9)
>> > >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> > >>
>> > >> @@ -205,6 +245,7 @@
>> > >>
>> > >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>> > >>
>> > >> #define WINCON1_BLD_PIX (1 << 6)
>> > >>
>> > >> +#define WINCON1_BLD_PLANE (0 << 6)
>> > >>
>> > >> #define WINCON1_ALPHA_SEL (1 << 1)
>> > >> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> > >>
>> > >> @@ -395,9 +436,19 @@
>> > >>
>> > >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> > >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>> > >>
>> > >> +/* Clock gate mode control */
>> > >> +#define REG_CLKGATE_MODE (0x1b0)
>> > >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> > >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> > >> +
>> > >>
>> > >> /* Blending equation control */
>> > >> #define BLENDCON (0x260)
>> > >> #define BLENDCON_NEW_MASK (1 << 0)
>> > >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> > >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>> > >>
>> > >> +/* Window alpha control */
>> > >> +#define VIDW0ALPHA0 (0x200)
>> > >> +#define VIDW0ALPHA1 (0x204)
>> > >> +#define DPCLKCON (0x27c)
>> > >> +#define DPCLKCON_ENABLE (1 << 1)
>> > >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> > >> index 0217f74..f81bf55 100644
>> > >> --- a/drivers/video/Kconfig
>> > >> +++ b/drivers/video/Kconfig
>> > >> @@ -2053,6 +2053,12 @@ config FB_S3C
>> > >>
>> > >> Currently the support is only for the S3C6400 and S3C6410
>> > >> SoCs.
>> > >>
>> > >> +config FB_EXYNOS_FIMD_V8
>> > >> + bool "register extensions for FIMD version 8"
>> > >> + depends on ARCH_EXYNOS5
>> > >> + ---help---
>> > >> + This uses register extensions for FIMD version 8
>> > >> +
>> > >>
>> > >> config FB_S3C_DEBUG_REGWRITE
>> > >>
>> > >> bool "Debug register writes"
>> > >> depends on FB_S3C
>> > >
>> > > Best regards,
>> > > Tomasz Figa
>> > >
>> > > --
>> > > To unsubscribe from this list: send the line "unsubscribe
>> > > linux-samsung-soc" in the body of a message to
>> > > majordomo@vger.kernel.org
>> > > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 2:59 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-20 2:59 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 20, 2012 at 7:51 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> On Thursday, July 19, 2012 10:35 PM, Tomasz Figa wrote:
>>
>> Hi Leela,
>>
>> On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
>> > Hi Tomasz,
>> >
>> > On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
>> wrote:
>> > > Hi,
>> > >
>> > > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
>> > >> This patch updates the register address offsets and adds SFR
>> > >> definitions
>> > >> for writeback for Samsung's V8 display controller.
>> > >>
>> > >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> > >> ---
>> > >>
>> > >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
>> > >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
>> > >>
>> > >> +++++++++++++++++++++++ drivers/video/Kconfig
>> > >>
>> > >> | 6 +++
>> > >>
>> > >> 3 files changed, 67 insertions(+), 0 deletions(-)
>> > >>
>> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> > >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
>> > >> 4c3647f..1639c17
>> > >> 100644
>> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> > >> @@ -30,9 +30,16 @@
>> > >>
>> > >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
>> > >>
>> > >> /* Video timing controls */
>> > >>
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDTCON0 (0x20010)
>> > >> +#define VIDTCON1 (0x20014)
>> > >> +#define VIDTCON3 (0x2001C)
>> > >> +#else
>> > >>
>> > >> #define VIDTCON0 (0x10)
>> > >> #define VIDTCON1 (0x14)
>> > >> #define VIDTCON2 (0x18)
>> > >>
>> > >> +#define VIDTCON3 (0x1C)
>> > >> +#endif
>> > >
>> > > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
>> > > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
>> > > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
>> > > kernel)?
>> > Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
>> > As address offsets for certain registers has changed in FIMD_V8, we
>> > introduced these defines.
>> > So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
>> > and deselect for other SoCs.
>>
>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
>> support other SoCs than Exynos5, i.e. additional config options should be
>> incremental - should not break other setups. Ideally there should not be
>> any new config option for FIMD v8.
>>
>> The detection of FIMD version and selection of appropriate register offsets
>> should be done in the driver at runtime, based for example on
>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
>> and s3c_fb_win_variant structs).
>
> I could not agree with Tomasz Figa more.
> FIMD register offset should be selected at runtime.
>
> Leela Krishna Amudala,
> Please, don't use ugly "#ifdef".
>
> Best regards,
> Jingoo Han
>
Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
exynos5_defconfig etc.,)
So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
it won't affect the other SoCs.
Best Wishes,
Leela Krishna Amudala.
>>
>> Best regards,
>> Tomasz Figa
>>
>> >
>> > >> /* Window position controls */
>> > >>
>> > >> @@ -43,9 +50,12 @@
>> > >>
>> > >> #define VIDOSD_BASE (0x40)
>> > >>
>> > >> #define VIDINTCON0 (0x130)
>> > >>
>> > >> +#define VIDINTCON1 (0x134)
>> > >>
>> > >> /* WINCONx */
>> > >>
>> > >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
>> > >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
>> > >>
>> > >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> > >> #define WINCONx_CSCWIDTH_SHIFT (26)
>> > >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> > >>
>> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> > >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16
>> > >> 100644
>> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> > >> @@ -32,12 +32,28 @@
>> > >>
>> > >> #define VIDCON0 (0x00)
>> > >> #define VIDCON0_INTERLACE (1 << 29)
>> > >>
>> > >> +
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDOUT_CON (0x20000)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
>> > >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
>> > >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
>> > >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
>> > >> +#endif
>> > >> +
>> > >>
>> > >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> > >> #define VIDCON0_VIDOUT_SHIFT (26)
>> > >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> > >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
>> > >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> > >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> > >>
>> > >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
>> > >>
>> > >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> > >> #define VIDCON0_L1_DATA_SHIFT (23)
>> > >>
>> > >> @@ -81,7 +97,13 @@
>> > >>
>> > >> #define VIDCON0_ENVID (1 << 1)
>> > >> #define VIDCON0_ENVID_F (1 << 0)
>> > >>
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDOUT_CON (0x20000)
>> > >> +#define VIDCON1 (0x20004)
>> > >> +#else
>> > >>
>> > >> #define VIDCON1 (0x04)
>> > >>
>> > >> +#endif
>> > >
>> > > Same here. Also isn't it a redefinition of VIDOUT_CON that was defined
>> > > several lines above?
>> >
>> > Will be corrected in the next version patch set.
>> >
>> > Best Wishes,
>> > Leela Krishna Amudala.
>> >
>> > >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> > >> #define VIDCON1_LINECNT_SHIFT (16)
>> > >> #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
>> > >> 0x7ff)>>
>> > >> @@ -111,6 +133,14 @@
>> > >>
>> > >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> > >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> > >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> > >>
>> > >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> > >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> > >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
>> > >> +
>> > >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> > >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> > >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> > >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> > >>
>> > >> #define VIDCON2_ORGYCbCr (1 << 8)
>> > >> #define VIDCON2_YUVORDCrCb (1 << 7)
>> > >>
>> > >> @@ -165,8 +195,15 @@
>> > >>
>> > >> #define VIDTCON1_HSPW_SHIFT (0)
>> > >> #define VIDTCON1_HSPW_LIMIT (0xff)
>> > >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
>> > >>
>> > >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> > >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> > >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>> > >>
>> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>> > >> +#define VIDTCON2 (0x20018)
>> > >> +#else
>> > >>
>> > >> #define VIDTCON2 (0x18)
>> > >>
>> > >> +#endif
>> > >
>> > > Same as in my first comment.
>> > >
>> > >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800)
>> > >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
>> > >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
>> > >> (11)
>> > >>
>> > >> @@ -186,6 +223,9 @@
>> > >>
>> > >> #define WINCONx_BYTSWP (1 << 17)
>> > >> #define WINCONx_HAWSWP (1 << 16)
>> > >> #define WINCONx_WSWP (1 << 15)
>> > >>
>> > >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
>> > >> +#define WINCONx_INRGB_RGB (0 << 13)
>> > >> +#define WINCONx_INRGB_YCBCR (1 << 13)
>> > >>
>> > >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> > >> #define WINCONx_BURSTLEN_SHIFT (9)
>> > >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> > >>
>> > >> @@ -205,6 +245,7 @@
>> > >>
>> > >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>> > >>
>> > >> #define WINCON1_BLD_PIX (1 << 6)
>> > >>
>> > >> +#define WINCON1_BLD_PLANE (0 << 6)
>> > >>
>> > >> #define WINCON1_ALPHA_SEL (1 << 1)
>> > >> #define WINCON1_BPPMODE_MASK (0xf << 2)
>> > >>
>> > >> @@ -395,9 +436,19 @@
>> > >>
>> > >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> > >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>> > >>
>> > >> +/* Clock gate mode control */
>> > >> +#define REG_CLKGATE_MODE (0x1b0)
>> > >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
>> > >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
>> > >> +
>> > >>
>> > >> /* Blending equation control */
>> > >> #define BLENDCON (0x260)
>> > >> #define BLENDCON_NEW_MASK (1 << 0)
>> > >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> > >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>> > >>
>> > >> +/* Window alpha control */
>> > >> +#define VIDW0ALPHA0 (0x200)
>> > >> +#define VIDW0ALPHA1 (0x204)
>> > >> +#define DPCLKCON (0x27c)
>> > >> +#define DPCLKCON_ENABLE (1 << 1)
>> > >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
>> > >> index 0217f74..f81bf55 100644
>> > >> --- a/drivers/video/Kconfig
>> > >> +++ b/drivers/video/Kconfig
>> > >> @@ -2053,6 +2053,12 @@ config FB_S3C
>> > >>
>> > >> Currently the support is only for the S3C6400 and S3C6410
>> > >> SoCs.
>> > >>
>> > >> +config FB_EXYNOS_FIMD_V8
>> > >> + bool "register extensions for FIMD version 8"
>> > >> + depends on ARCH_EXYNOS5
>> > >> + ---help---
>> > >> + This uses register extensions for FIMD version 8
>> > >> +
>> > >>
>> > >> config FB_S3C_DEBUG_REGWRITE
>> > >>
>> > >> bool "Debug register writes"
>> > >> depends on FB_S3C
>> > >
>> > > Best regards,
>> > > Tomasz Figa
>> > >
>> > > --
>> > > To unsubscribe from this list: send the line "unsubscribe
>> > > linux-samsung-soc" in the body of a message to
>> > > majordomo at vger.kernel.org
>> > > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-20 2:59 ` Leela Krishna Amudala
@ 2012-07-20 9:49 ` Tomasz Figa
-1 siblings, 0 replies; 84+ messages in thread
From: Tomasz Figa @ 2012-07-20 9:49 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: Jingoo Han, linux-samsung-soc, devicetree-discuss, joshi,
thomas.ab, kgene.kim, olofj, linux-arm-kernel
Hi,
On Friday 20 of July 2012 08:29:21 Leela Krishna Amudala wrote:
> On Fri, Jul 20, 2012 at 7:51 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Thursday, July 19, 2012 10:35 PM, Tomasz Figa wrote:
> >> Hi Leela,
> >>
> >> On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
> >> > Hi Tomasz,
> >> >
> >> > On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
> >>
> >> wrote:
> >> > > Hi,
> >> > >
> >> > > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> >> > >> This patch updates the register address offsets and adds SFR
> >> > >> definitions
> >> > >> for writeback for Samsung's V8 display controller.
> >> > >>
> >> > >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> > >> ---
> >> > >>
> >> > >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> >> > >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> >> > >>
> >> > >> +++++++++++++++++++++++ drivers/video/Kconfig
> >> > >>
> >> > >> | 6 +++
> >> > >>
> >> > >> 3 files changed, 67 insertions(+), 0 deletions(-)
> >> > >>
> >> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> > >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
> >> > >> 4c3647f..1639c17
> >> > >> 100644
> >> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> > >> @@ -30,9 +30,16 @@
> >> > >>
> >> > >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> >> > >>
> >> > >> /* Video timing controls */
> >> > >>
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDTCON0 (0x20010)
> >> > >> +#define VIDTCON1 (0x20014)
> >> > >> +#define VIDTCON3 (0x2001C)
> >> > >> +#else
> >> > >>
> >> > >> #define VIDTCON0 (0x10)
> >> > >> #define VIDTCON1 (0x14)
> >> > >> #define VIDTCON2 (0x18)
> >> > >>
> >> > >> +#define VIDTCON3 (0x1C)
> >> > >> +#endif
> >> > >
> >> > > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> >> > > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform
> >> > > ARM
> >> > > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> >> > > kernel)?
> >> >
> >> > Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> >> > As address offsets for certain registers has changed in FIMD_V8, we
> >> > introduced these defines.
> >> > So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5
> >> > SoC,
> >> > and deselect for other SoCs.
> >>
> >> Yes, I'm aware of different FIMD versions in different SoCs. My point
> >> is
> >> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
> >> support other SoCs than Exynos5, i.e. additional config options should
> >> be incremental - should not break other setups. Ideally there should
> >> not be any new config option for FIMD v8.
> >>
> >> The detection of FIMD version and selection of appropriate register
> >> offsets should be done in the driver at runtime, based for example on
> >> platform_device_id (see the s3c-fb driver and usage of
> >> s3c_fb_driverdata
> >> and s3c_fb_win_variant structs).
> >
> > I could not agree with Tomasz Figa more.
> > FIMD register offset should be selected at runtime.
> >
> > Leela Krishna Amudala,
> > Please, don't use ugly "#ifdef".
> >
> > Best regards,
> > Jingoo Han
>
> Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
> exynos5_defconfig etc.,)
> So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
> it won't affect the other SoCs.
>
> Best Wishes,
> Leela Krishna Amudala.
Defconfig is only used to build a kernel image for a single machine.
Let me give you another example. Consider that we want to build a single
kernel binary running on all Exynos SocS (this is what ARM Linux is
currently aiming at). What we do is enabling in config support for every
bit of every SoC we want to support in resulting kernel binary. Now with
your patch to support Exynos 5 in such kernel we would have to enable
CONFIG_FB_EXYNOS_FIMD_V8 to get support for FIMD on Exynos 5 leading to a
situation where we could have support for all Exynos SoCs in one kernel,
but, depending on one config option, either without FIMD support on Exynos
5 or on any older SoC.
Best regards,
Tom
> >> Best regards,
> >> Tomasz Figa
> >>
> >> > >> /* Window position controls */
> >> > >>
> >> > >> @@ -43,9 +50,12 @@
> >> > >>
> >> > >> #define VIDOSD_BASE (0x40)
> >> > >>
> >> > >> #define VIDINTCON0 (0x130)
> >> > >>
> >> > >> +#define VIDINTCON1 (0x134)
> >> > >>
> >> > >> /* WINCONx */
> >> > >>
> >> > >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> >> > >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> >> > >>
> >> > >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> > >> #define WINCONx_CSCWIDTH_SHIFT (26)
> >> > >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >> > >>
> >> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> > >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index
> >> > >> 9a78012..6d2ee16
> >> > >> 100644
> >> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> > >> @@ -32,12 +32,28 @@
> >> > >>
> >> > >> #define VIDCON0 (0x00)
> >> > >> #define VIDCON0_INTERLACE (1 << 29)
> >> > >>
> >> > >> +
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDOUT_CON (0x20000)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> >> > >> +#endif
> >> > >> +
> >> > >>
> >> > >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> > >> #define VIDCON0_VIDOUT_SHIFT (26)
> >> > >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> > >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> > >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> > >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >> > >>
> >> > >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> >> > >>
> >> > >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> > >> #define VIDCON0_L1_DATA_SHIFT (23)
> >> > >>
> >> > >> @@ -81,7 +97,13 @@
> >> > >>
> >> > >> #define VIDCON0_ENVID (1 << 1)
> >> > >> #define VIDCON0_ENVID_F (1 << 0)
> >> > >>
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDOUT_CON (0x20000)
> >> > >> +#define VIDCON1 (0x20004)
> >> > >> +#else
> >> > >>
> >> > >> #define VIDCON1 (0x04)
> >> > >>
> >> > >> +#endif
> >> > >
> >> > > Same here. Also isn't it a redefinition of VIDOUT_CON that was
> >> > > defined
> >> > > several lines above?
> >> >
> >> > Will be corrected in the next version patch set.
> >> >
> >> > Best Wishes,
> >> > Leela Krishna Amudala.
> >> >
> >> > >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> > >> #define VIDCON1_LINECNT_SHIFT (16)
> >> > >> #define VIDCON1_LINECNT_GET(_v) (((_v) >>
> >> > >> 16) &
> >> > >> 0x7ff)>>
> >> > >>
> >> > >> @@ -111,6 +133,14 @@
> >> > >>
> >> > >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> > >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> > >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> > >>
> >> > >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> > >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> > >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> >> > >> +
> >> > >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> > >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> > >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> > >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> > >>
> >> > >> #define VIDCON2_ORGYCbCr (1 << 8)
> >> > >> #define VIDCON2_YUVORDCrCb (1 << 7)
> >> > >>
> >> > >> @@ -165,8 +195,15 @@
> >> > >>
> >> > >> #define VIDTCON1_HSPW_SHIFT (0)
> >> > >> #define VIDTCON1_HSPW_LIMIT (0xff)
> >> > >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> >> > >>
> >> > >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> > >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> > >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >> > >>
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDTCON2 (0x20018)
> >> > >> +#else
> >> > >>
> >> > >> #define VIDTCON2 (0x18)
> >> > >>
> >> > >> +#endif
> >> > >
> >> > > Same as in my first comment.
> >> > >
> >> > >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) &
> >> > >> 0x800)
> >> > >>
> >> > >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
> >> > >>
> >> > >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
> >> > >> (11)
> >> > >>
> >> > >> @@ -186,6 +223,9 @@
> >> > >>
> >> > >> #define WINCONx_BYTSWP (1 << 17)
> >> > >> #define WINCONx_HAWSWP (1 << 16)
> >> > >> #define WINCONx_WSWP (1 << 15)
> >> > >>
> >> > >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> >> > >> +#define WINCONx_INRGB_RGB (0 << 13)
> >> > >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> >> > >>
> >> > >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> > >> #define WINCONx_BURSTLEN_SHIFT (9)
> >> > >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >> > >>
> >> > >> @@ -205,6 +245,7 @@
> >> > >>
> >> > >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >> > >>
> >> > >> #define WINCON1_BLD_PIX (1 << 6)
> >> > >>
> >> > >> +#define WINCON1_BLD_PLANE (0 << 6)
> >> > >>
> >> > >> #define WINCON1_ALPHA_SEL (1 << 1)
> >> > >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> >> > >>
> >> > >> @@ -395,9 +436,19 @@
> >> > >>
> >> > >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> > >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >> > >>
> >> > >> +/* Clock gate mode control */
> >> > >> +#define REG_CLKGATE_MODE (0x1b0)
> >> > >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> >> > >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> >> > >> +
> >> > >>
> >> > >> /* Blending equation control */
> >> > >> #define BLENDCON (0x260)
> >> > >> #define BLENDCON_NEW_MASK (1 << 0)
> >> > >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> > >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >> > >>
> >> > >> +/* Window alpha control */
> >> > >> +#define VIDW0ALPHA0 (0x200)
> >> > >> +#define VIDW0ALPHA1 (0x204)
> >> > >> +#define DPCLKCON (0x27c)
> >> > >> +#define DPCLKCON_ENABLE (1 << 1)
> >> > >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> >> > >> index 0217f74..f81bf55 100644
> >> > >> --- a/drivers/video/Kconfig
> >> > >> +++ b/drivers/video/Kconfig
> >> > >> @@ -2053,6 +2053,12 @@ config FB_S3C
> >> > >>
> >> > >> Currently the support is only for the S3C6400 and S3C6410
> >> > >> SoCs.
> >> > >>
> >> > >> +config FB_EXYNOS_FIMD_V8
> >> > >> + bool "register extensions for FIMD version 8"
> >> > >> + depends on ARCH_EXYNOS5
> >> > >> + ---help---
> >> > >> + This uses register extensions for FIMD version 8
> >> > >> +
> >> > >>
> >> > >> config FB_S3C_DEBUG_REGWRITE
> >> > >>
> >> > >> bool "Debug register writes"
> >> > >> depends on FB_S3C
> >> > >
> >> > > Best regards,
> >> > > Tomasz Figa
> >> > >
> >> > > --
> >> > > To unsubscribe from this list: send the line "unsubscribe
> >> > > linux-samsung-soc" in the body of a message to
> >> > > majordomo@vger.kernel.org
> >> > > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 9:49 ` Tomasz Figa
0 siblings, 0 replies; 84+ messages in thread
From: Tomasz Figa @ 2012-07-20 9:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Friday 20 of July 2012 08:29:21 Leela Krishna Amudala wrote:
> On Fri, Jul 20, 2012 at 7:51 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Thursday, July 19, 2012 10:35 PM, Tomasz Figa wrote:
> >> Hi Leela,
> >>
> >> On Thursday 19 of July 2012 18:30:44 Leela Krishna Amudala wrote:
> >> > Hi Tomasz,
> >> >
> >> > On Wed, Jul 18, 2012 at 4:35 PM, Tomasz Figa <tomasz.figa@gmail.com>
> >>
> >> wrote:
> >> > > Hi,
> >> > >
> >> > > On Wednesday 18 of July 2012 11:27:27 Leela Krishna Amudala wrote:
> >> > >> This patch updates the register address offsets and adds SFR
> >> > >> definitions
> >> > >> for writeback for Samsung's V8 display controller.
> >> > >>
> >> > >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> > >> ---
> >> > >>
> >> > >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++
> >> > >> arch/arm/plat-samsung/include/plat/regs-fb.h | 51
> >> > >>
> >> > >> +++++++++++++++++++++++ drivers/video/Kconfig
> >> > >>
> >> > >> | 6 +++
> >> > >>
> >> > >> 3 files changed, 67 insertions(+), 0 deletions(-)
> >> > >>
> >> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> > >> b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index
> >> > >> 4c3647f..1639c17
> >> > >> 100644
> >> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> > >> @@ -30,9 +30,16 @@
> >> > >>
> >> > >> #define VIDCON1_FSTATUS_EVEN (1 << 15)
> >> > >>
> >> > >> /* Video timing controls */
> >> > >>
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDTCON0 (0x20010)
> >> > >> +#define VIDTCON1 (0x20014)
> >> > >> +#define VIDTCON3 (0x2001C)
> >> > >> +#else
> >> > >>
> >> > >> #define VIDTCON0 (0x10)
> >> > >> #define VIDTCON1 (0x14)
> >> > >> #define VIDTCON2 (0x18)
> >> > >>
> >> > >> +#define VIDTCON3 (0x1C)
> >> > >> +#endif
> >> > >
> >> > > Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> >> > > CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform
> >> > > ARM
> >> > > kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> >> > > kernel)?
> >> >
> >> > Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> >> > As address offsets for certain registers has changed in FIMD_V8, we
> >> > introduced these defines.
> >> > So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5
> >> > SoC,
> >> > and deselect for other SoCs.
> >>
> >> Yes, I'm aware of different FIMD versions in different SoCs. My point
> >> is
> >> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
> >> support other SoCs than Exynos5, i.e. additional config options should
> >> be incremental - should not break other setups. Ideally there should
> >> not be any new config option for FIMD v8.
> >>
> >> The detection of FIMD version and selection of appropriate register
> >> offsets should be done in the driver at runtime, based for example on
> >> platform_device_id (see the s3c-fb driver and usage of
> >> s3c_fb_driverdata
> >> and s3c_fb_win_variant structs).
> >
> > I could not agree with Tomasz Figa more.
> > FIMD register offset should be selected at runtime.
> >
> > Leela Krishna Amudala,
> > Please, don't use ugly "#ifdef".
> >
> > Best regards,
> > Jingoo Han
>
> Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
> exynos5_defconfig etc.,)
> So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
> it won't affect the other SoCs.
>
> Best Wishes,
> Leela Krishna Amudala.
Defconfig is only used to build a kernel image for a single machine.
Let me give you another example. Consider that we want to build a single
kernel binary running on all Exynos SocS (this is what ARM Linux is
currently aiming at). What we do is enabling in config support for every
bit of every SoC we want to support in resulting kernel binary. Now with
your patch to support Exynos 5 in such kernel we would have to enable
CONFIG_FB_EXYNOS_FIMD_V8 to get support for FIMD on Exynos 5 leading to a
situation where we could have support for all Exynos SoCs in one kernel,
but, depending on one config option, either without FIMD support on Exynos
5 or on any older SoC.
Best regards,
Tom
> >> Best regards,
> >> Tomasz Figa
> >>
> >> > >> /* Window position controls */
> >> > >>
> >> > >> @@ -43,9 +50,12 @@
> >> > >>
> >> > >> #define VIDOSD_BASE (0x40)
> >> > >>
> >> > >> #define VIDINTCON0 (0x130)
> >> > >>
> >> > >> +#define VIDINTCON1 (0x134)
> >> > >>
> >> > >> /* WINCONx */
> >> > >>
> >> > >> +#define WINCONx_CSC_CON_EQ709 (1 << 28)
> >> > >> +#define WINCONx_CSC_CON_EQ601 (0 << 28)
> >> > >>
> >> > >> #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> > >> #define WINCONx_CSCWIDTH_SHIFT (26)
> >> > >> #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >> > >>
> >> > >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> > >> b/arch/arm/plat-samsung/include/plat/regs-fb.h index
> >> > >> 9a78012..6d2ee16
> >> > >> 100644
> >> > >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> > >> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> > >> @@ -32,12 +32,28 @@
> >> > >>
> >> > >> #define VIDCON0 (0x00)
> >> > >> #define VIDCON0_INTERLACE (1 << 29)
> >> > >>
> >> > >> +
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDOUT_CON (0x20000)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16)
> >> > >> +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_SHIFT (8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8)
> >> > >> +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8)
> >> > >> +#endif
> >> > >> +
> >> > >>
> >> > >> #define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> > >> #define VIDCON0_VIDOUT_SHIFT (26)
> >> > >> #define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> > >> #define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> > >> #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> > >> #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >> > >>
> >> > >> +#define VIDCON0_VIDOUT_WB (0x4 << 26)
> >> > >>
> >> > >> #define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> > >> #define VIDCON0_L1_DATA_SHIFT (23)
> >> > >>
> >> > >> @@ -81,7 +97,13 @@
> >> > >>
> >> > >> #define VIDCON0_ENVID (1 << 1)
> >> > >> #define VIDCON0_ENVID_F (1 << 0)
> >> > >>
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDOUT_CON (0x20000)
> >> > >> +#define VIDCON1 (0x20004)
> >> > >> +#else
> >> > >>
> >> > >> #define VIDCON1 (0x04)
> >> > >>
> >> > >> +#endif
> >> > >
> >> > > Same here. Also isn't it a redefinition of VIDOUT_CON that was
> >> > > defined
> >> > > several lines above?
> >> >
> >> > Will be corrected in the next version patch set.
> >> >
> >> > Best Wishes,
> >> > Leela Krishna Amudala.
> >> >
> >> > >> #define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> > >> #define VIDCON1_LINECNT_SHIFT (16)
> >> > >> #define VIDCON1_LINECNT_GET(_v) (((_v) >>
> >> > >> 16) &
> >> > >> 0x7ff)>>
> >> > >>
> >> > >> @@ -111,6 +133,14 @@
> >> > >>
> >> > >> #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> > >> #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> > >> #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> > >>
> >> > >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> > >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> > >> +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
> >> > >> +
> >> > >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> > >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> > >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> > >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> > >>
> >> > >> #define VIDCON2_ORGYCbCr (1 << 8)
> >> > >> #define VIDCON2_YUVORDCrCb (1 << 7)
> >> > >>
> >> > >> @@ -165,8 +195,15 @@
> >> > >>
> >> > >> #define VIDTCON1_HSPW_SHIFT (0)
> >> > >> #define VIDTCON1_HSPW_LIMIT (0xff)
> >> > >> #define VIDTCON1_HSPW(_x) ((_x) << 0)
> >> > >>
> >> > >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> > >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> > >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >> > >>
> >> > >> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >> > >> +#define VIDTCON2 (0x20018)
> >> > >> +#else
> >> > >>
> >> > >> #define VIDTCON2 (0x18)
> >> > >>
> >> > >> +#endif
> >> > >
> >> > > Same as in my first comment.
> >> > >
> >> > >> #define VIDTCON2_LINEVAL_E(_x) ((((_x) &
> >> > >> 0x800)
> >> > >>
> >> > >> >> 11) << 23) #define VIDTCON2_LINEVAL_MASK
> >> > >>
> >> > >> (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT
> >> > >> (11)
> >> > >>
> >> > >> @@ -186,6 +223,9 @@
> >> > >>
> >> > >> #define WINCONx_BYTSWP (1 << 17)
> >> > >> #define WINCONx_HAWSWP (1 << 16)
> >> > >> #define WINCONx_WSWP (1 << 15)
> >> > >>
> >> > >> +#define WINCONx_ENLOCAL_MASK (0xf << 15)
> >> > >> +#define WINCONx_INRGB_RGB (0 << 13)
> >> > >> +#define WINCONx_INRGB_YCBCR (1 << 13)
> >> > >>
> >> > >> #define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> > >> #define WINCONx_BURSTLEN_SHIFT (9)
> >> > >> #define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >> > >>
> >> > >> @@ -205,6 +245,7 @@
> >> > >>
> >> > >> #define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >> > >>
> >> > >> #define WINCON1_BLD_PIX (1 << 6)
> >> > >>
> >> > >> +#define WINCON1_BLD_PLANE (0 << 6)
> >> > >>
> >> > >> #define WINCON1_ALPHA_SEL (1 << 1)
> >> > >> #define WINCON1_BPPMODE_MASK (0xf << 2)
> >> > >>
> >> > >> @@ -395,9 +436,19 @@
> >> > >>
> >> > >> #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> > >> #define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >> > >>
> >> > >> +/* Clock gate mode control */
> >> > >> +#define REG_CLKGATE_MODE (0x1b0)
> >> > >> +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0)
> >> > >> +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0)
> >> > >> +
> >> > >>
> >> > >> /* Blending equation control */
> >> > >> #define BLENDCON (0x260)
> >> > >> #define BLENDCON_NEW_MASK (1 << 0)
> >> > >> #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> > >> #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >> > >>
> >> > >> +/* Window alpha control */
> >> > >> +#define VIDW0ALPHA0 (0x200)
> >> > >> +#define VIDW0ALPHA1 (0x204)
> >> > >> +#define DPCLKCON (0x27c)
> >> > >> +#define DPCLKCON_ENABLE (1 << 1)
> >> > >> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> >> > >> index 0217f74..f81bf55 100644
> >> > >> --- a/drivers/video/Kconfig
> >> > >> +++ b/drivers/video/Kconfig
> >> > >> @@ -2053,6 +2053,12 @@ config FB_S3C
> >> > >>
> >> > >> Currently the support is only for the S3C6400 and S3C6410
> >> > >> SoCs.
> >> > >>
> >> > >> +config FB_EXYNOS_FIMD_V8
> >> > >> + bool "register extensions for FIMD version 8"
> >> > >> + depends on ARCH_EXYNOS5
> >> > >> + ---help---
> >> > >> + This uses register extensions for FIMD version 8
> >> > >> +
> >> > >>
> >> > >> config FB_S3C_DEBUG_REGWRITE
> >> > >>
> >> > >> bool "Debug register writes"
> >> > >> depends on FB_S3C
> >> > >
> >> > > Best regards,
> >> > > Tomasz Figa
> >> > >
> >> > > --
> >> > > To unsubscribe from this list: send the line "unsubscribe
> >> > > linux-samsung-soc" in the body of a message to
> >> > > majordomo at vger.kernel.org
> >> > > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss at lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-20 2:59 ` Leela Krishna Amudala
@ 2012-07-20 10:00 ` Sylwester Nawrocki
-1 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-20 10:00 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: Jingoo Han, Tomasz Figa, linux-samsung-soc, devicetree-discuss,
joshi, thomas.ab, kgene.kim, olofj, linux-arm-kernel
On 07/20/2012 04:59 AM, Leela Krishna Amudala wrote:
>>>>>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>> @@ -30,9 +30,16 @@
>>>>>>
>>>>>> #define VIDCON1_FSTATUS_EVEN (1<< 15)
>>>>>>
>>>>>> /* Video timing controls */
>>>>>>
>>>>>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>>>>>> +#define VIDTCON0 (0x20010)
>>>>>> +#define VIDTCON1 (0x20014)
>>>>>> +#define VIDTCON3 (0x2001C)
>>>>>> +#else
>>>>>>
>>>>>> #define VIDTCON0 (0x10)
>>>>>> #define VIDTCON1 (0x14)
>>>>>> #define VIDTCON2 (0x18)
>>>>>>
>>>>>> +#define VIDTCON3 (0x1C)
>>>>>> +#endif
>>>>>
>>>>> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
>>>>> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
>>>>> kernels, aren't we (i.e support of both V8 and earlier FIMD in one
>>>>> kernel)?
>>>> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
>>>> As address offsets for certain registers has changed in FIMD_V8, we
>>>> introduced these defines.
>>>> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
>>>> and deselect for other SoCs.
>>>
>>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
>>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
>>> support other SoCs than Exynos5, i.e. additional config options should be
>>> incremental - should not break other setups. Ideally there should not be
>>> any new config option for FIMD v8.
>>>
>>> The detection of FIMD version and selection of appropriate register offsets
>>> should be done in the driver at runtime, based for example on
>>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
>>> and s3c_fb_win_variant structs).
>>
>> I could not agree with Tomasz Figa more.
>> FIMD register offset should be selected at runtime.
>>
>> Leela Krishna Amudala,
>> Please, don't use ugly "#ifdef".
>>
>> Best regards,
>> Jingoo Han
>>
>
> Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
> exynos5_defconfig etc.,)
> So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
> it won't affect the other SoCs.
NACK.
As others explained, and you don't seem to understand or you are stubborn
enough not to change your approach, resolving hardware differences at
compile time only is not acceptable, especially that Exynos SoCs are
going to be DT only platforms. We shouldn't be short-sighted like this.
Especially that the problem is relatively easy to solve at run-time, just
add EXYNOS5_* register address definitions and create separate functions
at the driver(s) touching those registers that changed on Exynos5.
Or parametrize existing ones with an offset that would be stored in driver
data passed trough struct platform_device_id::driver_data.
@Jingoo: BTW, shouldn't we have
plat-samsung/include/plat/regs-fb.h
plat-samsung/include/plat/regs-fb-v4.h
merged into one file and moved under include/video/ ?
For example include/video/s3c-fb.h, and board files could also include
that header. We have FIMD variant structures anyway, so why do we still
need multiple headers ?
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 10:00 ` Sylwester Nawrocki
0 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-20 10:00 UTC (permalink / raw)
To: linux-arm-kernel
On 07/20/2012 04:59 AM, Leela Krishna Amudala wrote:
>>>>>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>> @@ -30,9 +30,16 @@
>>>>>>
>>>>>> #define VIDCON1_FSTATUS_EVEN (1<< 15)
>>>>>>
>>>>>> /* Video timing controls */
>>>>>>
>>>>>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>>>>>> +#define VIDTCON0 (0x20010)
>>>>>> +#define VIDTCON1 (0x20014)
>>>>>> +#define VIDTCON3 (0x2001C)
>>>>>> +#else
>>>>>>
>>>>>> #define VIDTCON0 (0x10)
>>>>>> #define VIDTCON1 (0x14)
>>>>>> #define VIDTCON2 (0x18)
>>>>>>
>>>>>> +#define VIDTCON3 (0x1C)
>>>>>> +#endif
>>>>>
>>>>> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
>>>>> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
>>>>> kernels, aren't we (i.e support of both V8 and earlier FIMD in one
>>>>> kernel)?
>>>> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
>>>> As address offsets for certain registers has changed in FIMD_V8, we
>>>> introduced these defines.
>>>> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
>>>> and deselect for other SoCs.
>>>
>>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
>>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
>>> support other SoCs than Exynos5, i.e. additional config options should be
>>> incremental - should not break other setups. Ideally there should not be
>>> any new config option for FIMD v8.
>>>
>>> The detection of FIMD version and selection of appropriate register offsets
>>> should be done in the driver at runtime, based for example on
>>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
>>> and s3c_fb_win_variant structs).
>>
>> I could not agree with Tomasz Figa more.
>> FIMD register offset should be selected at runtime.
>>
>> Leela Krishna Amudala,
>> Please, don't use ugly "#ifdef".
>>
>> Best regards,
>> Jingoo Han
>>
>
> Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
> exynos5_defconfig etc.,)
> So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
> it won't affect the other SoCs.
NACK.
As others explained, and you don't seem to understand or you are stubborn
enough not to change your approach, resolving hardware differences at
compile time only is not acceptable, especially that Exynos SoCs are
going to be DT only platforms. We shouldn't be short-sighted like this.
Especially that the problem is relatively easy to solve at run-time, just
add EXYNOS5_* register address definitions and create separate functions
at the driver(s) touching those registers that changed on Exynos5.
Or parametrize existing ones with an offset that would be stored in driver
data passed trough struct platform_device_id::driver_data.
@Jingoo: BTW, shouldn't we have
plat-samsung/include/plat/regs-fb.h
plat-samsung/include/plat/regs-fb-v4.h
merged into one file and moved under include/video/ ?
For example include/video/s3c-fb.h, and board files could also include
that header. We have FIMD variant structures anyway, so why do we still
need multiple headers ?
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-20 10:00 ` Sylwester Nawrocki
@ 2012-07-20 11:07 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-20 11:07 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Jingoo Han, Tomasz Figa, linux-samsung-soc, devicetree-discuss,
joshi, thomas.ab, kgene.kim, olofj, linux-arm-kernel
Hello,
On Fri, Jul 20, 2012 at 3:30 PM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> On 07/20/2012 04:59 AM, Leela Krishna Amudala wrote:
>>>>>>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>>> @@ -30,9 +30,16 @@
>>>>>>>
>>>>>>> #define VIDCON1_FSTATUS_EVEN (1<< 15)
>>>>>>>
>>>>>>> /* Video timing controls */
>>>>>>>
>>>>>>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>>>>>>> +#define VIDTCON0 (0x20010)
>>>>>>> +#define VIDTCON1 (0x20014)
>>>>>>> +#define VIDTCON3 (0x2001C)
>>>>>>> +#else
>>>>>>>
>>>>>>> #define VIDTCON0 (0x10)
>>>>>>> #define VIDTCON1 (0x14)
>>>>>>> #define VIDTCON2 (0x18)
>>>>>>>
>>>>>>> +#define VIDTCON3 (0x1C)
>>>>>>> +#endif
>>>>>>
>>>>>> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
>>>>>> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
>>>>>> kernels, aren't we (i.e support of both V8 and earlier FIMD in one
>>>>>> kernel)?
>>>>> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
>>>>> As address offsets for certain registers has changed in FIMD_V8, we
>>>>> introduced these defines.
>>>>> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
>>>>> and deselect for other SoCs.
>>>>
>>>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
>>>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
>>>> support other SoCs than Exynos5, i.e. additional config options should be
>>>> incremental - should not break other setups. Ideally there should not be
>>>> any new config option for FIMD v8.
>>>>
>>>> The detection of FIMD version and selection of appropriate register offsets
>>>> should be done in the driver at runtime, based for example on
>>>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
>>>> and s3c_fb_win_variant structs).
>>>
>>> I could not agree with Tomasz Figa more.
>>> FIMD register offset should be selected at runtime.
>>>
>>> Leela Krishna Amudala,
>>> Please, don't use ugly "#ifdef".
>>>
>>> Best regards,
>>> Jingoo Han
>>>
>>
>> Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
>> exynos5_defconfig etc.,)
>> So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
>> it won't affect the other SoCs.
>
> NACK.
>
> As others explained, and you don't seem to understand or you are stubborn
> enough not to change your approach, resolving hardware differences at
> compile time only is not acceptable, especially that Exynos SoCs are
> going to be DT only platforms. We shouldn't be short-sighted like this.
>
> Especially that the problem is relatively easy to solve at run-time, just
> add EXYNOS5_* register address definitions and create separate functions
> at the driver(s) touching those registers that changed on Exynos5.
>
> Or parametrize existing ones with an offset that would be stored in driver
> data passed trough struct platform_device_id::driver_data.
>
> @Jingoo: BTW, shouldn't we have
>
> plat-samsung/include/plat/regs-fb.h
> plat-samsung/include/plat/regs-fb-v4.h
>
> merged into one file and moved under include/video/ ?
>
> For example include/video/s3c-fb.h, and board files could also include
> that header. We have FIMD variant structures anyway, so why do we still
> need multiple headers ?
>
Will do the run-time approach, and post the next version patchset soon.
Thanks,
Leela Krishna Amudala
> --
>
> Regards,
> Sylwester
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-20 11:07 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-20 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Fri, Jul 20, 2012 at 3:30 PM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> On 07/20/2012 04:59 AM, Leela Krishna Amudala wrote:
>>>>>>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>>>> @@ -30,9 +30,16 @@
>>>>>>>
>>>>>>> #define VIDCON1_FSTATUS_EVEN (1<< 15)
>>>>>>>
>>>>>>> /* Video timing controls */
>>>>>>>
>>>>>>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
>>>>>>> +#define VIDTCON0 (0x20010)
>>>>>>> +#define VIDTCON1 (0x20014)
>>>>>>> +#define VIDTCON3 (0x2001C)
>>>>>>> +#else
>>>>>>>
>>>>>>> #define VIDTCON0 (0x10)
>>>>>>> #define VIDTCON1 (0x14)
>>>>>>> #define VIDTCON2 (0x18)
>>>>>>>
>>>>>>> +#define VIDTCON3 (0x1C)
>>>>>>> +#endif
>>>>>>
>>>>>> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
>>>>>> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
>>>>>> kernels, aren't we (i.e support of both V8 and earlier FIMD in one
>>>>>> kernel)?
>>>>> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
>>>>> As address offsets for certain registers has changed in FIMD_V8, we
>>>>> introduced these defines.
>>>>> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
>>>>> and deselect for other SoCs.
>>>>
>>>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
>>>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
>>>> support other SoCs than Exynos5, i.e. additional config options should be
>>>> incremental - should not break other setups. Ideally there should not be
>>>> any new config option for FIMD v8.
>>>>
>>>> The detection of FIMD version and selection of appropriate register offsets
>>>> should be done in the driver at runtime, based for example on
>>>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
>>>> and s3c_fb_win_variant structs).
>>>
>>> I could not agree with Tomasz Figa more.
>>> FIMD register offset should be selected at runtime.
>>>
>>> Leela Krishna Amudala,
>>> Please, don't use ugly "#ifdef".
>>>
>>> Best regards,
>>> Jingoo Han
>>>
>>
>> Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
>> exynos5_defconfig etc.,)
>> So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
>> it won't affect the other SoCs.
>
> NACK.
>
> As others explained, and you don't seem to understand or you are stubborn
> enough not to change your approach, resolving hardware differences at
> compile time only is not acceptable, especially that Exynos SoCs are
> going to be DT only platforms. We shouldn't be short-sighted like this.
>
> Especially that the problem is relatively easy to solve at run-time, just
> add EXYNOS5_* register address definitions and create separate functions
> at the driver(s) touching those registers that changed on Exynos5.
>
> Or parametrize existing ones with an offset that would be stored in driver
> data passed trough struct platform_device_id::driver_data.
>
> @Jingoo: BTW, shouldn't we have
>
> plat-samsung/include/plat/regs-fb.h
> plat-samsung/include/plat/regs-fb-v4.h
>
> merged into one file and moved under include/video/ ?
>
> For example include/video/s3c-fb.h, and board files could also include
> that header. We have FIMD variant structures anyway, so why do we still
> need multiple headers ?
>
Will do the run-time approach, and post the next version patchset soon.
Thanks,
Leela Krishna Amudala
> --
>
> Regards,
> Sylwester
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-20 11:07 ` Leela Krishna Amudala
@ 2012-07-20 12:54 ` Sylwester Nawrocki
-1 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-20 12:54 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: Jingoo Han, Tomasz Figa, linux-samsung-soc, devicetree-discuss,
joshi, thomas.ab, kgene.kim, olofj, linux-arm-kernel
On 07/20/2012 01:07 PM, Leela Krishna Amudala wrote:
> Will do the run-time approach, and post the next version patchset soon.
Great, thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
2012-07-20 10:00 ` Sylwester Nawrocki
@ 2012-07-22 22:35 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-22 22:35 UTC (permalink / raw)
To: 'Sylwester Nawrocki', 'Leela Krishna Amudala'
Cc: 'Tomasz Figa',
linux-samsung-soc, devicetree-discuss, joshi, thomas.ab,
kgene.kim, olofj, linux-arm-kernel, 'Jingoo Han'
On Friday, July 20, 2012 7:00 PM, Sylwester Nawrocki wrote:
>
> On 07/20/2012 04:59 AM, Leela Krishna Amudala wrote:
> >>>>>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>>>>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>>>>> @@ -30,9 +30,16 @@
> >>>>>>
> >>>>>> #define VIDCON1_FSTATUS_EVEN (1<< 15)
> >>>>>>
> >>>>>> /* Video timing controls */
> >>>>>>
> >>>>>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >>>>>> +#define VIDTCON0 (0x20010)
> >>>>>> +#define VIDTCON1 (0x20014)
> >>>>>> +#define VIDTCON3 (0x2001C)
> >>>>>> +#else
> >>>>>>
> >>>>>> #define VIDTCON0 (0x10)
> >>>>>> #define VIDTCON1 (0x14)
> >>>>>> #define VIDTCON2 (0x18)
> >>>>>>
> >>>>>> +#define VIDTCON3 (0x1C)
> >>>>>> +#endif
> >>>>>
> >>>>> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> >>>>> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> >>>>> kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> >>>>> kernel)?
> >>>> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> >>>> As address offsets for certain registers has changed in FIMD_V8, we
> >>>> introduced these defines.
> >>>> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
> >>>> and deselect for other SoCs.
> >>>
> >>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
> >>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
> >>> support other SoCs than Exynos5, i.e. additional config options should be
> >>> incremental - should not break other setups. Ideally there should not be
> >>> any new config option for FIMD v8.
> >>>
> >>> The detection of FIMD version and selection of appropriate register offsets
> >>> should be done in the driver at runtime, based for example on
> >>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
> >>> and s3c_fb_win_variant structs).
> >>
> >> I could not agree with Tomasz Figa more.
> >> FIMD register offset should be selected at runtime.
> >>
> >> Leela Krishna Amudala,
> >> Please, don't use ugly "#ifdef".
> >>
> >> Best regards,
> >> Jingoo Han
> >>
> >
> > Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
> > exynos5_defconfig etc.,)
> > So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
> > it won't affect the other SoCs.
>
> NACK.
>
> As others explained, and you don't seem to understand or you are stubborn
> enough not to change your approach, resolving hardware differences at
> compile time only is not acceptable, especially that Exynos SoCs are
> going to be DT only platforms. We shouldn't be short-sighted like this.
>
> Especially that the problem is relatively easy to solve at run-time, just
> add EXYNOS5_* register address definitions and create separate functions
> at the driver(s) touching those registers that changed on Exynos5.
>
> Or parametrize existing ones with an offset that would be stored in driver
> data passed trough struct platform_device_id::driver_data.
>
> @Jingoo: BTW, shouldn't we have
>
> plat-samsung/include/plat/regs-fb.h
> plat-samsung/include/plat/regs-fb-v4.h
>
> merged into one file and moved under include/video/ ?
Yes, you're right.
I think that these files need to be merged to one file.
Also, 'include/video/' seems to be good.
>
> For example include/video/s3c-fb.h, and board files could also include
> that header. We have FIMD variant structures anyway, so why do we still
> need multiple headers ?
>
> --
>
> Regards,
> Sylwester
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback
@ 2012-07-22 22:35 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-22 22:35 UTC (permalink / raw)
To: linux-arm-kernel
On Friday, July 20, 2012 7:00 PM, Sylwester Nawrocki wrote:
>
> On 07/20/2012 04:59 AM, Leela Krishna Amudala wrote:
> >>>>>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>>>>> +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>>>>> @@ -30,9 +30,16 @@
> >>>>>>
> >>>>>> #define VIDCON1_FSTATUS_EVEN (1<< 15)
> >>>>>>
> >>>>>> /* Video timing controls */
> >>>>>>
> >>>>>> +#ifdef CONFIG_FB_EXYNOS_FIMD_V8
> >>>>>> +#define VIDTCON0 (0x20010)
> >>>>>> +#define VIDTCON1 (0x20014)
> >>>>>> +#define VIDTCON3 (0x2001C)
> >>>>>> +#else
> >>>>>>
> >>>>>> #define VIDTCON0 (0x10)
> >>>>>> #define VIDTCON1 (0x14)
> >>>>>> #define VIDTCON2 (0x18)
> >>>>>>
> >>>>>> +#define VIDTCON3 (0x1C)
> >>>>>> +#endif
> >>>>>
> >>>>> Wouldn't it break s3c-fb on SoCs with earlier FIMD versions with
> >>>>> CONFIG_FB_EXYNOS_FIMD_V8 selected? We are aiming at multi-platform ARM
> >>>>> kernels, aren't we (i.e support of both V8 and earlier FIMD in one
> >>>>> kernel)?
> >>>> Exynos5 has FIMD_V8 and other SoCs has older FIMD versions.
> >>>> As address offsets for certain registers has changed in FIMD_V8, we
> >>>> introduced these defines.
> >>>> So we have to select CONFIG_FB_EXYNOS_FIMD_V8 in case of Exynos5 SoC,
> >>>> and deselect for other SoCs.
> >>>
> >>> Yes, I'm aware of different FIMD versions in different SoCs. My point is
> >>> that it shouldn't be necessary to deselect CONFIG_FB_EXYNOS_FIMD_V8 to
> >>> support other SoCs than Exynos5, i.e. additional config options should be
> >>> incremental - should not break other setups. Ideally there should not be
> >>> any new config option for FIMD v8.
> >>>
> >>> The detection of FIMD version and selection of appropriate register offsets
> >>> should be done in the driver at runtime, based for example on
> >>> platform_device_id (see the s3c-fb driver and usage of s3c_fb_driverdata
> >>> and s3c_fb_win_variant structs).
> >>
> >> I could not agree with Tomasz Figa more.
> >> FIMD register offset should be selected at runtime.
> >>
> >> Leela Krishna Amudala,
> >> Please, don't use ugly "#ifdef".
> >>
> >> Best regards,
> >> Jingoo Han
> >>
> >
> > Yes, Each SoC having its own defconfigs (eg: exynos4_defconfig,
> > exynos5_defconfig etc.,)
> > So, CONFIG_FB_EXYNOS_FIMD_V8 will be added into exynos5_defconfig and
> > it won't affect the other SoCs.
>
> NACK.
>
> As others explained, and you don't seem to understand or you are stubborn
> enough not to change your approach, resolving hardware differences at
> compile time only is not acceptable, especially that Exynos SoCs are
> going to be DT only platforms. We shouldn't be short-sighted like this.
>
> Especially that the problem is relatively easy to solve at run-time, just
> add EXYNOS5_* register address definitions and create separate functions
> at the driver(s) touching those registers that changed on Exynos5.
>
> Or parametrize existing ones with an offset that would be stored in driver
> data passed trough struct platform_device_id::driver_data.
>
> @Jingoo: BTW, shouldn't we have
>
> plat-samsung/include/plat/regs-fb.h
> plat-samsung/include/plat/regs-fb-v4.h
>
> merged into one file and moved under include/video/ ?
Yes, you're right.
I think that these files need to be merged to one file.
Also, 'include/video/' seems to be good.
>
> For example include/video/s3c-fb.h, and board files could also include
> that header. We have FIMD variant structures anyway, so why do we still
> need multiple headers ?
>
> --
>
> Regards,
> Sylwester
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 2/7] ARM: EXYNOS5: add machine specific support for backlight
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
Adds machine specific support for LCD backlight for SMDK board based
on Exynos5
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e698ca0..f0f41b7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -416,6 +416,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select SAMSUNG_DEV_BACKLIGHT
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..e7113cc 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,8 @@
#include <linux/of_platform.h>
#include <linux/serial_core.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
@@ -18,9 +20,33 @@
#include <plat/cpu.h>
#include <plat/regs-serial.h>
+#include <plat/backlight.h>
+#include <plat/gpio-cfg.h>
#include "common.h"
+static int smdk5250_bl_notify(struct device *unused, int brightness)
+{
+ /* manage lcd_bl_en signal */
+ if (brightness)
+ gpio_set_value(EXYNOS5_GPX3(0), 1);
+ else
+ gpio_set_value(EXYNOS5_GPX3(0), 0);
+
+ return brightness;
+}
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
+ .no = EXYNOS5_GPB2(0),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk5250_bl_data = {
+ .pwm_period_ns = 1000000,
+ .notify = smdk5250_bl_notify,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -67,6 +93,7 @@ static void __init exynos5250_dt_map_io(void)
static void __init exynos5250_dt_machine_init(void)
{
+ samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 2/7] ARM: EXYNOS5: add machine specific support for backlight
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
Adds machine specific support for LCD backlight for SMDK board based
on Exynos5
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e698ca0..f0f41b7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -416,6 +416,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select SAMSUNG_DEV_BACKLIGHT
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..e7113cc 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,8 @@
#include <linux/of_platform.h>
#include <linux/serial_core.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
@@ -18,9 +20,33 @@
#include <plat/cpu.h>
#include <plat/regs-serial.h>
+#include <plat/backlight.h>
+#include <plat/gpio-cfg.h>
#include "common.h"
+static int smdk5250_bl_notify(struct device *unused, int brightness)
+{
+ /* manage lcd_bl_en signal */
+ if (brightness)
+ gpio_set_value(EXYNOS5_GPX3(0), 1);
+ else
+ gpio_set_value(EXYNOS5_GPX3(0), 0);
+
+ return brightness;
+}
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
+ .no = EXYNOS5_GPB2(0),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk5250_bl_data = {
+ .pwm_period_ns = 1000000,
+ .notify = smdk5250_bl_notify,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -67,6 +93,7 @@ static void __init exynos5250_dt_map_io(void)
static void __init exynos5250_dt_machine_init(void)
{
+ samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread
* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
This patch adds machine specific support for LCD controller like setting power to LCD
and adding LCD platform device.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e7113cc..02a0e68 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -13,6 +13,7 @@
#include <linux/serial_core.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
+#include <linux/delay.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
@@ -24,6 +25,7 @@
#include <plat/gpio-cfg.h>
#include "common.h"
+#include <video/platform_lcd.h>
static int smdk5250_bl_notify(struct device *unused, int brightness)
{
@@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
.notify = smdk5250_bl_notify,
};
+static void lcd_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+
+ /* reset */
+ gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
+
+ mdelay(20);
+ if (power) {
+ /* fire nRESET on power up */
+ gpio_set_value(EXYNOS5_GPX1(5), 0);
+ mdelay(20);
+ gpio_set_value(EXYNOS5_GPX1(5), 1);
+ mdelay(20);
+ gpio_free(EXYNOS5_GPX1(5));
+ } else {
+ /* fire nRESET on power off */
+ gpio_set_value(EXYNOS5_GPX1(5), 0);
+ mdelay(20);
+ gpio_set_value(EXYNOS5_GPX1(5), 1);
+ mdelay(20);
+ gpio_free(EXYNOS5_GPX1(5));
+ }
+ mdelay(20);
+
+ /*
+ * Request lcd_bl_en GPIO for smdk5250_bl_notify().
+ * TODO: Fix this so we are not at risk of requesting the GPIO
+ * multiple times, this should be done with device tree, and
+ * likely integrated into the plat-samsung/dev-backlight.c init.
+ */
+ gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
+}
+
+static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
+{
+ /* Don't call .set_power callback while unblanking */
+ return 0;
+}
+
+static struct plat_lcd_data smdk5250_lcd_data = {
+ .set_power = lcd_set_power,
+ .match_fb = smdk5250_match_fb,
+};
+
+static struct platform_device smdk5250_lcd = {
+ .name = "platform-lcd",
+ .dev.platform_data = &smdk5250_lcd_data,
+};
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
{},
};
+static struct platform_device *smdk5250_devices[] __initdata = {
+ &smdk5250_lcd, /* for platform_lcd device */
+};
+
static void __init exynos5250_dt_map_io(void)
{
exynos_init_io(NULL, 0);
@@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+ platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
}
static char const *exynos5250_dt_compat[] __initdata = {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds machine specific support for LCD controller like setting power to LCD
and adding LCD platform device.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e7113cc..02a0e68 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -13,6 +13,7 @@
#include <linux/serial_core.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
+#include <linux/delay.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
@@ -24,6 +25,7 @@
#include <plat/gpio-cfg.h>
#include "common.h"
+#include <video/platform_lcd.h>
static int smdk5250_bl_notify(struct device *unused, int brightness)
{
@@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
.notify = smdk5250_bl_notify,
};
+static void lcd_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+
+ /* reset */
+ gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
+
+ mdelay(20);
+ if (power) {
+ /* fire nRESET on power up */
+ gpio_set_value(EXYNOS5_GPX1(5), 0);
+ mdelay(20);
+ gpio_set_value(EXYNOS5_GPX1(5), 1);
+ mdelay(20);
+ gpio_free(EXYNOS5_GPX1(5));
+ } else {
+ /* fire nRESET on power off */
+ gpio_set_value(EXYNOS5_GPX1(5), 0);
+ mdelay(20);
+ gpio_set_value(EXYNOS5_GPX1(5), 1);
+ mdelay(20);
+ gpio_free(EXYNOS5_GPX1(5));
+ }
+ mdelay(20);
+
+ /*
+ * Request lcd_bl_en GPIO for smdk5250_bl_notify().
+ * TODO: Fix this so we are not at risk of requesting the GPIO
+ * multiple times, this should be done with device tree, and
+ * likely integrated into the plat-samsung/dev-backlight.c init.
+ */
+ gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
+}
+
+static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
+{
+ /* Don't call .set_power callback while unblanking */
+ return 0;
+}
+
+static struct plat_lcd_data smdk5250_lcd_data = {
+ .set_power = lcd_set_power,
+ .match_fb = smdk5250_match_fb,
+};
+
+static struct platform_device smdk5250_lcd = {
+ .name = "platform-lcd",
+ .dev.platform_data = &smdk5250_lcd_data,
+};
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
{},
};
+static struct platform_device *smdk5250_devices[] __initdata = {
+ &smdk5250_lcd, /* for platform_lcd device */
+};
+
static void __init exynos5250_dt_map_io(void)
{
exynos_init_io(NULL, 0);
@@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+ platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
}
static char const *exynos5250_dt_compat[] __initdata = {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* RE: [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 6:45 ` Marek Szyprowski
-1 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-18 6:45 UTC (permalink / raw)
To: 'Leela Krishna Amudala', devicetree-discuss, linux-arm-kernel
Cc: kgene.kim, jg1.han, joshi, grant.likely, linux-samsung-soc,
thomas.ab, olofj
Hello,
On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> This patch adds machine specific support for LCD controller like setting power to LCD
> and adding LCD platform device.
>
> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
> 1 files changed, 56 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index e7113cc..02a0e68 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -13,6 +13,7 @@
> #include <linux/serial_core.h>
> #include <linux/pwm_backlight.h>
> #include <linux/gpio.h>
> +#include <linux/delay.h>
>
> #include <asm/mach/arch.h>
> #include <asm/hardware/gic.h>
> @@ -24,6 +25,7 @@
> #include <plat/gpio-cfg.h>
>
> #include "common.h"
> +#include <video/platform_lcd.h>
>
> static int smdk5250_bl_notify(struct device *unused, int brightness)
> {
> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
> .notify = smdk5250_bl_notify,
> };
>
> +static void lcd_set_power(struct plat_lcd_data *pd,
> + unsigned int power)
> +{
> +
> + /* reset */
> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
> +
> + mdelay(20);
> + if (power) {
> + /* fire nRESET on power up */
> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> + mdelay(20);
> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> + mdelay(20);
> + gpio_free(EXYNOS5_GPX1(5));
> + } else {
> + /* fire nRESET on power off */
> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> + mdelay(20);
> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> + mdelay(20);
> + gpio_free(EXYNOS5_GPX1(5));
> + }
> + mdelay(20);
> +
> + /*
> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
> + * TODO: Fix this so we are not at risk of requesting the GPIO
> + * multiple times, this should be done with device tree, and
> + * likely integrated into the plat-samsung/dev-backlight.c init.
> + */
> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
> +}
> +
> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
> +{
> + /* Don't call .set_power callback while unblanking */
> + return 0;
> +}
> +
> +static struct plat_lcd_data smdk5250_lcd_data = {
> + .set_power = lcd_set_power,
> + .match_fb = smdk5250_match_fb,
> +};
> +
> +static struct platform_device smdk5250_lcd = {
> + .name = "platform-lcd",
> + .dev.platform_data = &smdk5250_lcd_data,
> +};
> /*
> * The following lookup table is used to override device names when devices
> * are registered from device tree. This is temporarily added to enable
> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst
> = {
> {},
> };
>
> +static struct platform_device *smdk5250_devices[] __initdata = {
> + &smdk5250_lcd, /* for platform_lcd device */
> +};
> +
> static void __init exynos5250_dt_map_io(void)
> {
> exynos_init_io(NULL, 0);
> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> of_platform_populate(NULL, of_default_bus_match_table,
> exynos5250_auxdata_lookup, NULL);
> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> }
>
> static char const *exynos5250_dt_compat[] __initdata = {
Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
Please add DT support to platform lcd driver and create required bindings for it
instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
@ 2012-07-18 6:45 ` Marek Szyprowski
0 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-18 6:45 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> This patch adds machine specific support for LCD controller like setting power to LCD
> and adding LCD platform device.
>
> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
> 1 files changed, 56 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index e7113cc..02a0e68 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -13,6 +13,7 @@
> #include <linux/serial_core.h>
> #include <linux/pwm_backlight.h>
> #include <linux/gpio.h>
> +#include <linux/delay.h>
>
> #include <asm/mach/arch.h>
> #include <asm/hardware/gic.h>
> @@ -24,6 +25,7 @@
> #include <plat/gpio-cfg.h>
>
> #include "common.h"
> +#include <video/platform_lcd.h>
>
> static int smdk5250_bl_notify(struct device *unused, int brightness)
> {
> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
> .notify = smdk5250_bl_notify,
> };
>
> +static void lcd_set_power(struct plat_lcd_data *pd,
> + unsigned int power)
> +{
> +
> + /* reset */
> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
> +
> + mdelay(20);
> + if (power) {
> + /* fire nRESET on power up */
> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> + mdelay(20);
> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> + mdelay(20);
> + gpio_free(EXYNOS5_GPX1(5));
> + } else {
> + /* fire nRESET on power off */
> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> + mdelay(20);
> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> + mdelay(20);
> + gpio_free(EXYNOS5_GPX1(5));
> + }
> + mdelay(20);
> +
> + /*
> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
> + * TODO: Fix this so we are not at risk of requesting the GPIO
> + * multiple times, this should be done with device tree, and
> + * likely integrated into the plat-samsung/dev-backlight.c init.
> + */
> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
> +}
> +
> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
> +{
> + /* Don't call .set_power callback while unblanking */
> + return 0;
> +}
> +
> +static struct plat_lcd_data smdk5250_lcd_data = {
> + .set_power = lcd_set_power,
> + .match_fb = smdk5250_match_fb,
> +};
> +
> +static struct platform_device smdk5250_lcd = {
> + .name = "platform-lcd",
> + .dev.platform_data = &smdk5250_lcd_data,
> +};
> /*
> * The following lookup table is used to override device names when devices
> * are registered from device tree. This is temporarily added to enable
> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst
> = {
> {},
> };
>
> +static struct platform_device *smdk5250_devices[] __initdata = {
> + &smdk5250_lcd, /* for platform_lcd device */
> +};
> +
> static void __init exynos5250_dt_map_io(void)
> {
> exynos_init_io(NULL, 0);
> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> of_platform_populate(NULL, of_default_bus_match_table,
> exynos5250_auxdata_lookup, NULL);
> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> }
>
> static char const *exynos5250_dt_compat[] __initdata = {
Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
Please add DT support to platform lcd driver and create required bindings for it
instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
2012-07-18 6:45 ` Marek Szyprowski
@ 2012-07-19 13:21 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-19 13:21 UTC (permalink / raw)
To: Marek Szyprowski
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
Hello Marek,
On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>
>> This patch adds machine specific support for LCD controller like setting power to LCD
>> and adding LCD platform device.
>>
>> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
>> 1 files changed, 56 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> index e7113cc..02a0e68 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> @@ -13,6 +13,7 @@
>> #include <linux/serial_core.h>
>> #include <linux/pwm_backlight.h>
>> #include <linux/gpio.h>
>> +#include <linux/delay.h>
>>
>> #include <asm/mach/arch.h>
>> #include <asm/hardware/gic.h>
>> @@ -24,6 +25,7 @@
>> #include <plat/gpio-cfg.h>
>>
>> #include "common.h"
>> +#include <video/platform_lcd.h>
>>
>> static int smdk5250_bl_notify(struct device *unused, int brightness)
>> {
>> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
>> .notify = smdk5250_bl_notify,
>> };
>>
>> +static void lcd_set_power(struct plat_lcd_data *pd,
>> + unsigned int power)
>> +{
>> +
>> + /* reset */
>> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
>> +
>> + mdelay(20);
>> + if (power) {
>> + /* fire nRESET on power up */
>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> + mdelay(20);
>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> + mdelay(20);
>> + gpio_free(EXYNOS5_GPX1(5));
>> + } else {
>> + /* fire nRESET on power off */
>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> + mdelay(20);
>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> + mdelay(20);
>> + gpio_free(EXYNOS5_GPX1(5));
>> + }
>> + mdelay(20);
>> +
>> + /*
>> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
>> + * TODO: Fix this so we are not at risk of requesting the GPIO
>> + * multiple times, this should be done with device tree, and
>> + * likely integrated into the plat-samsung/dev-backlight.c init.
>> + */
>> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
>> +}
>> +
>> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
>> +{
>> + /* Don't call .set_power callback while unblanking */
>> + return 0;
>> +}
>> +
>> +static struct plat_lcd_data smdk5250_lcd_data = {
>> + .set_power = lcd_set_power,
>> + .match_fb = smdk5250_match_fb,
>> +};
>> +
>> +static struct platform_device smdk5250_lcd = {
>> + .name = "platform-lcd",
>> + .dev.platform_data = &smdk5250_lcd_data,
>> +};
>> /*
>> * The following lookup table is used to override device names when devices
>> * are registered from device tree. This is temporarily added to enable
>> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst
>> = {
>> {},
>> };
>>
>> +static struct platform_device *smdk5250_devices[] __initdata = {
>> + &smdk5250_lcd, /* for platform_lcd device */
>> +};
>> +
>> static void __init exynos5250_dt_map_io(void)
>> {
>> exynos_init_io(NULL, 0);
>> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
>> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
>> of_platform_populate(NULL, of_default_bus_match_table,
>> exynos5250_auxdata_lookup, NULL);
>> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
>> }
>>
>> static char const *exynos5250_dt_compat[] __initdata = {
>
> Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
> operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
> Please add DT support to platform lcd driver and create required bindings for it
> instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
>
Yes true, that GPIO numbers will vary for boards.
Can you please confirm that platform lcd driver means the core
"drivers/video/backlight/platform_lcd.c" file.
But platform lcd driver is used by other(non samsung) platforms also.
So, If I add the DT suppot to that file, I have to test the changes on
other platforms also.
Can you please kindly suggest me some other way to overcome this situation.
Best Wishes,
Leela Krishna Amudala.
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
@ 2012-07-19 13:21 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-19 13:21 UTC (permalink / raw)
To: linux-arm-kernel
Hello Marek,
On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>
>> This patch adds machine specific support for LCD controller like setting power to LCD
>> and adding LCD platform device.
>>
>> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
>> 1 files changed, 56 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> index e7113cc..02a0e68 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> @@ -13,6 +13,7 @@
>> #include <linux/serial_core.h>
>> #include <linux/pwm_backlight.h>
>> #include <linux/gpio.h>
>> +#include <linux/delay.h>
>>
>> #include <asm/mach/arch.h>
>> #include <asm/hardware/gic.h>
>> @@ -24,6 +25,7 @@
>> #include <plat/gpio-cfg.h>
>>
>> #include "common.h"
>> +#include <video/platform_lcd.h>
>>
>> static int smdk5250_bl_notify(struct device *unused, int brightness)
>> {
>> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
>> .notify = smdk5250_bl_notify,
>> };
>>
>> +static void lcd_set_power(struct plat_lcd_data *pd,
>> + unsigned int power)
>> +{
>> +
>> + /* reset */
>> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
>> +
>> + mdelay(20);
>> + if (power) {
>> + /* fire nRESET on power up */
>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> + mdelay(20);
>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> + mdelay(20);
>> + gpio_free(EXYNOS5_GPX1(5));
>> + } else {
>> + /* fire nRESET on power off */
>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> + mdelay(20);
>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> + mdelay(20);
>> + gpio_free(EXYNOS5_GPX1(5));
>> + }
>> + mdelay(20);
>> +
>> + /*
>> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
>> + * TODO: Fix this so we are not at risk of requesting the GPIO
>> + * multiple times, this should be done with device tree, and
>> + * likely integrated into the plat-samsung/dev-backlight.c init.
>> + */
>> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
>> +}
>> +
>> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
>> +{
>> + /* Don't call .set_power callback while unblanking */
>> + return 0;
>> +}
>> +
>> +static struct plat_lcd_data smdk5250_lcd_data = {
>> + .set_power = lcd_set_power,
>> + .match_fb = smdk5250_match_fb,
>> +};
>> +
>> +static struct platform_device smdk5250_lcd = {
>> + .name = "platform-lcd",
>> + .dev.platform_data = &smdk5250_lcd_data,
>> +};
>> /*
>> * The following lookup table is used to override device names when devices
>> * are registered from device tree. This is temporarily added to enable
>> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst
>> = {
>> {},
>> };
>>
>> +static struct platform_device *smdk5250_devices[] __initdata = {
>> + &smdk5250_lcd, /* for platform_lcd device */
>> +};
>> +
>> static void __init exynos5250_dt_map_io(void)
>> {
>> exynos_init_io(NULL, 0);
>> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
>> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
>> of_platform_populate(NULL, of_default_bus_match_table,
>> exynos5250_auxdata_lookup, NULL);
>> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
>> }
>>
>> static char const *exynos5250_dt_compat[] __initdata = {
>
> Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
> operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
> Please add DT support to platform lcd driver and create required bindings for it
> instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
>
Yes true, that GPIO numbers will vary for boards.
Can you please confirm that platform lcd driver means the core
"drivers/video/backlight/platform_lcd.c" file.
But platform lcd driver is used by other(non samsung) platforms also.
So, If I add the DT suppot to that file, I have to test the changes on
other platforms also.
Can you please kindly suggest me some other way to overcome this situation.
Best Wishes,
Leela Krishna Amudala.
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* RE: [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
2012-07-19 13:21 ` Leela Krishna Amudala
@ 2012-07-20 6:31 ` Marek Szyprowski
-1 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-20 6:31 UTC (permalink / raw)
To: 'Leela Krishna Amudala'
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
Hello,
On Thursday, July 19, 2012 3:22 PM Leela Krishna Amudala wrote:
> Hello Marek,
>
> On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> >
> >> This patch adds machine specific support for LCD controller like setting power to LCD
> >> and adding LCD platform device.
> >>
> >> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
> >> 1 files changed, 56 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-
> dt.c
> >> index e7113cc..02a0e68 100644
> >> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> >> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> >> @@ -13,6 +13,7 @@
> >> #include <linux/serial_core.h>
> >> #include <linux/pwm_backlight.h>
> >> #include <linux/gpio.h>
> >> +#include <linux/delay.h>
> >>
> >> #include <asm/mach/arch.h>
> >> #include <asm/hardware/gic.h>
> >> @@ -24,6 +25,7 @@
> >> #include <plat/gpio-cfg.h>
> >>
> >> #include "common.h"
> >> +#include <video/platform_lcd.h>
> >>
> >> static int smdk5250_bl_notify(struct device *unused, int brightness)
> >> {
> >> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
> >> .notify = smdk5250_bl_notify,
> >> };
> >>
> >> +static void lcd_set_power(struct plat_lcd_data *pd,
> >> + unsigned int power)
> >> +{
> >> +
> >> + /* reset */
> >> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
> >> +
> >> + mdelay(20);
> >> + if (power) {
> >> + /* fire nRESET on power up */
> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> >> + mdelay(20);
> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> >> + mdelay(20);
> >> + gpio_free(EXYNOS5_GPX1(5));
> >> + } else {
> >> + /* fire nRESET on power off */
> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> >> + mdelay(20);
> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> >> + mdelay(20);
> >> + gpio_free(EXYNOS5_GPX1(5));
> >> + }
> >> + mdelay(20);
> >> +
> >> + /*
> >> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
> >> + * TODO: Fix this so we are not at risk of requesting the GPIO
> >> + * multiple times, this should be done with device tree, and
> >> + * likely integrated into the plat-samsung/dev-backlight.c init.
> >> + */
> >> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
> >> +}
> >> +
> >> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
> >> +{
> >> + /* Don't call .set_power callback while unblanking */
> >> + return 0;
> >> +}
> >> +
> >> +static struct plat_lcd_data smdk5250_lcd_data = {
> >> + .set_power = lcd_set_power,
> >> + .match_fb = smdk5250_match_fb,
> >> +};
> >> +
> >> +static struct platform_device smdk5250_lcd = {
> >> + .name = "platform-lcd",
> >> + .dev.platform_data = &smdk5250_lcd_data,
> >> +};
> >> /*
> >> * The following lookup table is used to override device names when devices
> >> * are registered from device tree. This is temporarily added to enable
> >> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[]
> __initconst
> >> = {
> >> {},
> >> };
> >>
> >> +static struct platform_device *smdk5250_devices[] __initdata = {
> >> + &smdk5250_lcd, /* for platform_lcd device */
> >> +};
> >> +
> >> static void __init exynos5250_dt_map_io(void)
> >> {
> >> exynos_init_io(NULL, 0);
> >> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
> >> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> >> of_platform_populate(NULL, of_default_bus_match_table,
> >> exynos5250_auxdata_lookup, NULL);
> >> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> >> }
> >>
> >> static char const *exynos5250_dt_compat[] __initdata = {
> >
> > Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
> > operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
> > Please add DT support to platform lcd driver and create required bindings for it
> > instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
> >
>
> Yes true, that GPIO numbers will vary for boards.
> Can you please confirm that platform lcd driver means the core
> "drivers/video/backlight/platform_lcd.c" file.
Yes, by lcd driver I meant that driver.
> But platform lcd driver is used by other(non samsung) platforms also.
> So, If I add the DT suppot to that file, I have to test the changes on
> other platforms also.
> Can you please kindly suggest me some other way to overcome this situation.
Just check that you don't break existing code. For some examples please refer to the DT
changes in drivers/input/keyboard/gpio_keys.c (see commit fd05d08920). You can also check
if the driver works fine after your changes by setting it up from platform data instead of
DT.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
@ 2012-07-20 6:31 ` Marek Szyprowski
0 siblings, 0 replies; 84+ messages in thread
From: Marek Szyprowski @ 2012-07-20 6:31 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Thursday, July 19, 2012 3:22 PM Leela Krishna Amudala wrote:
> Hello Marek,
>
> On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
> >
> >> This patch adds machine specific support for LCD controller like setting power to LCD
> >> and adding LCD platform device.
> >>
> >> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
> >> 1 files changed, 56 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-
> dt.c
> >> index e7113cc..02a0e68 100644
> >> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> >> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> >> @@ -13,6 +13,7 @@
> >> #include <linux/serial_core.h>
> >> #include <linux/pwm_backlight.h>
> >> #include <linux/gpio.h>
> >> +#include <linux/delay.h>
> >>
> >> #include <asm/mach/arch.h>
> >> #include <asm/hardware/gic.h>
> >> @@ -24,6 +25,7 @@
> >> #include <plat/gpio-cfg.h>
> >>
> >> #include "common.h"
> >> +#include <video/platform_lcd.h>
> >>
> >> static int smdk5250_bl_notify(struct device *unused, int brightness)
> >> {
> >> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
> >> .notify = smdk5250_bl_notify,
> >> };
> >>
> >> +static void lcd_set_power(struct plat_lcd_data *pd,
> >> + unsigned int power)
> >> +{
> >> +
> >> + /* reset */
> >> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
> >> +
> >> + mdelay(20);
> >> + if (power) {
> >> + /* fire nRESET on power up */
> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> >> + mdelay(20);
> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> >> + mdelay(20);
> >> + gpio_free(EXYNOS5_GPX1(5));
> >> + } else {
> >> + /* fire nRESET on power off */
> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
> >> + mdelay(20);
> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
> >> + mdelay(20);
> >> + gpio_free(EXYNOS5_GPX1(5));
> >> + }
> >> + mdelay(20);
> >> +
> >> + /*
> >> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
> >> + * TODO: Fix this so we are not at risk of requesting the GPIO
> >> + * multiple times, this should be done with device tree, and
> >> + * likely integrated into the plat-samsung/dev-backlight.c init.
> >> + */
> >> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
> >> +}
> >> +
> >> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
> >> +{
> >> + /* Don't call .set_power callback while unblanking */
> >> + return 0;
> >> +}
> >> +
> >> +static struct plat_lcd_data smdk5250_lcd_data = {
> >> + .set_power = lcd_set_power,
> >> + .match_fb = smdk5250_match_fb,
> >> +};
> >> +
> >> +static struct platform_device smdk5250_lcd = {
> >> + .name = "platform-lcd",
> >> + .dev.platform_data = &smdk5250_lcd_data,
> >> +};
> >> /*
> >> * The following lookup table is used to override device names when devices
> >> * are registered from device tree. This is temporarily added to enable
> >> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[]
> __initconst
> >> = {
> >> {},
> >> };
> >>
> >> +static struct platform_device *smdk5250_devices[] __initdata = {
> >> + &smdk5250_lcd, /* for platform_lcd device */
> >> +};
> >> +
> >> static void __init exynos5250_dt_map_io(void)
> >> {
> >> exynos_init_io(NULL, 0);
> >> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
> >> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> >> of_platform_populate(NULL, of_default_bus_match_table,
> >> exynos5250_auxdata_lookup, NULL);
> >> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> >> }
> >>
> >> static char const *exynos5250_dt_compat[] __initdata = {
> >
> > Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
> > operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
> > Please add DT support to platform lcd driver and create required bindings for it
> > instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
> >
>
> Yes true, that GPIO numbers will vary for boards.
> Can you please confirm that platform lcd driver means the core
> "drivers/video/backlight/platform_lcd.c" file.
Yes, by lcd driver I meant that driver.
> But platform lcd driver is used by other(non samsung) platforms also.
> So, If I add the DT suppot to that file, I have to test the changes on
> other platforms also.
> Can you please kindly suggest me some other way to overcome this situation.
Just check that you don't break existing code. For some examples please refer to the DT
changes in drivers/input/keyboard/gpio_keys.c (see commit fd05d08920). You can also check
if the driver works fine after your changes by setting it up from platform data instead of
DT.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
2012-07-20 6:31 ` Marek Szyprowski
@ 2012-07-24 16:02 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-24 16:02 UTC (permalink / raw)
To: Marek Szyprowski
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
Hello Marek,
On Fri, Jul 20, 2012 at 3:31 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Thursday, July 19, 2012 3:22 PM Leela Krishna Amudala wrote:
>
>> Hello Marek,
>>
>> On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>> > Hello,
>> >
>> > On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>> >
>> >> This patch adds machine specific support for LCD controller like setting power to LCD
>> >> and adding LCD platform device.
>> >>
>> >> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
>> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> >> ---
>> >> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
>> >> 1 files changed, 56 insertions(+), 0 deletions(-)
>> >>
>> >> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-
>> dt.c
>> >> index e7113cc..02a0e68 100644
>> >> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> >> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> >> @@ -13,6 +13,7 @@
>> >> #include <linux/serial_core.h>
>> >> #include <linux/pwm_backlight.h>
>> >> #include <linux/gpio.h>
>> >> +#include <linux/delay.h>
>> >>
>> >> #include <asm/mach/arch.h>
>> >> #include <asm/hardware/gic.h>
>> >> @@ -24,6 +25,7 @@
>> >> #include <plat/gpio-cfg.h>
>> >>
>> >> #include "common.h"
>> >> +#include <video/platform_lcd.h>
>> >>
>> >> static int smdk5250_bl_notify(struct device *unused, int brightness)
>> >> {
>> >> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
>> >> .notify = smdk5250_bl_notify,
>> >> };
>> >>
>> >> +static void lcd_set_power(struct plat_lcd_data *pd,
>> >> + unsigned int power)
>> >> +{
>> >> +
>> >> + /* reset */
>> >> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
>> >> +
>> >> + mdelay(20);
>> >> + if (power) {
>> >> + /* fire nRESET on power up */
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> >> + mdelay(20);
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> >> + mdelay(20);
>> >> + gpio_free(EXYNOS5_GPX1(5));
>> >> + } else {
>> >> + /* fire nRESET on power off */
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> >> + mdelay(20);
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> >> + mdelay(20);
>> >> + gpio_free(EXYNOS5_GPX1(5));
>> >> + }
>> >> + mdelay(20);
>> >> +
>> >> + /*
>> >> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
>> >> + * TODO: Fix this so we are not at risk of requesting the GPIO
>> >> + * multiple times, this should be done with device tree, and
>> >> + * likely integrated into the plat-samsung/dev-backlight.c init.
>> >> + */
>> >> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
>> >> +}
>> >> +
>> >> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
>> >> +{
>> >> + /* Don't call .set_power callback while unblanking */
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static struct plat_lcd_data smdk5250_lcd_data = {
>> >> + .set_power = lcd_set_power,
>> >> + .match_fb = smdk5250_match_fb,
>> >> +};
>> >> +
>> >> +static struct platform_device smdk5250_lcd = {
>> >> + .name = "platform-lcd",
>> >> + .dev.platform_data = &smdk5250_lcd_data,
>> >> +};
>> >> /*
>> >> * The following lookup table is used to override device names when devices
>> >> * are registered from device tree. This is temporarily added to enable
>> >> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[]
>> __initconst
>> >> = {
>> >> {},
>> >> };
>> >>
>> >> +static struct platform_device *smdk5250_devices[] __initdata = {
>> >> + &smdk5250_lcd, /* for platform_lcd device */
>> >> +};
>> >> +
>> >> static void __init exynos5250_dt_map_io(void)
>> >> {
>> >> exynos_init_io(NULL, 0);
>> >> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
>> >> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
>> >> of_platform_populate(NULL, of_default_bus_match_table,
>> >> exynos5250_auxdata_lookup, NULL);
>> >> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
>> >> }
>> >>
>> >> static char const *exynos5250_dt_compat[] __initdata = {
>> >
>> > Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
>> > operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
>> > Please add DT support to platform lcd driver and create required bindings for it
>> > instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
>> >
>>
>> Yes true, that GPIO numbers will vary for boards.
>> Can you please confirm that platform lcd driver means the core
>> "drivers/video/backlight/platform_lcd.c" file.
>
> Yes, by lcd driver I meant that driver.
>
>> But platform lcd driver is used by other(non samsung) platforms also.
>> So, If I add the DT suppot to that file, I have to test the changes on
>> other platforms also.
>> Can you please kindly suggest me some other way to overcome this situation.
>
> Just check that you don't break existing code. For some examples please refer to the DT
> changes in drivers/input/keyboard/gpio_keys.c (see commit fd05d08920). You can also check
> if the driver works fine after your changes by setting it up from platform data instead of
> DT.
>
I came across some links for adding DT support to platform-lcd driver
posted by Thomas Abraham.
And because of some reasons it was not accepted.
Here is the link for the discussion happened on this topic
http://lkml.indiana.edu/hypermail/linux/kernel/1201.0/00089.html
He has posted some patches for lcd panel power control, so can I go
ahead and extend this driver to meet our requirements?
Here is the link for the patch set
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091412.html
Best Wishes,
Leela Krishna Amudala
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
@ 2012-07-24 16:02 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-24 16:02 UTC (permalink / raw)
To: linux-arm-kernel
Hello Marek,
On Fri, Jul 20, 2012 at 3:31 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Thursday, July 19, 2012 3:22 PM Leela Krishna Amudala wrote:
>
>> Hello Marek,
>>
>> On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>> > Hello,
>> >
>> > On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>> >
>> >> This patch adds machine specific support for LCD controller like setting power to LCD
>> >> and adding LCD platform device.
>> >>
>> >> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
>> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> >> ---
>> >> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
>> >> 1 files changed, 56 insertions(+), 0 deletions(-)
>> >>
>> >> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-
>> dt.c
>> >> index e7113cc..02a0e68 100644
>> >> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> >> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> >> @@ -13,6 +13,7 @@
>> >> #include <linux/serial_core.h>
>> >> #include <linux/pwm_backlight.h>
>> >> #include <linux/gpio.h>
>> >> +#include <linux/delay.h>
>> >>
>> >> #include <asm/mach/arch.h>
>> >> #include <asm/hardware/gic.h>
>> >> @@ -24,6 +25,7 @@
>> >> #include <plat/gpio-cfg.h>
>> >>
>> >> #include "common.h"
>> >> +#include <video/platform_lcd.h>
>> >>
>> >> static int smdk5250_bl_notify(struct device *unused, int brightness)
>> >> {
>> >> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
>> >> .notify = smdk5250_bl_notify,
>> >> };
>> >>
>> >> +static void lcd_set_power(struct plat_lcd_data *pd,
>> >> + unsigned int power)
>> >> +{
>> >> +
>> >> + /* reset */
>> >> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
>> >> +
>> >> + mdelay(20);
>> >> + if (power) {
>> >> + /* fire nRESET on power up */
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> >> + mdelay(20);
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> >> + mdelay(20);
>> >> + gpio_free(EXYNOS5_GPX1(5));
>> >> + } else {
>> >> + /* fire nRESET on power off */
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>> >> + mdelay(20);
>> >> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>> >> + mdelay(20);
>> >> + gpio_free(EXYNOS5_GPX1(5));
>> >> + }
>> >> + mdelay(20);
>> >> +
>> >> + /*
>> >> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
>> >> + * TODO: Fix this so we are not at risk of requesting the GPIO
>> >> + * multiple times, this should be done with device tree, and
>> >> + * likely integrated into the plat-samsung/dev-backlight.c init.
>> >> + */
>> >> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
>> >> +}
>> >> +
>> >> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
>> >> +{
>> >> + /* Don't call .set_power callback while unblanking */
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static struct plat_lcd_data smdk5250_lcd_data = {
>> >> + .set_power = lcd_set_power,
>> >> + .match_fb = smdk5250_match_fb,
>> >> +};
>> >> +
>> >> +static struct platform_device smdk5250_lcd = {
>> >> + .name = "platform-lcd",
>> >> + .dev.platform_data = &smdk5250_lcd_data,
>> >> +};
>> >> /*
>> >> * The following lookup table is used to override device names when devices
>> >> * are registered from device tree. This is temporarily added to enable
>> >> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[]
>> __initconst
>> >> = {
>> >> {},
>> >> };
>> >>
>> >> +static struct platform_device *smdk5250_devices[] __initdata = {
>> >> + &smdk5250_lcd, /* for platform_lcd device */
>> >> +};
>> >> +
>> >> static void __init exynos5250_dt_map_io(void)
>> >> {
>> >> exynos_init_io(NULL, 0);
>> >> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
>> >> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
>> >> of_platform_populate(NULL, of_default_bus_match_table,
>> >> exynos5250_auxdata_lookup, NULL);
>> >> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
>> >> }
>> >>
>> >> static char const *exynos5250_dt_compat[] __initdata = {
>> >
>> > Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
>> > operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
>> > Please add DT support to platform lcd driver and create required bindings for it
>> > instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
>> >
>>
>> Yes true, that GPIO numbers will vary for boards.
>> Can you please confirm that platform lcd driver means the core
>> "drivers/video/backlight/platform_lcd.c" file.
>
> Yes, by lcd driver I meant that driver.
>
>> But platform lcd driver is used by other(non samsung) platforms also.
>> So, If I add the DT suppot to that file, I have to test the changes on
>> other platforms also.
>> Can you please kindly suggest me some other way to overcome this situation.
>
> Just check that you don't break existing code. For some examples please refer to the DT
> changes in drivers/input/keyboard/gpio_keys.c (see commit fd05d08920). You can also check
> if the driver works fine after your changes by setting it up from platform data instead of
> DT.
>
I came across some links for adding DT support to platform-lcd driver
posted by Thomas Abraham.
And because of some reasons it was not accepted.
Here is the link for the discussion happened on this topic
http://lkml.indiana.edu/hypermail/linux/kernel/1201.0/00089.html
He has posted some patches for lcd panel power control, so can I go
ahead and extend this driver to meet our requirements?
Here is the link for the patch set
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091412.html
Best Wishes,
Leela Krishna Amudala
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
2012-07-19 13:21 ` Leela Krishna Amudala
@ 2012-07-20 7:17 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-20 7:17 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: Marek Szyprowski, kgene.kim, devicetree-discuss, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj,
linux-arm-kernel
On 07/19/2012 10:21 PM, Leela Krishna Amudala wrote:
> Hello Marek,
>
> On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> Hello,
>>
>> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>>
>>> This patch adds machine specific support for LCD controller like setting power to LCD
>>> and adding LCD platform device.
>>>
>>> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>> ---
>>> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
>>> 1 files changed, 56 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> index e7113cc..02a0e68 100644
>>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> @@ -13,6 +13,7 @@
>>> #include <linux/serial_core.h>
>>> #include <linux/pwm_backlight.h>
>>> #include <linux/gpio.h>
>>> +#include <linux/delay.h>
>>>
>>> #include <asm/mach/arch.h>
>>> #include <asm/hardware/gic.h>
>>> @@ -24,6 +25,7 @@
>>> #include <plat/gpio-cfg.h>
>>>
>>> #include "common.h"
>>> +#include <video/platform_lcd.h>
>>>
>>> static int smdk5250_bl_notify(struct device *unused, int brightness)
>>> {
>>> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
>>> .notify = smdk5250_bl_notify,
>>> };
>>>
>>> +static void lcd_set_power(struct plat_lcd_data *pd,
>>> + unsigned int power)
>>> +{
>>> +
>>> + /* reset */
>>> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
>>> +
>>> + mdelay(20);
>>> + if (power) {
>>> + /* fire nRESET on power up */
>>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>>> + mdelay(20);
>>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>>> + mdelay(20);
>>> + gpio_free(EXYNOS5_GPX1(5));
>>> + } else {
>>> + /* fire nRESET on power off */
>>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>>> + mdelay(20);
>>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>>> + mdelay(20);
>>> + gpio_free(EXYNOS5_GPX1(5));
>>> + }
>>> + mdelay(20);
>>> +
>>> + /*
>>> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
>>> + * TODO: Fix this so we are not at risk of requesting the GPIO
>>> + * multiple times, this should be done with device tree, and
>>> + * likely integrated into the plat-samsung/dev-backlight.c init.
>>> + */
>>> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
>>> +}
>>> +
>>> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
>>> +{
>>> + /* Don't call .set_power callback while unblanking */
>>> + return 0;
>>> +}
>>> +
>>> +static struct plat_lcd_data smdk5250_lcd_data = {
>>> + .set_power = lcd_set_power,
>>> + .match_fb = smdk5250_match_fb,
>>> +};
>>> +
>>> +static struct platform_device smdk5250_lcd = {
>>> + .name = "platform-lcd",
>>> + .dev.platform_data = &smdk5250_lcd_data,
>>> +};
>>> /*
>>> * The following lookup table is used to override device names when devices
>>> * are registered from device tree. This is temporarily added to enable
>>> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst
>>> = {
>>> {},
>>> };
>>>
>>> +static struct platform_device *smdk5250_devices[] __initdata = {
>>> + &smdk5250_lcd, /* for platform_lcd device */
>>> +};
>>> +
>>> static void __init exynos5250_dt_map_io(void)
>>> {
>>> exynos_init_io(NULL, 0);
>>> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
>>> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
>>> of_platform_populate(NULL, of_default_bus_match_table,
>>> exynos5250_auxdata_lookup, NULL);
>>> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
>>> }
>>>
>>> static char const *exynos5250_dt_compat[] __initdata = {
>> Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
>> operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
>> Please add DT support to platform lcd driver and create required bindings for it
>> instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
>>
> Yes true, that GPIO numbers will vary for boards.
> Can you please confirm that platform lcd driver means the core
> "drivers/video/backlight/platform_lcd.c" file.
> But platform lcd driver is used by other(non samsung) platforms also.
> So, If I add the DT suppot to that file, I have to test the changes on
> other platforms also.
> Can you please kindly suggest me some other way to overcome this situation.
These are smdk5250 specific codes to support NON DT device and driver.
Please see arch/arm/mach-kirkwood/board-dnskw.c, you can refer it to
support NON DT devices and drivers.
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 3/7] ARM: EXYNOS5: add machine specific support for LCD
@ 2012-07-20 7:17 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-20 7:17 UTC (permalink / raw)
To: linux-arm-kernel
On 07/19/2012 10:21 PM, Leela Krishna Amudala wrote:
> Hello Marek,
>
> On Wed, Jul 18, 2012 at 12:15 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> Hello,
>>
>> On Wednesday, July 18, 2012 7:57 AM Leela Krishna Amudala wrote:
>>
>>> This patch adds machine specific support for LCD controller like setting power to LCD
>>> and adding LCD platform device.
>>>
>>> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>> ---
>>> arch/arm/mach-exynos/mach-exynos5-dt.c | 56 ++++++++++++++++++++++++++++++++
>>> 1 files changed, 56 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> index e7113cc..02a0e68 100644
>>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> @@ -13,6 +13,7 @@
>>> #include <linux/serial_core.h>
>>> #include <linux/pwm_backlight.h>
>>> #include <linux/gpio.h>
>>> +#include <linux/delay.h>
>>>
>>> #include <asm/mach/arch.h>
>>> #include <asm/hardware/gic.h>
>>> @@ -24,6 +25,7 @@
>>> #include <plat/gpio-cfg.h>
>>>
>>> #include "common.h"
>>> +#include <video/platform_lcd.h>
>>>
>>> static int smdk5250_bl_notify(struct device *unused, int brightness)
>>> {
>>> @@ -47,6 +49,55 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
>>> .notify = smdk5250_bl_notify,
>>> };
>>>
>>> +static void lcd_set_power(struct plat_lcd_data *pd,
>>> + unsigned int power)
>>> +{
>>> +
>>> + /* reset */
>>> + gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
>>> +
>>> + mdelay(20);
>>> + if (power) {
>>> + /* fire nRESET on power up */
>>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>>> + mdelay(20);
>>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>>> + mdelay(20);
>>> + gpio_free(EXYNOS5_GPX1(5));
>>> + } else {
>>> + /* fire nRESET on power off */
>>> + gpio_set_value(EXYNOS5_GPX1(5), 0);
>>> + mdelay(20);
>>> + gpio_set_value(EXYNOS5_GPX1(5), 1);
>>> + mdelay(20);
>>> + gpio_free(EXYNOS5_GPX1(5));
>>> + }
>>> + mdelay(20);
>>> +
>>> + /*
>>> + * Request lcd_bl_en GPIO for smdk5250_bl_notify().
>>> + * TODO: Fix this so we are not at risk of requesting the GPIO
>>> + * multiple times, this should be done with device tree, and
>>> + * likely integrated into the plat-samsung/dev-backlight.c init.
>>> + */
>>> + gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
>>> +}
>>> +
>>> +static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
>>> +{
>>> + /* Don't call .set_power callback while unblanking */
>>> + return 0;
>>> +}
>>> +
>>> +static struct plat_lcd_data smdk5250_lcd_data = {
>>> + .set_power = lcd_set_power,
>>> + .match_fb = smdk5250_match_fb,
>>> +};
>>> +
>>> +static struct platform_device smdk5250_lcd = {
>>> + .name = "platform-lcd",
>>> + .dev.platform_data = &smdk5250_lcd_data,
>>> +};
>>> /*
>>> * The following lookup table is used to override device names when devices
>>> * are registered from device tree. This is temporarily added to enable
>>> @@ -85,6 +136,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst
>>> = {
>>> {},
>>> };
>>>
>>> +static struct platform_device *smdk5250_devices[] __initdata = {
>>> + &smdk5250_lcd, /* for platform_lcd device */
>>> +};
>>> +
>>> static void __init exynos5250_dt_map_io(void)
>>> {
>>> exynos_init_io(NULL, 0);
>>> @@ -96,6 +151,7 @@ static void __init exynos5250_dt_machine_init(void)
>>> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
>>> of_platform_populate(NULL, of_default_bus_match_table,
>>> exynos5250_auxdata_lookup, NULL);
>>> + platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
>>> }
>>>
>>> static char const *exynos5250_dt_compat[] __initdata = {
>> Sorry, but this patch looks completely weird to me. exynos5-dt machine is aimed to
>> operate on ANY Exynos5 based board with proper device tree bindings, not only SMDK5250.
>> Please add DT support to platform lcd driver and create required bindings for it
>> instead of hardcoding the platform data and gpio numbers in mach-exynos5-dt.c
>>
> Yes true, that GPIO numbers will vary for boards.
> Can you please confirm that platform lcd driver means the core
> "drivers/video/backlight/platform_lcd.c" file.
> But platform lcd driver is used by other(non samsung) platforms also.
> So, If I add the DT suppot to that file, I have to test the changes on
> other platforms also.
> Can you please kindly suggest me some other way to overcome this situation.
These are smdk5250 specific codes to support NON DT device and driver.
Please see arch/arm/mach-kirkwood/board-dnskw.c, you can refer it to
support NON DT devices and drivers.
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 4/7] ARM: EXYNOS: Adding DRM platform device
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
Add DRM platform device to machine file for exynos5.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/mach-exynos5-dt.c | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 02a0e68..99f2b24 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -17,6 +17,7 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
+#include <asm/io.h>
#include <mach/map.h>
#include <plat/cpu.h>
@@ -27,6 +28,22 @@
#include "common.h"
#include <video/platform_lcd.h>
+static void exynos_fimd_gpio_setup_24bpp(void)
+{
+ unsigned int reg = 0;
+ /*
+ * Set DISP1BLK_CFG register for Display path selection
+ * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
+ * ---------------------
+ * 0 | MIE/MDNIE
+ * 1 | FIMD : selected
+ */
+ reg = __raw_readl(S3C_VA_SYS + 0x0214);
+ reg &= ~(1 << 15); /* To save other reset values */
+ reg |= (1 << 15);
+ __raw_writel(reg, S3C_VA_SYS + 0x0214);
+}
+
static int smdk5250_bl_notify(struct device *unused, int brightness)
{
/* manage lcd_bl_en signal */
@@ -49,6 +66,14 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
.notify = smdk5250_bl_notify,
};
+static struct platform_device exynos_drm_device = {
+ .name = "exynos-drm",
+ .dev = {
+ .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = 0xffffffffUL,
+ }
+};
+
static void lcd_set_power(struct plat_lcd_data *pd,
unsigned int power)
{
@@ -138,6 +163,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
static struct platform_device *smdk5250_devices[] __initdata = {
&smdk5250_lcd, /* for platform_lcd device */
+ &exynos_drm_device,
};
static void __init exynos5250_dt_map_io(void)
@@ -151,6 +177,7 @@ static void __init exynos5250_dt_machine_init(void)
samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+ exynos_fimd_gpio_setup_24bpp();
platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 4/7] ARM: EXYNOS: Adding DRM platform device
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
Add DRM platform device to machine file for exynos5.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/mach-exynos5-dt.c | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 02a0e68..99f2b24 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -17,6 +17,7 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
+#include <asm/io.h>
#include <mach/map.h>
#include <plat/cpu.h>
@@ -27,6 +28,22 @@
#include "common.h"
#include <video/platform_lcd.h>
+static void exynos_fimd_gpio_setup_24bpp(void)
+{
+ unsigned int reg = 0;
+ /*
+ * Set DISP1BLK_CFG register for Display path selection
+ * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
+ * ---------------------
+ * 0 | MIE/MDNIE
+ * 1 | FIMD : selected
+ */
+ reg = __raw_readl(S3C_VA_SYS + 0x0214);
+ reg &= ~(1 << 15); /* To save other reset values */
+ reg |= (1 << 15);
+ __raw_writel(reg, S3C_VA_SYS + 0x0214);
+}
+
static int smdk5250_bl_notify(struct device *unused, int brightness)
{
/* manage lcd_bl_en signal */
@@ -49,6 +66,14 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
.notify = smdk5250_bl_notify,
};
+static struct platform_device exynos_drm_device = {
+ .name = "exynos-drm",
+ .dev = {
+ .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = 0xffffffffUL,
+ }
+};
+
static void lcd_set_power(struct plat_lcd_data *pd,
unsigned int power)
{
@@ -138,6 +163,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
static struct platform_device *smdk5250_devices[] __initdata = {
&smdk5250_lcd, /* for platform_lcd device */
+ &exynos_drm_device,
};
static void __init exynos5250_dt_map_io(void)
@@ -151,6 +177,7 @@ static void __init exynos5250_dt_machine_init(void)
samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+ exynos_fimd_gpio_setup_24bpp();
platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH V2 4/7] ARM: EXYNOS: Adding DRM platform device
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-20 7:33 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-20 7:33 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> Add DRM platform device to machine file for exynos5.
>
> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/mach-exynos5-dt.c | 27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 02a0e68..99f2b24 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -17,6 +17,7 @@
>
> #include <asm/mach/arch.h>
> #include <asm/hardware/gic.h>
> +#include <asm/io.h>
> #include <mach/map.h>
>
> #include <plat/cpu.h>
> @@ -27,6 +28,22 @@
> #include "common.h"
> #include <video/platform_lcd.h>
>
> +static void exynos_fimd_gpio_setup_24bpp(void)
The function name is wrong, this function doesn't control gpios.
> +{
> + unsigned int reg = 0;
> + /*
> + * Set DISP1BLK_CFG register for Display path selection
> + * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
> + * ---------------------
> + * 0 | MIE/MDNIE
> + * 1 | FIMD : selected
> + */
> + reg = __raw_readl(S3C_VA_SYS + 0x0214);
> + reg &= ~(1 << 15); /* To save other reset values */
> + reg |= (1 << 15);
> + __raw_writel(reg, S3C_VA_SYS + 0x0214);
> +}
If needs this, move to arch/arm/mach-exynos/setup-fimd0.c
> +
> static int smdk5250_bl_notify(struct device *unused, int brightness)
> {
> /* manage lcd_bl_en signal */
> @@ -49,6 +66,14 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
> .notify = smdk5250_bl_notify,
> };
>
> +static struct platform_device exynos_drm_device = {
> + .name = "exynos-drm",
> + .dev = {
> + .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
> + .coherent_dma_mask = 0xffffffffUL,
> + }
> +};
> +
There is already exynos-drm device at the arch/arm/mach-exynos/dev-drm.c
> static void lcd_set_power(struct plat_lcd_data *pd,
> unsigned int power)
> {
> @@ -138,6 +163,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>
> static struct platform_device *smdk5250_devices[] __initdata = {
> &smdk5250_lcd, /* for platform_lcd device */
> + &exynos_drm_device,
> };
>
> static void __init exynos5250_dt_map_io(void)
> @@ -151,6 +177,7 @@ static void __init exynos5250_dt_machine_init(void)
> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> of_platform_populate(NULL, of_default_bus_match_table,
> exynos5250_auxdata_lookup, NULL);
> + exynos_fimd_gpio_setup_24bpp();
> platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> }
>
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 4/7] ARM: EXYNOS: Adding DRM platform device
@ 2012-07-20 7:33 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-20 7:33 UTC (permalink / raw)
To: linux-arm-kernel
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> Add DRM platform device to machine file for exynos5.
>
> Signed-off-by: Prathyush K <prathyush.k@samsung.com>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/mach-exynos5-dt.c | 27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 02a0e68..99f2b24 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -17,6 +17,7 @@
>
> #include <asm/mach/arch.h>
> #include <asm/hardware/gic.h>
> +#include <asm/io.h>
> #include <mach/map.h>
>
> #include <plat/cpu.h>
> @@ -27,6 +28,22 @@
> #include "common.h"
> #include <video/platform_lcd.h>
>
> +static void exynos_fimd_gpio_setup_24bpp(void)
The function name is wrong, this function doesn't control gpios.
> +{
> + unsigned int reg = 0;
> + /*
> + * Set DISP1BLK_CFG register for Display path selection
> + * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
> + * ---------------------
> + * 0 | MIE/MDNIE
> + * 1 | FIMD : selected
> + */
> + reg = __raw_readl(S3C_VA_SYS + 0x0214);
> + reg &= ~(1 << 15); /* To save other reset values */
> + reg |= (1 << 15);
> + __raw_writel(reg, S3C_VA_SYS + 0x0214);
> +}
If needs this, move to arch/arm/mach-exynos/setup-fimd0.c
> +
> static int smdk5250_bl_notify(struct device *unused, int brightness)
> {
> /* manage lcd_bl_en signal */
> @@ -49,6 +66,14 @@ static struct platform_pwm_backlight_data smdk5250_bl_data = {
> .notify = smdk5250_bl_notify,
> };
>
> +static struct platform_device exynos_drm_device = {
> + .name = "exynos-drm",
> + .dev = {
> + .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
> + .coherent_dma_mask = 0xffffffffUL,
> + }
> +};
> +
There is already exynos-drm device at the arch/arm/mach-exynos/dev-drm.c
> static void lcd_set_power(struct plat_lcd_data *pd,
> unsigned int power)
> {
> @@ -138,6 +163,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>
> static struct platform_device *smdk5250_devices[] __initdata = {
> &smdk5250_lcd, /* for platform_lcd device */
> + &exynos_drm_device,
> };
>
> static void __init exynos5250_dt_map_io(void)
> @@ -151,6 +177,7 @@ static void __init exynos5250_dt_machine_init(void)
> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> of_platform_populate(NULL, of_default_bus_match_table,
> exynos5250_auxdata_lookup, NULL);
> + exynos_fimd_gpio_setup_24bpp();
> platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> }
>
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 5/7] ARM: EXYNOS: add device tree based discovery support for FIMD
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
This patch adds support for device tree based discovery for Samsung's
display controller. Adds DRM-Fimd plat data for smdk5250
evt1 to the corresponding dts file
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 ++++++++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 7 +++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 ++
4 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..c8d32f5 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,20 @@
spi_2: spi@12d40000 {
status = "disabled";
};
+
+ lcd_fimd0: lcd_panel0 {
+ lcd-htiming = <4 4 4 1280>;
+ lcd-vtiming = <4 4 4 800>;
+ supports-mipi-panel;
+ };
+
+ fimd {
+ samsung,fimd-display = <&lcd_fimd0>;
+ samsung,fimd-vidout-rgb;
+ samsung,fimd-inv-vclk;
+ samsung,fimd-frame-rate = <60>;
+ samsung,default-window = <0>;
+ samsung,fimd-win-bpp = <32>;
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index a3a2eb2..3a67092 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -460,4 +460,11 @@
#gpio-cells = <4>;
};
};
+
+ fimd {
+ compatible = "samsung,exynos5-drm";
+ interrupt-parent = <&combiner>;
+ reg = <0x14400000 0x40000>;
+ interrupts = <18 5>, <18 4>, <18 6>;
+ };
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..f027da2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -170,6 +170,7 @@
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_FIMD0 0x11C00000
+#define EXYNOS5_PA_FIMD1 0x14400000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_DWMCI 0x12550000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 99f2b24..2107e01 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -158,6 +158,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-drm", EXYNOS5_PA_FIMD1,
+ "exynos5-fb", NULL),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 5/7] ARM: EXYNOS: add device tree based discovery support for FIMD
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for device tree based discovery for Samsung's
display controller. Adds DRM-Fimd plat data for smdk5250
evt1 to the corresponding dts file
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 ++++++++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 7 +++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 ++
4 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..c8d32f5 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,20 @@
spi_2: spi at 12d40000 {
status = "disabled";
};
+
+ lcd_fimd0: lcd_panel0 {
+ lcd-htiming = <4 4 4 1280>;
+ lcd-vtiming = <4 4 4 800>;
+ supports-mipi-panel;
+ };
+
+ fimd {
+ samsung,fimd-display = <&lcd_fimd0>;
+ samsung,fimd-vidout-rgb;
+ samsung,fimd-inv-vclk;
+ samsung,fimd-frame-rate = <60>;
+ samsung,default-window = <0>;
+ samsung,fimd-win-bpp = <32>;
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index a3a2eb2..3a67092 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -460,4 +460,11 @@
#gpio-cells = <4>;
};
};
+
+ fimd {
+ compatible = "samsung,exynos5-drm";
+ interrupt-parent = <&combiner>;
+ reg = <0x14400000 0x40000>;
+ interrupts = <18 5>, <18 4>, <18 6>;
+ };
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..f027da2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -170,6 +170,7 @@
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_FIMD0 0x11C00000
+#define EXYNOS5_PA_FIMD1 0x14400000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_DWMCI 0x12550000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 99f2b24..2107e01 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -158,6 +158,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-drm", EXYNOS5_PA_FIMD1,
+ "exynos5-fb", NULL),
{},
};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH V2 5/7] ARM: EXYNOS: add device tree based discovery support for FIMD
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-20 7:39 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-20 7:39 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> This patch adds support for device tree based discovery for Samsung's
> display controller. Adds DRM-Fimd plat data for smdk5250
> evt1 to the corresponding dts file
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 ++++++++++++++++
> arch/arm/boot/dts/exynos5250.dtsi | 7 +++++++
Please make separated patches for exynos5250.dtsi and
exynos5250-smdk5250.dts.
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/mach-exynos5-dt.c | 2 ++
> 4 files changed, 26 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 8a5e348..c8d32f5 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -109,4 +109,20 @@
> spi_2: spi@12d40000 {
> status = "disabled";
> };
> +
> + lcd_fimd0: lcd_panel0 {
> + lcd-htiming = <4 4 4 1280>;
> + lcd-vtiming = <4 4 4 800>;
> + supports-mipi-panel;
> + };
> +
> + fimd {
> + samsung,fimd-display = <&lcd_fimd0>;
> + samsung,fimd-vidout-rgb;
> + samsung,fimd-inv-vclk;
> + samsung,fimd-frame-rate = <60>;
> + samsung,default-window = <0>;
> + samsung,fimd-win-bpp = <32>;
> + };
> +
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index a3a2eb2..3a67092 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -460,4 +460,11 @@
> #gpio-cells = <4>;
> };
> };
> +
> + fimd {
> + compatible = "samsung,exynos5-drm";
> + interrupt-parent = <&combiner>;
> + reg = <0x14400000 0x40000>;
> + interrupts = <18 5>, <18 4>, <18 6>;
> + };
> };
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index c72b675..f027da2 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -170,6 +170,7 @@
> #define EXYNOS4_PA_MIPI_CSIS1 0x11890000
>
> #define EXYNOS4_PA_FIMD0 0x11C00000
> +#define EXYNOS5_PA_FIMD1 0x14400000
Is FIMD1 name right? I know exynos5250 has one FIMD, so use FIMD
postfix.
>
> #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
> #define EXYNOS4_PA_DWMCI 0x12550000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 99f2b24..2107e01 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -158,6 +158,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> + OF_DEV_AUXDATA("samsung,exynos5-drm", EXYNOS5_PA_FIMD1,
> + "exynos5-fb", NULL),
> {},
> };
>
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 5/7] ARM: EXYNOS: add device tree based discovery support for FIMD
@ 2012-07-20 7:39 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-20 7:39 UTC (permalink / raw)
To: linux-arm-kernel
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> This patch adds support for device tree based discovery for Samsung's
> display controller. Adds DRM-Fimd plat data for smdk5250
> evt1 to the corresponding dts file
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 ++++++++++++++++
> arch/arm/boot/dts/exynos5250.dtsi | 7 +++++++
Please make separated patches for exynos5250.dtsi and
exynos5250-smdk5250.dts.
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/mach-exynos5-dt.c | 2 ++
> 4 files changed, 26 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 8a5e348..c8d32f5 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -109,4 +109,20 @@
> spi_2: spi at 12d40000 {
> status = "disabled";
> };
> +
> + lcd_fimd0: lcd_panel0 {
> + lcd-htiming = <4 4 4 1280>;
> + lcd-vtiming = <4 4 4 800>;
> + supports-mipi-panel;
> + };
> +
> + fimd {
> + samsung,fimd-display = <&lcd_fimd0>;
> + samsung,fimd-vidout-rgb;
> + samsung,fimd-inv-vclk;
> + samsung,fimd-frame-rate = <60>;
> + samsung,default-window = <0>;
> + samsung,fimd-win-bpp = <32>;
> + };
> +
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index a3a2eb2..3a67092 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -460,4 +460,11 @@
> #gpio-cells = <4>;
> };
> };
> +
> + fimd {
> + compatible = "samsung,exynos5-drm";
> + interrupt-parent = <&combiner>;
> + reg = <0x14400000 0x40000>;
> + interrupts = <18 5>, <18 4>, <18 6>;
> + };
> };
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index c72b675..f027da2 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -170,6 +170,7 @@
> #define EXYNOS4_PA_MIPI_CSIS1 0x11890000
>
> #define EXYNOS4_PA_FIMD0 0x11C00000
> +#define EXYNOS5_PA_FIMD1 0x14400000
Is FIMD1 name right? I know exynos5250 has one FIMD, so use FIMD
postfix.
>
> #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
> #define EXYNOS4_PA_DWMCI 0x12550000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 99f2b24..2107e01 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -158,6 +158,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> + OF_DEV_AUXDATA("samsung,exynos5-drm", EXYNOS5_PA_FIMD1,
> + "exynos5-fb", NULL),
> {},
> };
>
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
This patch adds the bus clock for FIMD and changes
the device name for lcd clock
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..f001876 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 3),
}, {
+ .name = "fimd",
+ .devname = "exynos5-fb",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
.name = "iis",
.devname = "samsung-i2s.1",
.enable = exynos5_clk_ip_peric_ctrl,
@@ -1132,7 +1137,7 @@ static struct clksrc_clk exynos5_clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .devname = "s3cfb.1",
+ .devname = "exynos5-fb",
.enable = exynos5_clksrc_mask_disp1_0_ctrl,
.ctrlbit = (1 << 0),
},
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the bus clock for FIMD and changes
the device name for lcd clock
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..f001876 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 3),
}, {
+ .name = "fimd",
+ .devname = "exynos5-fb",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
.name = "iis",
.devname = "samsung-i2s.1",
.enable = exynos5_clk_ip_peric_ctrl,
@@ -1132,7 +1137,7 @@ static struct clksrc_clk exynos5_clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .devname = "s3cfb.1",
+ .devname = "exynos5-fb",
.enable = exynos5_clksrc_mask_disp1_0_ctrl,
.ctrlbit = (1 << 0),
},
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-23 8:34 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 8:34 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> This patch adds the bus clock for FIMD and changes
> the device name for lcd clock
Please refer below patch for exynos4.
http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> 1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index 774533c..f001876 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_disp1_ctrl,
> .ctrlbit = (1 << 3),
> }, {
> + .name = "fimd",
> + .devname = "exynos5-fb",
> + .enable = exynos5_clk_ip_disp1_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> .name = "iis",
> .devname = "samsung-i2s.1",
> .enable = exynos5_clk_ip_peric_ctrl,
> @@ -1132,7 +1137,7 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimd",
> - .devname = "s3cfb.1",
> + .devname = "exynos5-fb",
> .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> .ctrlbit = (1 << 0),
> },
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-23 8:34 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 8:34 UTC (permalink / raw)
To: linux-arm-kernel
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> This patch adds the bus clock for FIMD and changes
> the device name for lcd clock
Please refer below patch for exynos4.
http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> 1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index 774533c..f001876 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_disp1_ctrl,
> .ctrlbit = (1 << 3),
> }, {
> + .name = "fimd",
> + .devname = "exynos5-fb",
> + .enable = exynos5_clk_ip_disp1_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> .name = "iis",
> .devname = "samsung-i2s.1",
> .enable = exynos5_clk_ip_peric_ctrl,
> @@ -1132,7 +1137,7 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimd",
> - .devname = "s3cfb.1",
> + .devname = "exynos5-fb",
> .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> .ctrlbit = (1 << 0),
> },
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-23 8:34 ` Joonyoung Shim
@ 2012-07-23 9:54 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 9:54 UTC (permalink / raw)
Cc: Leela Krishna Amudala, kgene.kim, devicetree-discuss, jg1.han,
joshi, grant.likely, linux-samsung-soc, thomas.ab, olofj,
linux-arm-kernel
Hi, Jingoo.
On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>> This patch adds the bus clock for FIMD and changes
>> the device name for lcd clock
>
> Please refer below patch for exynos4.
>
> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>> b/arch/arm/mach-exynos/clock-exynos5.c
>> index 774533c..f001876 100644
>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>> .enable = exynos5_clk_ip_disp1_ctrl,
>> .ctrlbit = (1 << 3),
>> }, {
>> + .name = "fimd",
>> + .devname = "exynos5-fb",
>> + .enable = exynos5_clk_ip_disp1_ctrl,
>> + .ctrlbit = (1 << 0),
>> + }, {
With this patch, it causes below error at the DP driver because fimd
clock is disabled.
[ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
[ 0.210000] exynos-dp exynos-dp: unable to config video
[ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
I wonder fimd clock has any dependency with DP
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-23 9:54 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 9:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi, Jingoo.
On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>> This patch adds the bus clock for FIMD and changes
>> the device name for lcd clock
>
> Please refer below patch for exynos4.
>
> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>> b/arch/arm/mach-exynos/clock-exynos5.c
>> index 774533c..f001876 100644
>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>> .enable = exynos5_clk_ip_disp1_ctrl,
>> .ctrlbit = (1 << 3),
>> }, {
>> + .name = "fimd",
>> + .devname = "exynos5-fb",
>> + .enable = exynos5_clk_ip_disp1_ctrl,
>> + .ctrlbit = (1 << 0),
>> + }, {
With this patch, it causes below error at the DP driver because fimd
clock is disabled.
[ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
[ 0.210000] exynos-dp exynos-dp: unable to config video
[ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
I wonder fimd clock has any dependency with DP
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-23 9:54 ` Joonyoung Shim
@ 2012-07-23 23:14 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-23 23:14 UTC (permalink / raw)
To: 'Joonyoung Shim'
Cc: 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>
> Hi, Jingoo.
>
> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> > On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >> This patch adds the bus clock for FIMD and changes
> >> the device name for lcd clock
> >
> > Please refer below patch for exynos4.
> >
> > http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >> b/arch/arm/mach-exynos/clock-exynos5.c
> >> index 774533c..f001876 100644
> >> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >> .enable = exynos5_clk_ip_disp1_ctrl,
> >> .ctrlbit = (1 << 3),
> >> }, {
> >> + .name = "fimd",
> >> + .devname = "exynos5-fb",
> >> + .enable = exynos5_clk_ip_disp1_ctrl,
> >> + .ctrlbit = (1 << 0),
> >> + }, {
>
> With this patch, it causes below error at the DP driver because fimd
> clock is disabled.
>
> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> [ 0.210000] exynos-dp exynos-dp: unable to config video
> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>
> I wonder fimd clock has any dependency with DP
FIMD pixel clock is necessary to enable DP.
Best regards,
Jingoo Han
>
> Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-23 23:14 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-23 23:14 UTC (permalink / raw)
To: linux-arm-kernel
On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>
> Hi, Jingoo.
>
> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> > On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >> This patch adds the bus clock for FIMD and changes
> >> the device name for lcd clock
> >
> > Please refer below patch for exynos4.
> >
> > http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >> b/arch/arm/mach-exynos/clock-exynos5.c
> >> index 774533c..f001876 100644
> >> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >> .enable = exynos5_clk_ip_disp1_ctrl,
> >> .ctrlbit = (1 << 3),
> >> }, {
> >> + .name = "fimd",
> >> + .devname = "exynos5-fb",
> >> + .enable = exynos5_clk_ip_disp1_ctrl,
> >> + .ctrlbit = (1 << 0),
> >> + }, {
>
> With this patch, it causes below error at the DP driver because fimd
> clock is disabled.
>
> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> [ 0.210000] exynos-dp exynos-dp: unable to config video
> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>
> I wonder fimd clock has any dependency with DP
FIMD pixel clock is necessary to enable DP.
Best regards,
Jingoo Han
>
> Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-23 23:14 ` Jingoo Han
@ 2012-07-23 23:45 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 23:45 UTC (permalink / raw)
To: Jingoo Han
Cc: 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
On 07/24/2012 08:14 AM, Jingoo Han wrote:
> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>> Hi, Jingoo.
>>
>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>>>> This patch adds the bus clock for FIMD and changes
>>>> the device name for lcd clock
>>> Please refer below patch for exynos4.
>>>
>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>>>
>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>>> ---
>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>>> b/arch/arm/mach-exynos/clock-exynos5.c
>>>> index 774533c..f001876 100644
>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>> .enable = exynos5_clk_ip_disp1_ctrl,
>>>> .ctrlbit = (1 << 3),
>>>> }, {
>>>> + .name = "fimd",
>>>> + .devname = "exynos5-fb",
>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
>>>> + .ctrlbit = (1 << 0),
>>>> + }, {
>> With this patch, it causes below error at the DP driver because fimd
>> clock is disabled.
>>
>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
>> [ 0.210000] exynos-dp exynos-dp: unable to config video
>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>>
>> I wonder fimd clock has any dependency with DP
> FIMD pixel clock is necessary to enable DP.
So then, i think DP driver also should control FIMD pixel clock.
Do you have any patch or plan for it?
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-23 23:45 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 23:45 UTC (permalink / raw)
To: linux-arm-kernel
On 07/24/2012 08:14 AM, Jingoo Han wrote:
> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>> Hi, Jingoo.
>>
>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>>>> This patch adds the bus clock for FIMD and changes
>>>> the device name for lcd clock
>>> Please refer below patch for exynos4.
>>>
>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>>>
>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>>> ---
>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>>> b/arch/arm/mach-exynos/clock-exynos5.c
>>>> index 774533c..f001876 100644
>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>> .enable = exynos5_clk_ip_disp1_ctrl,
>>>> .ctrlbit = (1 << 3),
>>>> }, {
>>>> + .name = "fimd",
>>>> + .devname = "exynos5-fb",
>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
>>>> + .ctrlbit = (1 << 0),
>>>> + }, {
>> With this patch, it causes below error at the DP driver because fimd
>> clock is disabled.
>>
>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
>> [ 0.210000] exynos-dp exynos-dp: unable to config video
>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>>
>> I wonder fimd clock has any dependency with DP
> FIMD pixel clock is necessary to enable DP.
So then, i think DP driver also should control FIMD pixel clock.
Do you have any patch or plan for it?
^ permalink raw reply [flat|nested] 84+ messages in thread* RE: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-23 23:45 ` Joonyoung Shim
@ 2012-07-23 23:48 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-23 23:48 UTC (permalink / raw)
To: 'Joonyoung Shim'
Cc: 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim wrote:
>
> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> > On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >> Hi, Jingoo.
> >>
> >> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>> This patch adds the bus clock for FIMD and changes
> >>>> the device name for lcd clock
> >>> Please refer below patch for exynos4.
> >>>
> >>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>
> >>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >>>> ---
> >>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> index 774533c..f001876 100644
> >>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> .ctrlbit = (1 << 3),
> >>>> }, {
> >>>> + .name = "fimd",
> >>>> + .devname = "exynos5-fb",
> >>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> + .ctrlbit = (1 << 0),
> >>>> + }, {
> >> With this patch, it causes below error at the DP driver because fimd
> >> clock is disabled.
> >>
> >> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>
> >> I wonder fimd clock has any dependency with DP
> > FIMD pixel clock is necessary to enable DP.
>
> So then, i think DP driver also should control FIMD pixel clock.
> Do you have any patch or plan for it?
I have no plan.
Best regards,
Jingoo Han
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-23 23:48 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-23 23:48 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim wrote:
>
> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> > On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >> Hi, Jingoo.
> >>
> >> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>> This patch adds the bus clock for FIMD and changes
> >>>> the device name for lcd clock
> >>> Please refer below patch for exynos4.
> >>>
> >>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>
> >>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >>>> ---
> >>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> index 774533c..f001876 100644
> >>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> .ctrlbit = (1 << 3),
> >>>> }, {
> >>>> + .name = "fimd",
> >>>> + .devname = "exynos5-fb",
> >>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> + .ctrlbit = (1 << 0),
> >>>> + }, {
> >> With this patch, it causes below error at the DP driver because fimd
> >> clock is disabled.
> >>
> >> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>
> >> I wonder fimd clock has any dependency with DP
> > FIMD pixel clock is necessary to enable DP.
>
> So then, i think DP driver also should control FIMD pixel clock.
> Do you have any patch or plan for it?
I have no plan.
Best regards,
Jingoo Han
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread
[parent not found: <500DE22F.5010006-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]
* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-23 23:45 ` Joonyoung Shim
@ 2012-07-23 23:55 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-23 23:55 UTC (permalink / raw)
To: 'Joonyoung Shim'
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, 'Leela Krishna Amudala',
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
joshi-Sze3O3UU22JBDgjK7y7TUQ,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
thomas.ab-Sze3O3UU22JBDgjK7y7TUQ, olofj-hpIqsD4AKlfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
>
> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> > On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >> Hi, Jingoo.
> >>
> >> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>> This patch adds the bus clock for FIMD and changes
> >>>> the device name for lcd clock
> >>> Please refer below patch for exynos4.
> >>>
> >>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>
> >>>> Signed-off-by: Leela Krishna Amudala <l.krishna-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >>>> ---
> >>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> index 774533c..f001876 100644
> >>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> .ctrlbit = (1 << 3),
> >>>> }, {
> >>>> + .name = "fimd",
> >>>> + .devname = "exynos5-fb",
> >>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> + .ctrlbit = (1 << 0),
> >>>> + }, {
> >> With this patch, it causes below error at the DP driver because fimd
> >> clock is disabled.
> >>
> >> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>
> >> I wonder fimd clock has any dependency with DP
> > FIMD pixel clock is necessary to enable DP.
>
> So then, i think DP driver also should control FIMD pixel clock.
> Do you have any patch or plan for it?
Um, I don't think so.
Because, DP cannot work by itself.
In order to use DP, FIMD should be enabled.
If FIMD is enabled, FIMD pixel clock is enabled;
therefore, DP driver does not need to control FIMD pixel clock.
In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-23 23:55 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-23 23:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
>
> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> > On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >> Hi, Jingoo.
> >>
> >> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>> This patch adds the bus clock for FIMD and changes
> >>>> the device name for lcd clock
> >>> Please refer below patch for exynos4.
> >>>
> >>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>
> >>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >>>> ---
> >>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> index 774533c..f001876 100644
> >>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> .ctrlbit = (1 << 3),
> >>>> }, {
> >>>> + .name = "fimd",
> >>>> + .devname = "exynos5-fb",
> >>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>> + .ctrlbit = (1 << 0),
> >>>> + }, {
> >> With this patch, it causes below error at the DP driver because fimd
> >> clock is disabled.
> >>
> >> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>
> >> I wonder fimd clock has any dependency with DP
> > FIMD pixel clock is necessary to enable DP.
>
> So then, i think DP driver also should control FIMD pixel clock.
> Do you have any patch or plan for it?
Um, I don't think so.
Because, DP cannot work by itself.
In order to use DP, FIMD should be enabled.
If FIMD is enabled, FIMD pixel clock is enabled;
therefore, DP driver does not need to control FIMD pixel clock.
In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-23 23:55 ` Jingoo Han
@ 2012-07-24 1:55 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-24 1:55 UTC (permalink / raw)
To: Jingoo Han
Cc: 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
On 07/24/2012 08:55 AM, Jingoo Han wrote:
> On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
>> On 07/24/2012 08:14 AM, Jingoo Han wrote:
>>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>>>> Hi, Jingoo.
>>>>
>>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
>>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>>>>>> This patch adds the bus clock for FIMD and changes
>>>>>> the device name for lcd clock
>>>>> Please refer below patch for exynos4.
>>>>>
>>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>>>>>
>>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>>>>> ---
>>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> index 774533c..f001876 100644
>>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>> .ctrlbit = (1 << 3),
>>>>>> }, {
>>>>>> + .name = "fimd",
>>>>>> + .devname = "exynos5-fb",
>>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>> + .ctrlbit = (1 << 0),
>>>>>> + }, {
>>>> With this patch, it causes below error at the DP driver because fimd
>>>> clock is disabled.
>>>>
>>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
>>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
>>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>>>>
>>>> I wonder fimd clock has any dependency with DP
>>> FIMD pixel clock is necessary to enable DP.
>> So then, i think DP driver also should control FIMD pixel clock.
>> Do you have any patch or plan for it?
> Um, I don't think so.
> Because, DP cannot work by itself.
> In order to use DP, FIMD should be enabled.
>
> If FIMD is enabled, FIMD pixel clock is enabled;
> therefore, DP driver does not need to control FIMD pixel clock.
Why does DP driver have FIMD driver dependency? Also for this, it needs
FIMD driver is probed earlier then DP driver. We cannot decide driver
probe order if they are same level drivers and itself is weird
condition. Although there is hardware dependency, DP and FIMD driver
don't have any code relations. They are each other drivers. But DP
needs FIMD pixel clock and because the clock can be control at the
several drivers and the clock framework exists for that, then i think
it's better DP driver also control FIMD pixel clock.
>
> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
I think this is not solution. How do you ensure FIMD driver is probed
earlier than DP driver? Even if it's possible, when FIMD driver only
controls pixel clock, DP driver will execute any operations regardless
status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
then DP will occur any error.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-24 1:55 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-24 1:55 UTC (permalink / raw)
To: linux-arm-kernel
On 07/24/2012 08:55 AM, Jingoo Han wrote:
> On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
>> On 07/24/2012 08:14 AM, Jingoo Han wrote:
>>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>>>> Hi, Jingoo.
>>>>
>>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
>>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>>>>>> This patch adds the bus clock for FIMD and changes
>>>>>> the device name for lcd clock
>>>>> Please refer below patch for exynos4.
>>>>>
>>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>>>>>
>>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>>>>> ---
>>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> index 774533c..f001876 100644
>>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>> .ctrlbit = (1 << 3),
>>>>>> }, {
>>>>>> + .name = "fimd",
>>>>>> + .devname = "exynos5-fb",
>>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>> + .ctrlbit = (1 << 0),
>>>>>> + }, {
>>>> With this patch, it causes below error at the DP driver because fimd
>>>> clock is disabled.
>>>>
>>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
>>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
>>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>>>>
>>>> I wonder fimd clock has any dependency with DP
>>> FIMD pixel clock is necessary to enable DP.
>> So then, i think DP driver also should control FIMD pixel clock.
>> Do you have any patch or plan for it?
> Um, I don't think so.
> Because, DP cannot work by itself.
> In order to use DP, FIMD should be enabled.
>
> If FIMD is enabled, FIMD pixel clock is enabled;
> therefore, DP driver does not need to control FIMD pixel clock.
Why does DP driver have FIMD driver dependency? Also for this, it needs
FIMD driver is probed earlier then DP driver. We cannot decide driver
probe order if they are same level drivers and itself is weird
condition. Although there is hardware dependency, DP and FIMD driver
don't have any code relations. They are each other drivers. But DP
needs FIMD pixel clock and because the clock can be control at the
several drivers and the clock framework exists for that, then i think
it's better DP driver also control FIMD pixel clock.
>
> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
I think this is not solution. How do you ensure FIMD driver is probed
earlier than DP driver? Even if it's possible, when FIMD driver only
controls pixel clock, DP driver will execute any operations regardless
status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
then DP will occur any error.
^ permalink raw reply [flat|nested] 84+ messages in thread[parent not found: <500E00A3.8080203-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]
* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-24 1:55 ` Joonyoung Shim
@ 2012-07-24 2:15 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-24 2:15 UTC (permalink / raw)
To: 'Joonyoung Shim'
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ, 'Leela Krishna Amudala',
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
joshi-Sze3O3UU22JBDgjK7y7TUQ,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
thomas.ab-Sze3O3UU22JBDgjK7y7TUQ, olofj-hpIqsD4AKlfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Tuesday, July 24, 2012 10:56 AM, Joonyoung Shim Wrote:
>
> On 07/24/2012 08:55 AM, Jingoo Han wrote:
> > On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
> >> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> >>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >>>> Hi, Jingoo.
> >>>>
> >>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>>>> This patch adds the bus clock for FIMD and changes
> >>>>>> the device name for lcd clock
> >>>>> Please refer below patch for exynos4.
> >>>>>
> >>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>>>
> >>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> >>>>>> ---
> >>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>>>
> >>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> index 774533c..f001876 100644
> >>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>> .ctrlbit = (1 << 3),
> >>>>>> }, {
> >>>>>> + .name = "fimd",
> >>>>>> + .devname = "exynos5-fb",
> >>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>> + .ctrlbit = (1 << 0),
> >>>>>> + }, {
> >>>> With this patch, it causes below error at the DP driver because fimd
> >>>> clock is disabled.
> >>>>
> >>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>>>
> >>>> I wonder fimd clock has any dependency with DP
> >>> FIMD pixel clock is necessary to enable DP.
> >> So then, i think DP driver also should control FIMD pixel clock.
> >> Do you have any patch or plan for it?
> > Um, I don't think so.
> > Because, DP cannot work by itself.
> > In order to use DP, FIMD should be enabled.
> >
> > If FIMD is enabled, FIMD pixel clock is enabled;
> > therefore, DP driver does not need to control FIMD pixel clock.
>
> Why does DP driver have FIMD driver dependency? Also for this, it needs
> FIMD driver is probed earlier then DP driver. We cannot decide driver
> probe order if they are same level drivers and itself is weird
> condition. Although there is hardware dependency, DP and FIMD driver
> don't have any code relations. They are each other drivers. But DP
> needs FIMD pixel clock and because the clock can be control at the
> several drivers and the clock framework exists for that, then i think
> it's better DP driver also control FIMD pixel clock.
>
> >
> > In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
>
> I think this is not solution. How do you ensure FIMD driver is probed
> earlier than DP driver? Even if it's possible, when FIMD driver only
> controls pixel clock, DP driver will execute any operations regardless
> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
> then DP will occur any error.
late_initcall can ensure DP driver is probed later.
As you mentioned, DP controller does not work without FIMD controller.
Because FIMD controller should provide video data and video clock to DP controller.
In this case, adding config dependency would be good.
If FIMD driver turns off pixel clock, DP should be turned off too.
Currently, FB FIMD driver turns off pixel clock in remove() and suspend().
So, FIMD driver is enabled, DP will not occur any error on pixel clock.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-24 2:15 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-24 2:15 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, July 24, 2012 10:56 AM, Joonyoung Shim Wrote:
>
> On 07/24/2012 08:55 AM, Jingoo Han wrote:
> > On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
> >> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> >>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >>>> Hi, Jingoo.
> >>>>
> >>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>>>> This patch adds the bus clock for FIMD and changes
> >>>>>> the device name for lcd clock
> >>>>> Please refer below patch for exynos4.
> >>>>>
> >>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>>>
> >>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >>>>>> ---
> >>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>>>
> >>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> index 774533c..f001876 100644
> >>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>> .ctrlbit = (1 << 3),
> >>>>>> }, {
> >>>>>> + .name = "fimd",
> >>>>>> + .devname = "exynos5-fb",
> >>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>> + .ctrlbit = (1 << 0),
> >>>>>> + }, {
> >>>> With this patch, it causes below error at the DP driver because fimd
> >>>> clock is disabled.
> >>>>
> >>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>>>
> >>>> I wonder fimd clock has any dependency with DP
> >>> FIMD pixel clock is necessary to enable DP.
> >> So then, i think DP driver also should control FIMD pixel clock.
> >> Do you have any patch or plan for it?
> > Um, I don't think so.
> > Because, DP cannot work by itself.
> > In order to use DP, FIMD should be enabled.
> >
> > If FIMD is enabled, FIMD pixel clock is enabled;
> > therefore, DP driver does not need to control FIMD pixel clock.
>
> Why does DP driver have FIMD driver dependency? Also for this, it needs
> FIMD driver is probed earlier then DP driver. We cannot decide driver
> probe order if they are same level drivers and itself is weird
> condition. Although there is hardware dependency, DP and FIMD driver
> don't have any code relations. They are each other drivers. But DP
> needs FIMD pixel clock and because the clock can be control at the
> several drivers and the clock framework exists for that, then i think
> it's better DP driver also control FIMD pixel clock.
>
> >
> > In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
>
> I think this is not solution. How do you ensure FIMD driver is probed
> earlier than DP driver? Even if it's possible, when FIMD driver only
> controls pixel clock, DP driver will execute any operations regardless
> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
> then DP will occur any error.
late_initcall can ensure DP driver is probed later.
As you mentioned, DP controller does not work without FIMD controller.
Because FIMD controller should provide video data and video clock to DP controller.
In this case, adding config dependency would be good.
If FIMD driver turns off pixel clock, DP should be turned off too.
Currently, FB FIMD driver turns off pixel clock in remove() and suspend().
So, FIMD driver is enabled, DP will not occur any error on pixel clock.
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-24 2:15 ` Jingoo Han
@ 2012-07-24 3:06 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-24 3:06 UTC (permalink / raw)
To: Jingoo Han
Cc: 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
On 07/24/2012 11:15 AM, Jingoo Han wrote:
> On Tuesday, July 24, 2012 10:56 AM, Joonyoung Shim Wrote:
>> On 07/24/2012 08:55 AM, Jingoo Han wrote:
>>> On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
>>>> On 07/24/2012 08:14 AM, Jingoo Han wrote:
>>>>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>>>>>> Hi, Jingoo.
>>>>>>
>>>>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
>>>>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>>>>>>>> This patch adds the bus clock for FIMD and changes
>>>>>>>> the device name for lcd clock
>>>>>>> Please refer below patch for exynos4.
>>>>>>>
>>>>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>>>>>>>
>>>>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>>>>>>> ---
>>>>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>>>>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> index 774533c..f001876 100644
>>>>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>>>> .ctrlbit = (1 << 3),
>>>>>>>> }, {
>>>>>>>> + .name = "fimd",
>>>>>>>> + .devname = "exynos5-fb",
>>>>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>>>> + .ctrlbit = (1 << 0),
>>>>>>>> + }, {
>>>>>> With this patch, it causes below error at the DP driver because fimd
>>>>>> clock is disabled.
>>>>>>
>>>>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
>>>>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
>>>>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>>>>>>
>>>>>> I wonder fimd clock has any dependency with DP
>>>>> FIMD pixel clock is necessary to enable DP.
>>>> So then, i think DP driver also should control FIMD pixel clock.
>>>> Do you have any patch or plan for it?
>>> Um, I don't think so.
>>> Because, DP cannot work by itself.
>>> In order to use DP, FIMD should be enabled.
>>>
>>> If FIMD is enabled, FIMD pixel clock is enabled;
>>> therefore, DP driver does not need to control FIMD pixel clock.
>> Why does DP driver have FIMD driver dependency? Also for this, it needs
>> FIMD driver is probed earlier then DP driver. We cannot decide driver
>> probe order if they are same level drivers and itself is weird
>> condition. Although there is hardware dependency, DP and FIMD driver
>> don't have any code relations. They are each other drivers. But DP
>> needs FIMD pixel clock and because the clock can be control at the
>> several drivers and the clock framework exists for that, then i think
>> it's better DP driver also control FIMD pixel clock.
>>
>>> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
>> I think this is not solution. How do you ensure FIMD driver is probed
>> earlier than DP driver? Even if it's possible, when FIMD driver only
>> controls pixel clock, DP driver will execute any operations regardless
>> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
>> then DP will occur any error.
> late_initcall can ensure DP driver is probed later.
I'm not sure late_initcall solution is good. It must choose at the last
if there isn't other way really.
>
> As you mentioned, DP controller does not work without FIMD controller.
> Because FIMD controller should provide video data and video clock to DP controller.
> In this case, adding config dependency would be good.
>
> If FIMD driver turns off pixel clock, DP should be turned off too.
This means DP driver should know FIMD status.
> Currently, FB FIMD driver turns off pixel clock in remove() and suspend().
You should also consider blank operation and runtime suspend / resume.
> So, FIMD driver is enabled, DP will not occur any error on pixel clock.
>
Anyway i want to be solved early.
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-24 3:06 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-24 3:06 UTC (permalink / raw)
To: linux-arm-kernel
On 07/24/2012 11:15 AM, Jingoo Han wrote:
> On Tuesday, July 24, 2012 10:56 AM, Joonyoung Shim Wrote:
>> On 07/24/2012 08:55 AM, Jingoo Han wrote:
>>> On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
>>>> On 07/24/2012 08:14 AM, Jingoo Han wrote:
>>>>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
>>>>>> Hi, Jingoo.
>>>>>>
>>>>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
>>>>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
>>>>>>>> This patch adds the bus clock for FIMD and changes
>>>>>>>> the device name for lcd clock
>>>>>>> Please refer below patch for exynos4.
>>>>>>>
>>>>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
>>>>>>>
>>>>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>>>>>>> ---
>>>>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
>>>>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> index 774533c..f001876 100644
>>>>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>>>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>>>> .ctrlbit = (1 << 3),
>>>>>>>> }, {
>>>>>>>> + .name = "fimd",
>>>>>>>> + .devname = "exynos5-fb",
>>>>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
>>>>>>>> + .ctrlbit = (1 << 0),
>>>>>>>> + }, {
>>>>>> With this patch, it causes below error at the DP driver because fimd
>>>>>> clock is disabled.
>>>>>>
>>>>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
>>>>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
>>>>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
>>>>>>
>>>>>> I wonder fimd clock has any dependency with DP
>>>>> FIMD pixel clock is necessary to enable DP.
>>>> So then, i think DP driver also should control FIMD pixel clock.
>>>> Do you have any patch or plan for it?
>>> Um, I don't think so.
>>> Because, DP cannot work by itself.
>>> In order to use DP, FIMD should be enabled.
>>>
>>> If FIMD is enabled, FIMD pixel clock is enabled;
>>> therefore, DP driver does not need to control FIMD pixel clock.
>> Why does DP driver have FIMD driver dependency? Also for this, it needs
>> FIMD driver is probed earlier then DP driver. We cannot decide driver
>> probe order if they are same level drivers and itself is weird
>> condition. Although there is hardware dependency, DP and FIMD driver
>> don't have any code relations. They are each other drivers. But DP
>> needs FIMD pixel clock and because the clock can be control at the
>> several drivers and the clock framework exists for that, then i think
>> it's better DP driver also control FIMD pixel clock.
>>
>>> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
>> I think this is not solution. How do you ensure FIMD driver is probed
>> earlier than DP driver? Even if it's possible, when FIMD driver only
>> controls pixel clock, DP driver will execute any operations regardless
>> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
>> then DP will occur any error.
> late_initcall can ensure DP driver is probed later.
I'm not sure late_initcall solution is good. It must choose at the last
if there isn't other way really.
>
> As you mentioned, DP controller does not work without FIMD controller.
> Because FIMD controller should provide video data and video clock to DP controller.
> In this case, adding config dependency would be good.
>
> If FIMD driver turns off pixel clock, DP should be turned off too.
This means DP driver should know FIMD status.
> Currently, FB FIMD driver turns off pixel clock in remove() and suspend().
You should also consider blank operation and runtime suspend / resume.
> So, FIMD driver is enabled, DP will not occur any error on pixel clock.
>
Anyway i want to be solved early.
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-24 3:06 ` Joonyoung Shim
@ 2012-07-24 4:02 ` Jingoo Han
-1 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-24 4:02 UTC (permalink / raw)
To: 'Joonyoung Shim'
Cc: 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
On Tuesday, July 24, 2012 12:06 PM, Joonyoung Shim Wrote:
>
> On 07/24/2012 11:15 AM, Jingoo Han wrote:
> > On Tuesday, July 24, 2012 10:56 AM, Joonyoung Shim Wrote:
> >> On 07/24/2012 08:55 AM, Jingoo Han wrote:
> >>> On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
> >>>> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> >>>>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >>>>>> Hi, Jingoo.
> >>>>>>
> >>>>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>>>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>>>>>> This patch adds the bus clock for FIMD and changes
> >>>>>>>> the device name for lcd clock
> >>>>>>> Please refer below patch for exynos4.
> >>>>>>>
> >>>>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>>>>>
> >>>>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >>>>>>>> ---
> >>>>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>>>>>
> >>>>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> index 774533c..f001876 100644
> >>>>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>>>> .ctrlbit = (1 << 3),
> >>>>>>>> }, {
> >>>>>>>> + .name = "fimd",
> >>>>>>>> + .devname = "exynos5-fb",
> >>>>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>>>> + .ctrlbit = (1 << 0),
> >>>>>>>> + }, {
> >>>>>> With this patch, it causes below error at the DP driver because fimd
> >>>>>> clock is disabled.
> >>>>>>
> >>>>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >>>>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >>>>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>>>>>
> >>>>>> I wonder fimd clock has any dependency with DP
> >>>>> FIMD pixel clock is necessary to enable DP.
> >>>> So then, i think DP driver also should control FIMD pixel clock.
> >>>> Do you have any patch or plan for it?
> >>> Um, I don't think so.
> >>> Because, DP cannot work by itself.
> >>> In order to use DP, FIMD should be enabled.
> >>>
> >>> If FIMD is enabled, FIMD pixel clock is enabled;
> >>> therefore, DP driver does not need to control FIMD pixel clock.
> >> Why does DP driver have FIMD driver dependency? Also for this, it needs
> >> FIMD driver is probed earlier then DP driver. We cannot decide driver
> >> probe order if they are same level drivers and itself is weird
> >> condition. Although there is hardware dependency, DP and FIMD driver
> >> don't have any code relations. They are each other drivers. But DP
> >> needs FIMD pixel clock and because the clock can be control at the
> >> several drivers and the clock framework exists for that, then i think
> >> it's better DP driver also control FIMD pixel clock.
> >>
> >>> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
> >> I think this is not solution. How do you ensure FIMD driver is probed
> >> earlier than DP driver? Even if it's possible, when FIMD driver only
> >> controls pixel clock, DP driver will execute any operations regardless
> >> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
> >> then DP will occur any error.
> > late_initcall can ensure DP driver is probed later.
>
> I'm not sure late_initcall solution is good. It must choose at the last
> if there isn't other way really.
late_initcall is already used by many drivers.
If you have any good idea, please, suggest it.
>
> >
> > As you mentioned, DP controller does not work without FIMD controller.
> > Because FIMD controller should provide video data and video clock to DP controller.
> > In this case, adding config dependency would be good.
> >
> > If FIMD driver turns off pixel clock, DP should be turned off too.
>
> This means DP driver should know FIMD status.
>
> > Currently, FB FIMD driver turns off pixel clock in remove() and suspend().
>
> You should also consider blank operation and runtime suspend / resume.
Um, other people can submit this patch, then I will review it.
Please don't urge me to do what.
That's it.
>
> > So, FIMD driver is enabled, DP will not occur any error on pixel clock.
> >
>
> Anyway i want to be solved early.
>
> Thanks.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-24 4:02 ` Jingoo Han
0 siblings, 0 replies; 84+ messages in thread
From: Jingoo Han @ 2012-07-24 4:02 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, July 24, 2012 12:06 PM, Joonyoung Shim Wrote:
>
> On 07/24/2012 11:15 AM, Jingoo Han wrote:
> > On Tuesday, July 24, 2012 10:56 AM, Joonyoung Shim Wrote:
> >> On 07/24/2012 08:55 AM, Jingoo Han wrote:
> >>> On Tuesday, July 24, 2012 8:46 AM, Joonyoung Shim Wrote:
> >>>> On 07/24/2012 08:14 AM, Jingoo Han wrote:
> >>>>> On Monday, July 23, 2012 6:55 PM, Joonyoung Shim wrote:
> >>>>>> Hi, Jingoo.
> >>>>>>
> >>>>>> On 07/23/2012 05:34 PM, Joonyoung Shim wrote:
> >>>>>>> On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> >>>>>>>> This patch adds the bus clock for FIMD and changes
> >>>>>>>> the device name for lcd clock
> >>>>>>> Please refer below patch for exynos4.
> >>>>>>>
> >>>>>>> http://lists.linaro.org/pipermail/linaro-dev/2011-December/008872.html
> >>>>>>>
> >>>>>>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >>>>>>>> ---
> >>>>>>>> arch/arm/mach-exynos/clock-exynos5.c | 7 ++++++-
> >>>>>>>> 1 files changed, 6 insertions(+), 1 deletions(-)
> >>>>>>>>
> >>>>>>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> index 774533c..f001876 100644
> >>>>>>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> >>>>>>>> @@ -634,6 +634,11 @@ static struct clk exynos5_init_clocks_off[] = {
> >>>>>>>> .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>>>> .ctrlbit = (1 << 3),
> >>>>>>>> }, {
> >>>>>>>> + .name = "fimd",
> >>>>>>>> + .devname = "exynos5-fb",
> >>>>>>>> + .enable = exynos5_clk_ip_disp1_ctrl,
> >>>>>>>> + .ctrlbit = (1 << 0),
> >>>>>>>> + }, {
> >>>>>> With this patch, it causes below error at the DP driver because fimd
> >>>>>> clock is disabled.
> >>>>>>
> >>>>>> [ 0.210000] exynos-dp exynos-dp: Timeout of video streamclk ok
> >>>>>> [ 0.210000] exynos-dp exynos-dp: unable to config video
> >>>>>> [ 0.210000] exynos-dp: probe of exynos-dp failed with error -110
> >>>>>>
> >>>>>> I wonder fimd clock has any dependency with DP
> >>>>> FIMD pixel clock is necessary to enable DP.
> >>>> So then, i think DP driver also should control FIMD pixel clock.
> >>>> Do you have any patch or plan for it?
> >>> Um, I don't think so.
> >>> Because, DP cannot work by itself.
> >>> In order to use DP, FIMD should be enabled.
> >>>
> >>> If FIMD is enabled, FIMD pixel clock is enabled;
> >>> therefore, DP driver does not need to control FIMD pixel clock.
> >> Why does DP driver have FIMD driver dependency? Also for this, it needs
> >> FIMD driver is probed earlier then DP driver. We cannot decide driver
> >> probe order if they are same level drivers and itself is weird
> >> condition. Although there is hardware dependency, DP and FIMD driver
> >> don't have any code relations. They are each other drivers. But DP
> >> needs FIMD pixel clock and because the clock can be control at the
> >> several drivers and the clock framework exists for that, then i think
> >> it's better DP driver also control FIMD pixel clock.
> >>
> >>> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
> >> I think this is not solution. How do you ensure FIMD driver is probed
> >> earlier than DP driver? Even if it's possible, when FIMD driver only
> >> controls pixel clock, DP driver will execute any operations regardless
> >> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
> >> then DP will occur any error.
> > late_initcall can ensure DP driver is probed later.
>
> I'm not sure late_initcall solution is good. It must choose at the last
> if there isn't other way really.
late_initcall is already used by many drivers.
If you have any good idea, please, suggest it.
>
> >
> > As you mentioned, DP controller does not work without FIMD controller.
> > Because FIMD controller should provide video data and video clock to DP controller.
> > In this case, adding config dependency would be good.
> >
> > If FIMD driver turns off pixel clock, DP should be turned off too.
>
> This means DP driver should know FIMD status.
>
> > Currently, FB FIMD driver turns off pixel clock in remove() and suspend().
>
> You should also consider blank operation and runtime suspend / resume.
Um, other people can submit this patch, then I will review it.
Please don't urge me to do what.
That's it.
>
> > So, FIMD driver is enabled, DP will not occur any error on pixel clock.
> >
>
> Anyway i want to be solved early.
>
> Thanks.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
2012-07-24 4:02 ` Jingoo Han
@ 2012-07-24 9:13 ` Sylwester Nawrocki
-1 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-24 9:13 UTC (permalink / raw)
To: Jingoo Han
Cc: 'Joonyoung Shim', 'Leela Krishna Amudala',
kgene.kim, devicetree-discuss, joshi, grant.likely,
linux-samsung-soc, thomas.ab, olofj, linux-arm-kernel
Hi,
On 07/24/2012 06:02 AM, Jingoo Han wrote:
>>>>>>>> I wonder fimd clock has any dependency with DP
>>>>>>> FIMD pixel clock is necessary to enable DP.
>>>>>> So then, i think DP driver also should control FIMD pixel clock.
>>>>>> Do you have any patch or plan for it?
>>>>> Um, I don't think so.
>>>>> Because, DP cannot work by itself.
>>>>> In order to use DP, FIMD should be enabled.
>>>>>
>>>>> If FIMD is enabled, FIMD pixel clock is enabled;
>>>>> therefore, DP driver does not need to control FIMD pixel clock.
>>>> Why does DP driver have FIMD driver dependency? Also for this, it needs
>>>> FIMD driver is probed earlier then DP driver. We cannot decide driver
>>>> probe order if they are same level drivers and itself is weird
>>>> condition. Although there is hardware dependency, DP and FIMD driver
>>>> don't have any code relations. They are each other drivers. But DP
>>>> needs FIMD pixel clock and because the clock can be control at the
>>>> several drivers and the clock framework exists for that, then i think
>>>> it's better DP driver also control FIMD pixel clock.
>>>>
>>>>> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
>>>> I think this is not solution. How do you ensure FIMD driver is probed
>>>> earlier than DP driver? Even if it's possible, when FIMD driver only
>>>> controls pixel clock, DP driver will execute any operations regardless
>>>> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
>>>> then DP will occur any error.
>>> late_initcall can ensure DP driver is probed later.
>>
>> I'm not sure late_initcall solution is good. It must choose at the last
>> if there isn't other way really.
>
>
> late_initcall is already used by many drivers.
> If you have any good idea, please, suggest it.
I agree with Mr. Shim here. using initcall doesn't look like a solution
to this issue. Neither compile time dependency is of much help.
The S3C framebuffer driver can be used as a loadable module, how
would initcalls be supposed to work then ?
Some notify mechanisms or deferred probing could be used, to make sure one
of drivers is initialized before the other.
--
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 6/7] ARM: EXYNOS5: Add the bus clock for FIMD
@ 2012-07-24 9:13 ` Sylwester Nawrocki
0 siblings, 0 replies; 84+ messages in thread
From: Sylwester Nawrocki @ 2012-07-24 9:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 07/24/2012 06:02 AM, Jingoo Han wrote:
>>>>>>>> I wonder fimd clock has any dependency with DP
>>>>>>> FIMD pixel clock is necessary to enable DP.
>>>>>> So then, i think DP driver also should control FIMD pixel clock.
>>>>>> Do you have any patch or plan for it?
>>>>> Um, I don't think so.
>>>>> Because, DP cannot work by itself.
>>>>> In order to use DP, FIMD should be enabled.
>>>>>
>>>>> If FIMD is enabled, FIMD pixel clock is enabled;
>>>>> therefore, DP driver does not need to control FIMD pixel clock.
>>>> Why does DP driver have FIMD driver dependency? Also for this, it needs
>>>> FIMD driver is probed earlier then DP driver. We cannot decide driver
>>>> probe order if they are same level drivers and itself is weird
>>>> condition. Although there is hardware dependency, DP and FIMD driver
>>>> don't have any code relations. They are each other drivers. But DP
>>>> needs FIMD pixel clock and because the clock can be control at the
>>>> several drivers and the clock framework exists for that, then i think
>>>> it's better DP driver also control FIMD pixel clock.
>>>>
>>>>> In my opinion, adding config dependency would be better, such as FB_S3C or DRM_EXYNOS_FIMD.
>>>> I think this is not solution. How do you ensure FIMD driver is probed
>>>> earlier than DP driver? Even if it's possible, when FIMD driver only
>>>> controls pixel clock, DP driver will execute any operations regardless
>>>> status of FIMD pixel clock, so if FIMD driver turns off pixel clock,
>>>> then DP will occur any error.
>>> late_initcall can ensure DP driver is probed later.
>>
>> I'm not sure late_initcall solution is good. It must choose at the last
>> if there isn't other way really.
>
>
> late_initcall is already used by many drivers.
> If you have any good idea, please, suggest it.
I agree with Mr. Shim here. using initcall doesn't look like a solution
to this issue. Neither compile time dependency is of much help.
The S3C framebuffer driver can be used as a loadable module, how
would initcalls be supposed to work then ?
Some notify mechanisms or deferred probing could be used, to make sure one
of drivers is initialized before the other.
--
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH V2 7/7] ARM: EXYNOS5: Set parent clock to fimd
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-18 5:57 ` Leela Krishna Amudala
-1 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
Cc: linux-samsung-soc, grant.likely, olofj, thomas.ab, kgene.kim,
joshi, jg1.han
This patch sets mout_mpll_user as parent clock to fimd also
sets Fimd source clock rate to 800 MHz for MIPI LCD
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++----------
arch/arm/mach-exynos/mach-exynos5-dt.c | 11 +++++++++++
arch/arm/plat-samsung/include/plat/clock.h | 2 ++
3 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index f001876..8c20c4d 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -1125,6 +1125,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
};
+struct clksrc_clk exynos5_clk_sclk_fimd = {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos5-fb",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1136,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
}, {
.clk = {
- .name = "sclk_fimd",
- .devname = "exynos5-fb",
- .enable = exynos5_clksrc_mask_disp1_0_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &exynos5_clkset_group,
- .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
- .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
- }, {
- .clk = {
.name = "aclk_266_gscl",
},
.sources = &clk_src_gscl_266,
@@ -1245,6 +1247,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mdout_spi0,
&exynos5_clk_mdout_spi1,
&exynos5_clk_mdout_spi2,
+ &exynos5_clk_sclk_fimd,
};
static struct clk *exynos5_clk_cdev[] = {
@@ -1497,6 +1500,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+ clk_set_parent(&exynos5_clk_sclk_fimd.clk,
+ &exynos5_clk_mout_mpll_user.clk);
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 2107e01..19f3724 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -24,6 +24,9 @@
#include <plat/regs-serial.h>
#include <plat/backlight.h>
#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
#include "common.h"
#include <video/platform_lcd.h>
@@ -176,9 +179,17 @@ static void __init exynos5250_dt_map_io(void)
static void __init exynos5250_dt_machine_init(void)
{
+ struct device_node *fimd_node;
+
samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+
+ fimd_node = of_find_node_with_property(NULL, "supports-mipi-panel");
+ if (of_get_property(fimd_node, "supports-mipi-panel", NULL))
+ clk_set_rate(&exynos5_clk_sclk_fimd.clk, 800000000);
+ of_node_put(fimd_node);
+
exynos_fimd_gpio_setup_24bpp();
platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
}
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index a62753d..3d27783 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -83,6 +83,8 @@ extern struct clk clk_ext;
extern struct clksrc_clk clk_epllref;
extern struct clksrc_clk clk_esysclk;
+extern struct clksrc_clk exynos5_clk_sclk_fimd;
+
/* S3C64XX specific clocks */
extern struct clk clk_h2;
extern struct clk clk_27m;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH V2 7/7] ARM: EXYNOS5: Set parent clock to fimd
@ 2012-07-18 5:57 ` Leela Krishna Amudala
0 siblings, 0 replies; 84+ messages in thread
From: Leela Krishna Amudala @ 2012-07-18 5:57 UTC (permalink / raw)
To: linux-arm-kernel
This patch sets mout_mpll_user as parent clock to fimd also
sets Fimd source clock rate to 800 MHz for MIPI LCD
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++----------
arch/arm/mach-exynos/mach-exynos5-dt.c | 11 +++++++++++
arch/arm/plat-samsung/include/plat/clock.h | 2 ++
3 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index f001876..8c20c4d 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -1125,6 +1125,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
};
+struct clksrc_clk exynos5_clk_sclk_fimd = {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos5-fb",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1136,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
}, {
.clk = {
- .name = "sclk_fimd",
- .devname = "exynos5-fb",
- .enable = exynos5_clksrc_mask_disp1_0_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &exynos5_clkset_group,
- .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
- .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
- }, {
- .clk = {
.name = "aclk_266_gscl",
},
.sources = &clk_src_gscl_266,
@@ -1245,6 +1247,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mdout_spi0,
&exynos5_clk_mdout_spi1,
&exynos5_clk_mdout_spi2,
+ &exynos5_clk_sclk_fimd,
};
static struct clk *exynos5_clk_cdev[] = {
@@ -1497,6 +1500,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+ clk_set_parent(&exynos5_clk_sclk_fimd.clk,
+ &exynos5_clk_mout_mpll_user.clk);
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 2107e01..19f3724 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -24,6 +24,9 @@
#include <plat/regs-serial.h>
#include <plat/backlight.h>
#include <plat/gpio-cfg.h>
+#include <plat/clock.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
#include "common.h"
#include <video/platform_lcd.h>
@@ -176,9 +179,17 @@ static void __init exynos5250_dt_map_io(void)
static void __init exynos5250_dt_machine_init(void)
{
+ struct device_node *fimd_node;
+
samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+
+ fimd_node = of_find_node_with_property(NULL, "supports-mipi-panel");
+ if (of_get_property(fimd_node, "supports-mipi-panel", NULL))
+ clk_set_rate(&exynos5_clk_sclk_fimd.clk, 800000000);
+ of_node_put(fimd_node);
+
exynos_fimd_gpio_setup_24bpp();
platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
}
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index a62753d..3d27783 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -83,6 +83,8 @@ extern struct clk clk_ext;
extern struct clksrc_clk clk_epllref;
extern struct clksrc_clk clk_esysclk;
+extern struct clksrc_clk exynos5_clk_sclk_fimd;
+
/* S3C64XX specific clocks */
extern struct clk clk_h2;
extern struct clk clk_27m;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH V2 7/7] ARM: EXYNOS5: Set parent clock to fimd
2012-07-18 5:57 ` Leela Krishna Amudala
@ 2012-07-23 8:41 ` Joonyoung Shim
-1 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 8:41 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: devicetree-discuss, linux-arm-kernel, kgene.kim, jg1.han, joshi,
grant.likely, linux-samsung-soc, thomas.ab, olofj
Hi, Leela.
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> This patch sets mout_mpll_user as parent clock to fimd also
> sets Fimd source clock rate to 800 MHz for MIPI LCD
Don't decide parent clock at the common clock codes.
Thanks.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++----------
> arch/arm/mach-exynos/mach-exynos5-dt.c | 11 +++++++++++
> arch/arm/plat-samsung/include/plat/clock.h | 2 ++
> 3 files changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index f001876..8c20c4d 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -1125,6 +1125,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
> };
>
> +struct clksrc_clk exynos5_clk_sclk_fimd = {
> + .clk = {
> + .name = "sclk_fimd",
> + .devname = "exynos5-fb",
> + .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> + .ctrlbit = (1 << 0),
> + },
> + .sources = &exynos5_clkset_group,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> +};
> +
> static struct clksrc_clk exynos5_clksrcs[] = {
> {
> .clk = {
> @@ -1136,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
> }, {
> .clk = {
> - .name = "sclk_fimd",
> - .devname = "exynos5-fb",
> - .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> - .ctrlbit = (1 << 0),
> - },
> - .sources = &exynos5_clkset_group,
> - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> - }, {
> - .clk = {
> .name = "aclk_266_gscl",
> },
> .sources = &clk_src_gscl_266,
> @@ -1245,6 +1247,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_mdout_spi0,
> &exynos5_clk_mdout_spi1,
> &exynos5_clk_mdout_spi2,
> + &exynos5_clk_sclk_fimd,
> };
>
> static struct clk *exynos5_clk_cdev[] = {
> @@ -1497,6 +1500,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
>
> clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
> clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
> + clk_set_parent(&exynos5_clk_sclk_fimd.clk,
> + &exynos5_clk_mout_mpll_user.clk);
>
> for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
> s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 2107e01..19f3724 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -24,6 +24,9 @@
> #include <plat/regs-serial.h>
> #include <plat/backlight.h>
> #include <plat/gpio-cfg.h>
> +#include <plat/clock.h>
> +#include <plat/s5p-clock.h>
> +#include <plat/clock-clksrc.h>
>
> #include "common.h"
> #include <video/platform_lcd.h>
> @@ -176,9 +179,17 @@ static void __init exynos5250_dt_map_io(void)
>
> static void __init exynos5250_dt_machine_init(void)
> {
> + struct device_node *fimd_node;
> +
> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> of_platform_populate(NULL, of_default_bus_match_table,
> exynos5250_auxdata_lookup, NULL);
> +
> + fimd_node = of_find_node_with_property(NULL, "supports-mipi-panel");
> + if (of_get_property(fimd_node, "supports-mipi-panel", NULL))
> + clk_set_rate(&exynos5_clk_sclk_fimd.clk, 800000000);
> + of_node_put(fimd_node);
> +
> exynos_fimd_gpio_setup_24bpp();
> platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> }
> diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
> index a62753d..3d27783 100644
> --- a/arch/arm/plat-samsung/include/plat/clock.h
> +++ b/arch/arm/plat-samsung/include/plat/clock.h
> @@ -83,6 +83,8 @@ extern struct clk clk_ext;
> extern struct clksrc_clk clk_epllref;
> extern struct clksrc_clk clk_esysclk;
>
> +extern struct clksrc_clk exynos5_clk_sclk_fimd;
> +
> /* S3C64XX specific clocks */
> extern struct clk clk_h2;
> extern struct clk clk_27m;
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH V2 7/7] ARM: EXYNOS5: Set parent clock to fimd
@ 2012-07-23 8:41 ` Joonyoung Shim
0 siblings, 0 replies; 84+ messages in thread
From: Joonyoung Shim @ 2012-07-23 8:41 UTC (permalink / raw)
To: linux-arm-kernel
Hi, Leela.
On 07/18/2012 02:57 PM, Leela Krishna Amudala wrote:
> This patch sets mout_mpll_user as parent clock to fimd also
> sets Fimd source clock rate to 800 MHz for MIPI LCD
Don't decide parent clock at the common clock codes.
Thanks.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++----------
> arch/arm/mach-exynos/mach-exynos5-dt.c | 11 +++++++++++
> arch/arm/plat-samsung/include/plat/clock.h | 2 ++
> 3 files changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index f001876..8c20c4d 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -1125,6 +1125,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
> };
>
> +struct clksrc_clk exynos5_clk_sclk_fimd = {
> + .clk = {
> + .name = "sclk_fimd",
> + .devname = "exynos5-fb",
> + .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> + .ctrlbit = (1 << 0),
> + },
> + .sources = &exynos5_clkset_group,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> +};
> +
> static struct clksrc_clk exynos5_clksrcs[] = {
> {
> .clk = {
> @@ -1136,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
> }, {
> .clk = {
> - .name = "sclk_fimd",
> - .devname = "exynos5-fb",
> - .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> - .ctrlbit = (1 << 0),
> - },
> - .sources = &exynos5_clkset_group,
> - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
> - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
> - }, {
> - .clk = {
> .name = "aclk_266_gscl",
> },
> .sources = &clk_src_gscl_266,
> @@ -1245,6 +1247,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_mdout_spi0,
> &exynos5_clk_mdout_spi1,
> &exynos5_clk_mdout_spi2,
> + &exynos5_clk_sclk_fimd,
> };
>
> static struct clk *exynos5_clk_cdev[] = {
> @@ -1497,6 +1500,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
>
> clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
> clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
> + clk_set_parent(&exynos5_clk_sclk_fimd.clk,
> + &exynos5_clk_mout_mpll_user.clk);
>
> for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
> s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 2107e01..19f3724 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -24,6 +24,9 @@
> #include <plat/regs-serial.h>
> #include <plat/backlight.h>
> #include <plat/gpio-cfg.h>
> +#include <plat/clock.h>
> +#include <plat/s5p-clock.h>
> +#include <plat/clock-clksrc.h>
>
> #include "common.h"
> #include <video/platform_lcd.h>
> @@ -176,9 +179,17 @@ static void __init exynos5250_dt_map_io(void)
>
> static void __init exynos5250_dt_machine_init(void)
> {
> + struct device_node *fimd_node;
> +
> samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
> of_platform_populate(NULL, of_default_bus_match_table,
> exynos5250_auxdata_lookup, NULL);
> +
> + fimd_node = of_find_node_with_property(NULL, "supports-mipi-panel");
> + if (of_get_property(fimd_node, "supports-mipi-panel", NULL))
> + clk_set_rate(&exynos5_clk_sclk_fimd.clk, 800000000);
> + of_node_put(fimd_node);
> +
> exynos_fimd_gpio_setup_24bpp();
> platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
> }
> diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
> index a62753d..3d27783 100644
> --- a/arch/arm/plat-samsung/include/plat/clock.h
> +++ b/arch/arm/plat-samsung/include/plat/clock.h
> @@ -83,6 +83,8 @@ extern struct clk clk_ext;
> extern struct clksrc_clk clk_epllref;
> extern struct clksrc_clk clk_esysclk;
>
> +extern struct clksrc_clk exynos5_clk_sclk_fimd;
> +
> /* S3C64XX specific clocks */
> extern struct clk clk_h2;
> extern struct clk clk_27m;
^ permalink raw reply [flat|nested] 84+ messages in thread