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From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v3 02/21] target/riscv: Clean up division helpers
Date: Thu, 19 Aug 2021 07:23:48 -1000	[thread overview]
Message-ID: <00ab6885-12b6-9c1a-cb7b-b6df770eabd4@linaro.org> (raw)
In-Reply-To: <CAEUhbmV7mHc_MWPvhNG0Lh_vtjU-zOAABXGPkOm0YJUT5epSKQ@mail.gmail.com>

On 8/19/21 1:00 AM, Bin Meng wrote:
>>   static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
>>   {
>> -    TCGv cond1, cond2, zeroreg, resultopt1;
>> +    TCGv temp1, temp2, zero, one, mone, min;
>>
>> -    cond1 = tcg_temp_new();
>> -    cond2 = tcg_temp_new();
>> -    zeroreg = tcg_constant_tl(0);
>> -    resultopt1 = tcg_temp_new();
>> +    temp1 = tcg_temp_new();
>> +    temp2 = tcg_temp_new();
>> +    zero = tcg_constant_tl(0);
>> +    one = tcg_constant_tl(1);
>> +    mone = tcg_constant_tl(-1);
>> +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
>>
>> -    tcg_gen_movi_tl(resultopt1, 1L);
>> -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
>> -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
>> -                        (target_ulong)1 << (TARGET_LONG_BITS - 1));
>> -    tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
>> -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
>> -    /* if overflow or div by zero, set source2 to 1, else don't change */
>> -    tcg_gen_or_tl(cond2, cond1, cond2);
>> -    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
>> -            resultopt1);
>> -    tcg_gen_rem_tl(resultopt1, source1, source2);
>> -    /* if div by zero, just return the original dividend */
>> -    tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
>> -            source1);
>> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
>> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
>> +    tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
>> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
>> +    tcg_gen_or_tl(temp2, temp2, temp1);  /* temp2 = overflow | div0 */
>>
>> -    tcg_temp_free(cond1);
>> -    tcg_temp_free(cond2);
>> -    tcg_temp_free(resultopt1);
>> +    /*
>> +     * if overflow or div by zero, set temp2 to 1, else source2
>> +     * this automatically takes care of returning the original
>> +     * dividend for div by zero.
>> +     */
>> +    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2);
> 
> What about the overflow case? The return value should be 0.

Hmm.  I see that in the table, yes, but I don't see that the original code got that 
correct either.  I'll send a follow-up patch.

r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v3 02/21] target/riscv: Clean up division helpers
Date: Thu, 19 Aug 2021 07:23:48 -1000	[thread overview]
Message-ID: <00ab6885-12b6-9c1a-cb7b-b6df770eabd4@linaro.org> (raw)
In-Reply-To: <CAEUhbmV7mHc_MWPvhNG0Lh_vtjU-zOAABXGPkOm0YJUT5epSKQ@mail.gmail.com>

On 8/19/21 1:00 AM, Bin Meng wrote:
>>   static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
>>   {
>> -    TCGv cond1, cond2, zeroreg, resultopt1;
>> +    TCGv temp1, temp2, zero, one, mone, min;
>>
>> -    cond1 = tcg_temp_new();
>> -    cond2 = tcg_temp_new();
>> -    zeroreg = tcg_constant_tl(0);
>> -    resultopt1 = tcg_temp_new();
>> +    temp1 = tcg_temp_new();
>> +    temp2 = tcg_temp_new();
>> +    zero = tcg_constant_tl(0);
>> +    one = tcg_constant_tl(1);
>> +    mone = tcg_constant_tl(-1);
>> +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
>>
>> -    tcg_gen_movi_tl(resultopt1, 1L);
>> -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
>> -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
>> -                        (target_ulong)1 << (TARGET_LONG_BITS - 1));
>> -    tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
>> -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
>> -    /* if overflow or div by zero, set source2 to 1, else don't change */
>> -    tcg_gen_or_tl(cond2, cond1, cond2);
>> -    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
>> -            resultopt1);
>> -    tcg_gen_rem_tl(resultopt1, source1, source2);
>> -    /* if div by zero, just return the original dividend */
>> -    tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
>> -            source1);
>> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
>> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
>> +    tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
>> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
>> +    tcg_gen_or_tl(temp2, temp2, temp1);  /* temp2 = overflow | div0 */
>>
>> -    tcg_temp_free(cond1);
>> -    tcg_temp_free(cond2);
>> -    tcg_temp_free(resultopt1);
>> +    /*
>> +     * if overflow or div by zero, set temp2 to 1, else source2
>> +     * this automatically takes care of returning the original
>> +     * dividend for div by zero.
>> +     */
>> +    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2);
> 
> What about the overflow case? The return value should be 0.

Hmm.  I see that in the table, yes, but I don't see that the original code got that 
correct either.  I'll send a follow-up patch.

r~


  reply	other threads:[~2021-08-19 17:25 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-19  9:04 [PATCH v3 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-19  9:04 ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 01/21] " Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 02/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19 11:00   ` Bin Meng
2021-08-19 11:00     ` Bin Meng
2021-08-19 17:23     ` Richard Henderson [this message]
2021-08-19 17:23       ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19 11:01   ` Bin Meng
2021-08-19 11:01     ` Bin Meng
2021-08-19  9:04 ` [PATCH v3 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 06/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-20  1:35   ` Alistair Francis
2021-08-20  1:35     ` Alistair Francis
2021-08-19  9:04 ` [PATCH v3 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 12/21] target/riscv: Add gen_greviw Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:04 ` [PATCH v3 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-19  9:04   ` Richard Henderson
2021-08-19  9:05 ` [PATCH v3 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-19  9:05   ` Richard Henderson
2021-08-19  9:05 ` [PATCH v3 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-19  9:05   ` Richard Henderson
2021-08-19  9:05 ` [PATCH v3 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-19  9:05   ` Richard Henderson

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