[PATCH 00/13] SPEAr: Move to common clock framework

[PATCH 00/13] SPEAr: Move to common clock framework

[Viresh Kumar]

Arnd,

SPEAr now supports common clock framework. This patchset contains changes
related to this. It also contain few dependency commits for clock framework that
are earlier sent separately.

@Mike: It would be easiest to get these through ARM-SoC tree. So, would need
your Acked-by on these patches. But firstly they must get reivewed :)

This patchset is rebased over:
- clk: add a fixed factor clock - by Sascha Hauer
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/090680.html

- common clk framework misc fixes - by Mike Turquette
https://lkml.org/lkml/2012/4/11/780

- V4: pinctrl: Add SPEAr pinctrl support
http://www.spinics.net/lists/arm-kernel/msg169387.html

- V3: SPEAr DT support updates
http://comments.gmane.org/gmane.linux.drivers.devicetree/14197

Russell King (1):
  CLKDEV: Add helper routines to allocate and add clkdevs for given
    struct clk *

Viresh Kumar (12):
  clk: Fix typo in comment
  clk: Fix typo in comment
  clk: clk-private: Add DEFINE_CLK macro
  clk: clk-gate: Create clk_gate_endisable()
  clk: Don't set clk->new_rate twice
  clk: clk_set_rate() must fail if CLK_SET_RATE_GATE is set and clk is
    enabled
  SPEAr: clk: Add VCO-PLL Synthesizer clock
  SPEAr: clk: Add Auxiliary Synthesizer clock
  SPEAr: clk: Add Fractional Synthesizer clock
  SPEAr: clk: Add General Purpose Timer Synthesizer clock
  SPEAr: Switch to common clock framework
  SPEAr: Call clk_prepare() before calling clk_enable

 MAINTAINERS                                     |    4 +-
 arch/arm/Kconfig                                |    1 +
 arch/arm/mach-spear3xx/clock.c                  | 1354 +++++++++--------------
 arch/arm/mach-spear3xx/include/mach/generic.h   |    4 +-
 arch/arm/mach-spear3xx/include/mach/misc_regs.h |    2 +
 arch/arm/mach-spear3xx/include/mach/spear.h     |   13 +
 arch/arm/mach-spear3xx/spear300.c               |    1 -
 arch/arm/mach-spear3xx/spear310.c               |    1 -
 arch/arm/mach-spear3xx/spear320.c               |   12 +-
 arch/arm/mach-spear3xx/spear3xx.c               |    2 +
 arch/arm/mach-spear6xx/clock.c                  | 1015 +++++------------
 arch/arm/mach-spear6xx/include/mach/misc_regs.h |    2 +
 arch/arm/mach-spear6xx/spear6xx.c               |    5 +-
 arch/arm/plat-spear/Makefile                    |    3 +-
 arch/arm/plat-spear/clk-aux-synth.c             |  195 ++++
 arch/arm/plat-spear/clk-frac-synth.c            |  156 +++
 arch/arm/plat-spear/clk-gpt-synth.c             |  145 +++
 arch/arm/plat-spear/clk-vco-pll.c               |  346 ++++++
 arch/arm/plat-spear/clock.c                     | 1005 -----------------
 arch/arm/plat-spear/include/plat/clk.h          |  143 +++
 arch/arm/plat-spear/include/plat/clock.h        |  249 -----
 arch/arm/plat-spear/time.c                      |    8 +-
 drivers/clk/clk-gate.c                          |   54 +-
 drivers/clk/clk.c                               |    7 +-
 drivers/clk/clkdev.c                            |   64 +-
 include/linux/clk-private.h                     |   59 +-
 include/linux/clk-provider.h                    |    4 +-
 include/linux/clkdev.h                          |    3 +
 28 files changed, 1963 insertions(+), 2894 deletions(-)
 create mode 100644 arch/arm/plat-spear/clk-aux-synth.c
 create mode 100644 arch/arm/plat-spear/clk-frac-synth.c
 create mode 100644 arch/arm/plat-spear/clk-gpt-synth.c
 create mode 100644 arch/arm/plat-spear/clk-vco-pll.c
 delete mode 100644 arch/arm/plat-spear/clock.c
 create mode 100644 arch/arm/plat-spear/include/plat/clk.h
 delete mode 100644 arch/arm/plat-spear/include/plat/clock.h

-- 
1.7.9

[PATCH 01/13] CLKDEV: Add helper routines to allocate and add clkdevs for given struct clk *

[Viresh Kumar]

From: Russell King <rmk+kernel@arm.linux.org.uk>

With common clock framework, clks are allocated at runtime. Some of them require
clkdevs to be allocated and added in global clkdev list.

This patch introduces helper routines to:

 - allocate and add single clkdev for a single clk structure.
 - add multiple clkdevs for a single clk structure.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/clk/clkdev.c   |   64 +++++++++++++++++++++++++++++++++++++++++++----
 include/linux/clkdev.h |    3 ++
 2 files changed, 61 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index f487015..3a72022 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -121,8 +121,9 @@ struct clk_lookup_alloc {
 	char	con_id[MAX_CON_ID];
 };
 
-struct clk_lookup * __init_refok
-clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
+static struct clk_lookup * __init_refok
+__clkdev_alloc_valist(struct clk *clk, const char *con_id, const char *dev_fmt,
+		va_list ap)
 {
 	struct clk_lookup_alloc *cla;
 
@@ -137,16 +138,35 @@ clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
 	}
 
 	if (dev_fmt) {
-		va_list ap;
-
-		va_start(ap, dev_fmt);
 		vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
 		cla->cl.dev_id = cla->dev_id;
-		va_end(ap);
 	}
 
 	return &cla->cl;
 }
+
+#define clkdev_alloc_valist(_cl, _clk, _con_id, _dev_fmt, _ap)		\
+	do {								\
+		if (_dev_fmt)						\
+			va_start(_ap, _dev_fmt);			\
+									\
+		_cl = __clkdev_alloc_valist(_clk, _con_id, _dev_fmt,	\
+				_ap);					\
+									\
+		if (_dev_fmt)						\
+			va_end(ap);					\
+	} while (0);
+
+struct clk_lookup * __init_refok
+clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
+{
+	struct clk_lookup *cl;
+	va_list ap;
+
+	clkdev_alloc_valist(cl, clk, con_id, dev_fmt, ap);
+
+	return cl;
+}
 EXPORT_SYMBOL(clkdev_alloc);
 
 int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
@@ -178,3 +198,35 @@ void clkdev_drop(struct clk_lookup *cl)
 	kfree(cl);
 }
 EXPORT_SYMBOL(clkdev_drop);
+
+int clk_register_clkdev(struct clk *clk, const char *con_id,
+		const char *dev_fmt, ...)
+{
+	struct clk_lookup *cl;
+	va_list ap;
+
+	clkdev_alloc_valist(cl, clk, con_id, dev_fmt, ap);
+
+	if (!cl)
+		return -ENOMEM;
+
+	clkdev_add(cl);
+	return 0;
+}
+EXPORT_SYMBOL(clk_register_clkdev);
+
+int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num)
+{
+	unsigned i;
+
+	if (!clk)
+		return -ENOMEM;
+
+	for (i = 0; i < num; i++, cl++) {
+		cl->clk = clk;
+		clkdev_add(cl);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(clk_register_clkdevs);
diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index d9a4fd0..01d8ff6 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -39,5 +39,8 @@ void clkdev_drop(struct clk_lookup *cl);
 
 void clkdev_add_table(struct clk_lookup *, size_t);
 int clk_add_alias(const char *, const char *, char *, struct device *);
+int clk_register_clkdev(struct clk *clk, const char *con_id,
+		const char *dev_fmt, ...);
+int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num);
 
 #endif
-- 
1.7.9

[PATCH 02/13] clk: Fix typo in comment

[Viresh Kumar]

CLK_GATE_SET_TO_DISABLE is mistakenly written as CLK_GATE_SET_DISABLE in
comment. Fix it.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 include/linux/clk-provider.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 50ee80b..d98bdbc 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -166,7 +166,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
  * Clock which can gate its output.  Implements .enable & .disable
  *
  * Flags:
- * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
+ * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
  * 	enable the clock.  Setting this flag does the opposite: setting the bit
  * 	disable the clock and clearing it enables the clock
  */
-- 
1.7.9

[PATCH 02/13] clk: Fix typo in comment

[Turquette, Mike]

On Tue, Apr 17, 2012 at 4:15 AM, Viresh Kumar <viresh.kumar@st.com> wrote:
> CLK_GATE_SET_TO_DISABLE is mistakenly written as CLK_GATE_SET_DISABLE in
> comment. Fix it.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>

Thanks for the fix.  I'll combine this patch with your
CLK_MUX_INDEX_BIT typo fix and pull into my -next branch.

Regards,
Mike

> ---
> ?include/linux/clk-provider.h | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 50ee80b..d98bdbc 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -166,7 +166,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ?* Clock which can gate its output. ?Implements .enable & .disable
> ?*
> ?* Flags:
> - * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
> + * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
> ?* ? ? enable the clock. ?Setting this flag does the opposite: setting the bit
> ?* ? ? disable the clock and clearing it enables the clock
> ?*/
> --
> 1.7.9
>

[PATCH 03/13] clk: Fix typo in comment

[Viresh Kumar]

CLK_MUX_INDEX_BIT is mistakenly written as CLK_MUX_INDEX_BITWISE in comment. Fix
it.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 include/linux/clk-provider.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d98bdbc..8bb93c4 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -239,7 +239,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
  *
  * Flags:
  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
- * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
+ * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
  */
 struct clk_mux {
 	struct clk_hw	hw;
-- 
1.7.9

[PATCH 04/13] clk: clk-private: Add DEFINE_CLK macro

[Viresh Kumar]

All macros used for creating different kind of clocks have similar code for
initializing struct clk. This patch removes those redundant lines and create
another macro DEFINE_CLK.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 include/linux/clk-private.h |   59 ++++++++++++++----------------------------
 1 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index e7032fd..eeae7a3 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -55,6 +55,18 @@ struct clk {
  * alternative macro for static initialization
  */
 
+#define DEFINE_CLK(_name, _ops, _flags, _parent_names,		\
+		_parents)					\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &_ops,					\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _parent_names,			\
+		.num_parents = ARRAY_SIZE(_parent_names),	\
+		.parents = _parents,				\
+		.flags = _flags,				\
+	}
+
 #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
 				_fixed_rate_flags)		\
 	static struct clk _name;				\
@@ -66,15 +78,8 @@ struct clk {
 		.fixed_rate = _rate,				\
 		.flags = _fixed_rate_flags,			\
 	};							\
-	static struct clk _name = {				\
-		.name = #_name,					\
-		.ops = &clk_fixed_rate_ops,			\
-		.hw = &_name##_hw.hw,				\
-		.parent_names = _name##_parent_names,		\
-		.num_parents =					\
-			ARRAY_SIZE(_name##_parent_names),	\
-		.flags = _flags,				\
-	};
+	DEFINE_CLK(_name, clk_fixed_rate_ops, _flags,		\
+			_name##_parent_names, NULL);
 
 #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
 				_flags, _reg, _bit_idx,		\
@@ -95,16 +100,8 @@ struct clk {
 		.flags = _gate_flags,				\
 		.lock = _lock,					\
 	};							\
-	static struct clk _name = {				\
-		.name = #_name,					\
-		.ops = &clk_gate_ops,				\
-		.hw = &_name##_hw.hw,				\
-		.parent_names = _name##_parent_names,		\
-		.num_parents =					\
-			ARRAY_SIZE(_name##_parent_names),	\
-		.parents = _name##_parents,			\
-		.flags = _flags,				\
-	};
+	DEFINE_CLK(_name, clk_gate_ops, _flags,			\
+			_name##_parent_names, _name##_parents);
 
 #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
 				_flags, _reg, _shift, _width,	\
@@ -126,16 +123,8 @@ struct clk {
 		.flags = _divider_flags,			\
 		.lock = _lock,					\
 	};							\
-	static struct clk _name = {				\
-		.name = #_name,					\
-		.ops = &clk_divider_ops,			\
-		.hw = &_name##_hw.hw,				\
-		.parent_names = _name##_parent_names,		\
-		.num_parents =					\
-			ARRAY_SIZE(_name##_parent_names),	\
-		.parents = _name##_parents,			\
-		.flags = _flags,				\
-	};
+	DEFINE_CLK(_name, clk_divider_ops, _flags,		\
+			_name##_parent_names, _name##_parents);
 
 #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
 				_reg, _shift, _width,		\
@@ -151,16 +140,8 @@ struct clk {
 		.flags = _mux_flags,				\
 		.lock = _lock,					\
 	};							\
-	static struct clk _name = {				\
-		.name = #_name,					\
-		.ops = &clk_mux_ops,				\
-		.hw = &_name##_hw.hw,				\
-		.parent_names = _parent_names,			\
-		.num_parents =					\
-			ARRAY_SIZE(_parent_names),		\
-		.parents = _parents,				\
-		.flags = _flags,				\
-	};
+	DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names,	\
+			_parents);
 
 /**
  * __clk_init - initialize the data structures in a struct clk
-- 
1.7.9

[PATCH 04/13] clk: clk-private: Add DEFINE_CLK macro

[Turquette, Mike]

On Tue, Apr 17, 2012 at 4:15 AM, Viresh Kumar <viresh.kumar@st.com> wrote:
> All macros used for creating different kind of clocks have similar code for
> initializing struct clk. This patch removes those redundant lines and create
> another macro DEFINE_CLK.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>

Viresh,

I want to kill off these macros entirely in the future.  That said,
your patch reduces LoC and the macros will certainly be there in 3.5,
so I'll take this into my -next branch.

Thanks,
Mike

> ---
> ?include/linux/clk-private.h | ? 59 ++++++++++++++----------------------------
> ?1 files changed, 20 insertions(+), 39 deletions(-)
>
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index e7032fd..eeae7a3 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -55,6 +55,18 @@ struct clk {
> ?* alternative macro for static initialization
> ?*/
>
> +#define DEFINE_CLK(_name, _ops, _flags, _parent_names, ? ? ? ? \
> + ? ? ? ? ? ? ? _parents) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops = &_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .parent_names = _parent_names, ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .num_parents = ARRAY_SIZE(_parent_names), ? ? ? \
> + ? ? ? ? ? ? ? .parents = _parents, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }
> +
> ?#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_fixed_rate_flags) ? ? ? ? ? ? ?\
> ? ? ? ?static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> @@ -66,15 +78,8 @@ struct clk {
> ? ? ? ? ? ? ? ?.fixed_rate = _rate, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.flags = _fixed_rate_flags, ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ?}; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops = &clk_fixed_rate_ops, ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
> - ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> - ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? };
> + ? ? ? DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? _name##_parent_names, NULL);
>
> ?#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_flags, _reg, _bit_idx, ? ? ? ? \
> @@ -95,16 +100,8 @@ struct clk {
> ? ? ? ? ? ? ? ?.flags = _gate_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?}; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops = &clk_gate_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
> - ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> - ? ? ? ? ? ? ? .parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? };
> + ? ? ? DEFINE_CLK(_name, clk_gate_ops, _flags, ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? _name##_parent_names, _name##_parents);
>
> ?#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, ? \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_flags, _reg, _shift, _width, ? \
> @@ -126,16 +123,8 @@ struct clk {
> ? ? ? ? ? ? ? ?.flags = _divider_flags, ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?}; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops = &clk_divider_ops, ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
> - ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> - ? ? ? ? ? ? ? .parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? };
> + ? ? ? DEFINE_CLK(_name, clk_divider_ops, _flags, ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? _name##_parent_names, _name##_parents);
>
> ?#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_reg, _shift, _width, ? ? ? ? ? \
> @@ -151,16 +140,8 @@ struct clk {
> ? ? ? ? ? ? ? ?.flags = _mux_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?}; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops = &clk_mux_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .parent_names = _parent_names, ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_parent_names), ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? .parents = _parents, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? };
> + ? ? ? DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, ? \
> + ? ? ? ? ? ? ? ? ? ? ? _parents);
>
> ?/**
> ?* __clk_init - initialize the data structures in a struct clk
> --
> 1.7.9
>

[PATCH 05/13] clk: clk-gate: Create clk_gate_endisable()

[Viresh Kumar]

This patch tries to remove duplicate code for clk_gate clocks. This creates
another routine clk_gate_endisable() which will take care of enable/disable
clock with knowledge of CLK_GATE_SET_TO_DISABLE flag.

It works on following logic:

For enabling clock, enable = 1
	set2dis = 1	-> clear bit	-> set = 0
	set2dis = 0	-> set bit	-> set = 1

For disabling clock, enable = 0
	set2dis = 1	-> set bit	-> set = 1
	set2dis = 0	-> clear bit	-> set = 0

So, result is always: enable xor set2dis.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/clk/clk-gate.c |   54 ++++++++++++++++++++++-------------------------
 1 files changed, 25 insertions(+), 29 deletions(-)

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 288fb5e..f8d70b5 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -28,32 +28,38 @@
 
 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
 
-static void clk_gate_set_bit(struct clk_gate *gate)
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ *	set2dis = 1	-> clear bit	-> set = 0
+ *	set2dis = 0	-> set bit	-> set = 1
+ *
+ * For disabling clock, enable = 0
+ *	set2dis = 1	-> set bit	-> set = 1
+ *	set2dis = 0	-> clear bit	-> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void clk_gate_endisable(struct clk_hw *hw, int enable)
 {
-	u32 reg;
+	struct clk_gate *gate = to_clk_gate(hw);
+	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
 	unsigned long flags = 0;
+	u32 reg;
+
+	set ^= enable;
 
 	if (gate->lock)
 		spin_lock_irqsave(gate->lock, flags);
 
 	reg = readl(gate->reg);
-	reg |= BIT(gate->bit_idx);
-	writel(reg, gate->reg);
-
-	if (gate->lock)
-		spin_unlock_irqrestore(gate->lock, flags);
-}
-
-static void clk_gate_clear_bit(struct clk_gate *gate)
-{
-	u32 reg;
-	unsigned long flags = 0;
 
-	if (gate->lock)
-		spin_lock_irqsave(gate->lock, flags);
+	if (set)
+		reg |= BIT(gate->bit_idx);
+	else
+		reg &= ~BIT(gate->bit_idx);
 
-	reg = readl(gate->reg);
-	reg &= ~BIT(gate->bit_idx);
 	writel(reg, gate->reg);
 
 	if (gate->lock)
@@ -62,24 +68,14 @@ static void clk_gate_clear_bit(struct clk_gate *gate)
 
 static int clk_gate_enable(struct clk_hw *hw)
 {
-	struct clk_gate *gate = to_clk_gate(hw);
-
-	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
-		clk_gate_clear_bit(gate);
-	else
-		clk_gate_set_bit(gate);
+	clk_gate_endisable(hw, 1);
 
 	return 0;
 }
 
 static void clk_gate_disable(struct clk_hw *hw)
 {
-	struct clk_gate *gate = to_clk_gate(hw);
-
-	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
-		clk_gate_set_bit(gate);
-	else
-		clk_gate_clear_bit(gate);
+	clk_gate_endisable(hw, 0);
 }
 
 static int clk_gate_is_enabled(struct clk_hw *hw)
-- 
1.7.9

[PATCH 05/13] clk: clk-gate: Create clk_gate_endisable()

[Turquette, Mike]

On Tue, Apr 17, 2012 at 4:15 AM, Viresh Kumar <viresh.kumar@st.com> wrote:
> This patch tries to remove duplicate code for clk_gate clocks. This creates
> another routine clk_gate_endisable() which will take care of enable/disable
> clock with knowledge of CLK_GATE_SET_TO_DISABLE flag.
>
> It works on following logic:
>
> For enabling clock, enable = 1
> ? ? ? ?set2dis = 1 ? ? -> clear bit ? ?-> set = 0
> ? ? ? ?set2dis = 0 ? ? -> set bit ? ? ?-> set = 1
>
> For disabling clock, enable = 0
> ? ? ? ?set2dis = 1 ? ? -> set bit ? ? ?-> set = 1
> ? ? ? ?set2dis = 0 ? ? -> clear bit ? ?-> set = 0
>
> So, result is always: enable xor set2dis.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>

Hi Viresh,

Looks good to me.  I'll take into my -next branch.

Thanks,
Mike

> ---
> ?drivers/clk/clk-gate.c | ? 54 ++++++++++++++++++++++-------------------------
> ?1 files changed, 25 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index 288fb5e..f8d70b5 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -28,32 +28,38 @@
>
> ?#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
>
> -static void clk_gate_set_bit(struct clk_gate *gate)
> +/*
> + * It works on following logic:
> + *
> + * For enabling clock, enable = 1
> + * ? ? set2dis = 1 ? ? -> clear bit ? ?-> set = 0
> + * ? ? set2dis = 0 ? ? -> set bit ? ? ?-> set = 1
> + *
> + * For disabling clock, enable = 0
> + * ? ? set2dis = 1 ? ? -> set bit ? ? ?-> set = 1
> + * ? ? set2dis = 0 ? ? -> clear bit ? ?-> set = 0
> + *
> + * So, result is always: enable xor set2dis.
> + */
> +static void clk_gate_endisable(struct clk_hw *hw, int enable)
> ?{
> - ? ? ? u32 reg;
> + ? ? ? struct clk_gate *gate = to_clk_gate(hw);
> + ? ? ? int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
> ? ? ? ?unsigned long flags = 0;
> + ? ? ? u32 reg;
> +
> + ? ? ? set ^= enable;
>
> ? ? ? ?if (gate->lock)
> ? ? ? ? ? ? ? ?spin_lock_irqsave(gate->lock, flags);
>
> ? ? ? ?reg = readl(gate->reg);
> - ? ? ? reg |= BIT(gate->bit_idx);
> - ? ? ? writel(reg, gate->reg);
> -
> - ? ? ? if (gate->lock)
> - ? ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
> -}
> -
> -static void clk_gate_clear_bit(struct clk_gate *gate)
> -{
> - ? ? ? u32 reg;
> - ? ? ? unsigned long flags = 0;
>
> - ? ? ? if (gate->lock)
> - ? ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
> + ? ? ? if (set)
> + ? ? ? ? ? ? ? reg |= BIT(gate->bit_idx);
> + ? ? ? else
> + ? ? ? ? ? ? ? reg &= ~BIT(gate->bit_idx);
>
> - ? ? ? reg = readl(gate->reg);
> - ? ? ? reg &= ~BIT(gate->bit_idx);
> ? ? ? ?writel(reg, gate->reg);
>
> ? ? ? ?if (gate->lock)
> @@ -62,24 +68,14 @@ static void clk_gate_clear_bit(struct clk_gate *gate)
>
> ?static int clk_gate_enable(struct clk_hw *hw)
> ?{
> - ? ? ? struct clk_gate *gate = to_clk_gate(hw);
> -
> - ? ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> - ? ? ? ? ? ? ? clk_gate_clear_bit(gate);
> - ? ? ? else
> - ? ? ? ? ? ? ? clk_gate_set_bit(gate);
> + ? ? ? clk_gate_endisable(hw, 1);
>
> ? ? ? ?return 0;
> ?}
>
> ?static void clk_gate_disable(struct clk_hw *hw)
> ?{
> - ? ? ? struct clk_gate *gate = to_clk_gate(hw);
> -
> - ? ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> - ? ? ? ? ? ? ? clk_gate_set_bit(gate);
> - ? ? ? else
> - ? ? ? ? ? ? ? clk_gate_clear_bit(gate);
> + ? ? ? clk_gate_endisable(hw, 0);
> ?}
>
> ?static int clk_gate_is_enabled(struct clk_hw *hw)
> --
> 1.7.9
>

[PATCH 06/13] clk: Don't set clk->new_rate twice

[Viresh Kumar]

if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) is true, then
we don't need to set clk->new_rate here, as we will call clk_calc_subtree()
afterwards and it also sets clk->new_rate.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/clk/clk.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index af2bf12..865d0dd 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -789,7 +789,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 
 	if (!clk->ops->round_rate) {
 		top = clk_calc_new_rates(clk->parent, rate);
-		new_rate = clk->new_rate = clk->parent->new_rate;
+		new_rate = clk->parent->new_rate;
 
 		goto out;
 	}
-- 
1.7.9

[PATCH 06/13] clk: Don't set clk->new_rate twice

[Turquette, Mike]

On Tue, Apr 17, 2012 at 4:15 AM, Viresh Kumar <viresh.kumar@st.com> wrote:
> if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) is true, then
> we don't need to set clk->new_rate here, as we will call clk_calc_subtree()
> afterwards and it also sets clk->new_rate.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>

Looks good.  Will take into -next.

Thanks,
Mike

> ---
> ?drivers/clk/clk.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index af2bf12..865d0dd 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -789,7 +789,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
>
> ? ? ? ?if (!clk->ops->round_rate) {
> ? ? ? ? ? ? ? ?top = clk_calc_new_rates(clk->parent, rate);
> - ? ? ? ? ? ? ? new_rate = clk->new_rate = clk->parent->new_rate;
> + ? ? ? ? ? ? ? new_rate = clk->parent->new_rate;
>
> ? ? ? ? ? ? ? ?goto out;
> ? ? ? ?}
> --
> 1.7.9
>

[PATCH 07/13] clk: clk_set_rate() must fail if CLK_SET_RATE_GATE is set and clk is enabled

[Viresh Kumar]

This is well documented but isn't implemented. clk_set_rate() must check if
flags have CLK_SET_RATE_GATE bit set and is enabled too.

Untested patch.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/clk/clk.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 865d0dd..2bcce5a 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -898,6 +898,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	if (rate == clk->rate)
 		goto out;
 
+	if ((clk->flags & CLK_SET_RATE_GATE) && __clk_is_enabled(clk)) {
+		ret = -EBUSY;
+		goto out;
+	}
+
 	/* calculate new rates and get the topmost changed clock */
 	top = clk_calc_new_rates(clk, rate);
 	if (!top) {
-- 
1.7.9

[PATCH 08/13] SPEAr: clk: Add VCO-PLL Synthesizer clock

[Viresh Kumar]

All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 arch/arm/plat-spear/Makefile           |    1 +
 arch/arm/plat-spear/clk-vco-pll.c      |  346 ++++++++++++++++++++++++++++++++
 arch/arm/plat-spear/include/plat/clk.h |   78 +++++++
 3 files changed, 425 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-spear/clk-vco-pll.c
 create mode 100644 arch/arm/plat-spear/include/plat/clk.h

diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 7744802..4e6d65d 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,3 +6,4 @@
 obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-vco-pll.o
diff --git a/arch/arm/plat-spear/clk-vco-pll.c b/arch/arm/plat-spear/clk-vco-pll.c
new file mode 100644
index 0000000..0f12173
--- /dev/null
+++ b/arch/arm/plat-spear/clk-vco-pll.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * VCO-PLL clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-vco-pll: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <plat/clk.h>
+
+/*
+ * DOC: VCO-PLL clock
+ *
+ * VCO and PLL rate are derived from following equations:
+ *
+ * In normal mode
+ * vco = (2 * M[15:8] * Fin)/N
+ *
+ * In Dithered mode
+ * vco = (2 * M[15:0] * Fin)/(256 * N)
+ *
+ * pll_rate = pll/2^p
+ *
+ * vco and pll are very closely bound to each other, "vco needs to program:
+ * mode, m & n" and "pll needs to program p", both share common enable/disable
+ * logic.
+ *
+ * clk_register_vco_pll() registers instances of both vco & pll.
+ * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
+ * set_rate to vco. A single rate table exists for both the clocks, which
+ * configures m, n and p.
+ */
+
+/* PLL_CTR register masks */
+#define PLL_MODE_NORMAL		0
+#define PLL_MODE_FRACTION	1
+#define PLL_MODE_DITH_DSM	2
+#define PLL_MODE_DITH_SSM	3
+#define PLL_MODE_MASK		3
+#define PLL_MODE_SHIFT		3
+#define PLL_ENABLE		2
+
+#define PLL_LOCK_SHIFT		0
+#define PLL_LOCK_MASK		1
+
+/* PLL FRQ register masks */
+#define PLL_NORM_FDBK_M_MASK	0xFF
+#define PLL_NORM_FDBK_M_SHIFT	24
+#define PLL_DITH_FDBK_M_MASK	0xFFFF
+#define PLL_DITH_FDBK_M_SHIFT	16
+#define PLL_DIV_P_MASK		0x7
+#define PLL_DIV_P_SHIFT		8
+#define PLL_DIV_N_MASK		0xFF
+#define PLL_DIV_N_SHIFT		0
+
+#define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+/* Calculates pll clk rate for specific value of mode, m, n and p */
+static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
+		unsigned long prate, int index, unsigned long *pll_rate)
+{
+	unsigned long rate = prate;
+	unsigned int mode;
+
+	mode = rtbl[index].mode ? 256 : 1;
+	rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
+
+	if (pll_rate)
+		*pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
+
+	return rate * 10000;
+}
+
+static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
+				unsigned long *prate, int *index)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	unsigned long prev_rate, vco_prev_rate, rate = 0;
+	unsigned long vco_parent_rate =
+		__clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
+
+	if (!prate) {
+		pr_err("%s: prate is must for pll clk\n", __func__);
+		return -EINVAL;
+	}
+
+	for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
+		prev_rate = rate;
+		vco_prev_rate = *prate;
+		*prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
+				&rate);
+		if (drate < rate) {
+			/* previous clock was best */
+			if (*index) {
+				rate = prev_rate;
+				*prate = vco_prev_rate;
+				(*index)--;
+			}
+			break;
+		}
+	}
+
+	return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
+				unsigned long *prate)
+{
+	int unused;
+
+	return clk_pll_round_rate_index(hw, drate, prate, &unused);
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
+		parent_rate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	unsigned long flags = 0;
+	unsigned int p;
+
+	if (pll->vco->lock)
+		spin_lock_irqsave(pll->vco->lock, flags);
+
+	p = readl_relaxed(pll->vco->cfg_reg);
+
+	if (pll->vco->lock)
+		spin_unlock_irqrestore(pll->vco->lock, flags);
+
+	p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
+
+	return parent_rate / (1 << p);
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	struct pll_rate_tbl *rtbl = pll->vco->rtbl;
+	unsigned long flags = 0, val;
+	int i;
+
+	clk_pll_round_rate_index(hw, drate, NULL, &i);
+
+	if (pll->vco->lock)
+		spin_lock_irqsave(pll->vco->lock, flags);
+
+	val = readl_relaxed(pll->vco->cfg_reg);
+	val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
+	val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
+	writel_relaxed(val, pll->vco->cfg_reg);
+
+	if (pll->vco->lock)
+		spin_unlock_irqrestore(pll->vco->lock, flags);
+
+	return 0;
+}
+
+static struct clk_ops clk_pll_ops = {
+	.recalc_rate = clk_pll_recalc_rate,
+	.round_rate = clk_pll_round_rate,
+	.set_rate = clk_pll_set_rate,
+};
+
+static inline unsigned long vco_calc_rate(struct clk_hw *hw,
+		unsigned long prate, int index)
+{
+	struct clk_vco *vco = to_clk_vco(hw);
+
+	return pll_calc_rate(vco->rtbl, prate, index, NULL);
+}
+
+static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_vco *vco = to_clk_vco(hw);
+	int unused;
+
+	return clk_round_rate_index(hw, drate, vco_calc_rate, vco->rtbl_cnt,
+			&unused);
+}
+
+static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_vco *vco = to_clk_vco(hw);
+	unsigned long flags = 0;
+	unsigned int num = 2, den = 0, val, mode = 0;
+
+	if (vco->lock)
+		spin_lock_irqsave(vco->lock, flags);
+
+	mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
+
+	val = readl_relaxed(vco->cfg_reg);
+
+	if (vco->lock)
+		spin_unlock_irqrestore(vco->lock, flags);
+
+	den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
+
+	/* calculate numerator & denominator */
+	if (!mode) {
+		/* Normal mode */
+		num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
+	} else {
+		/* Dithered mode */
+		num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
+		den *= 256;
+	}
+
+	if (!den) {
+		WARN(1, "%s: denominator can't be zero\n", __func__);
+		return 0;
+	}
+
+	return (((parent_rate / 10000) * num) / den) * 10000;
+}
+
+/* Configures new clock rate of vco */
+static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate)
+{
+	struct clk_vco *vco = to_clk_vco(hw);
+	struct pll_rate_tbl *rtbl = vco->rtbl;
+	unsigned long flags = 0, val;
+	int i;
+
+	clk_round_rate_index(hw, drate, vco_calc_rate, vco->rtbl_cnt, &i);
+
+	if (vco->lock)
+		spin_lock_irqsave(vco->lock, flags);
+
+	val = readl_relaxed(vco->mode_reg);
+	val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
+	val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
+	writel_relaxed(val, vco->mode_reg);
+
+	val = readl_relaxed(vco->cfg_reg);
+	val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
+	val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
+
+	val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
+	if (rtbl[i].mode)
+		val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
+			PLL_DITH_FDBK_M_SHIFT;
+	else
+		val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
+			PLL_NORM_FDBK_M_SHIFT;
+
+	writel_relaxed(val, vco->cfg_reg);
+
+	if (vco->lock)
+		spin_unlock_irqrestore(vco->lock, flags);
+
+	return 0;
+}
+
+static struct clk_ops clk_vco_ops = {
+	.recalc_rate = clk_vco_recalc_rate,
+	.round_rate = clk_vco_round_rate,
+	.set_rate = clk_vco_set_rate,
+};
+
+struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
+		const char *vco_gate_name, const char *parent_name,
+		unsigned long flags, void __iomem *mode_reg, void __iomem
+		*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
+		spinlock_t *lock, struct clk **pll_clk,
+		struct clk **vco_gate_clk)
+{
+	struct clk_vco *vco;
+	struct clk_pll *pll;
+	struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
+	const char **vco_parent_name;
+
+	if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
+			!rtbl || !rtbl_cnt) {
+		pr_err("Invalid arguments passed");
+		return ERR_PTR(-EINVAL);
+	}
+
+	vco = kzalloc(sizeof(*vco), GFP_KERNEL);
+	if (!vco) {
+		pr_err("could not allocate vco clk\n");
+		return NULL;
+	}
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll) {
+		pr_err("could not allocate pll clk\n");
+		goto free_vco;
+	}
+
+	/* struct clk_vco assignments */
+	vco->mode_reg = mode_reg;
+	vco->cfg_reg = cfg_reg;
+	vco->rtbl = rtbl;
+	vco->rtbl_cnt = rtbl_cnt;
+	vco->lock = lock;
+	pll->vco = vco;
+
+	if (vco_gate_name) {
+		tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
+				parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
+		if (!tvco_gate_clk)
+			goto free_pll;
+
+		if (vco_gate_clk)
+			*vco_gate_clk = tvco_gate_clk;
+		vco_parent_name = &vco_gate_name;
+	} else {
+		vco_parent_name = &parent_name;
+	}
+
+	vco_clk = clk_register(NULL, vco_name, &clk_vco_ops, &vco->hw,
+			vco_parent_name, 1, flags);
+	if (!vco_clk)
+		goto free_pll;
+
+	tpll_clk = clk_register(NULL, pll_name, &clk_pll_ops, &pll->hw,
+			&vco_name, 1, CLK_SET_RATE_PARENT);
+	if (!tpll_clk)
+		goto free_pll;
+
+	if (pll_clk)
+		*pll_clk = tpll_clk;
+
+	return vco_clk;
+
+free_pll:
+	kfree(pll);
+free_vco:
+	kfree(vco);
+
+	pr_err("Failed to register vco pll clock\n");
+
+	return NULL;
+}
diff --git a/arch/arm/plat-spear/include/plat/clk.h b/arch/arm/plat-spear/include/plat/clk.h
new file mode 100644
index 0000000..3c93d9f
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/clk.h
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/plat-spear/include/plat/clk.h
+ *
+ * Clock framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_CLOCK_H
+#define __PLAT_CLOCK_H
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock_types.h>
+#include <linux/types.h>
+
+/* VCO-PLL clk */
+struct pll_rate_tbl {
+	u8 mode;
+	u16 m;
+	u8 n;
+	u8 p;
+};
+
+struct clk_vco {
+	struct			clk_hw hw;
+	void __iomem		*mode_reg;
+	void __iomem		*cfg_reg;
+	struct pll_rate_tbl	*rtbl;
+	u8			rtbl_cnt;
+	spinlock_t		*lock;
+};
+
+struct clk_pll {
+	struct			clk_hw hw;
+	struct clk_vco		*vco;
+	const char		*parent[1];
+	spinlock_t		*lock;
+};
+
+typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
+		int index);
+
+/* clk register routines */
+struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
+		const char *vco_gate_name, const char *parent_name,
+		unsigned long flags, void __iomem *mode_reg, void __iomem
+		*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
+		spinlock_t *lock, struct clk **pll_clk,
+		struct clk **vco_gate_clk);
+
+static inline long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+		clk_calc_rate calc_rate, u8 rtbl_cnt, int *index)
+{
+	unsigned long prev_rate, rate = 0;
+	unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+
+	for (*index = 0; *index < rtbl_cnt; (*index)++) {
+		prev_rate = rate;
+		rate = calc_rate(hw, parent_rate, *index);
+		if (drate < rate) {
+			/* previous clock was best */
+			if (*index) {
+				rate = prev_rate;
+				(*index)--;
+			}
+			break;
+		}
+	}
+
+	return rate;
+}
+
+#endif /* __PLAT_CLOCK_H */
-- 
1.7.9

[PATCH 09/13] SPEAr: clk: Add Auxiliary Synthesizer clock

[Viresh Kumar]

All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.

Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2		EQ1
Fout2 = Fin * X/Y		EQ2

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 arch/arm/plat-spear/Makefile           |    2 +-
 arch/arm/plat-spear/clk-aux-synth.c    |  195 ++++++++++++++++++++++++++++++++
 arch/arm/plat-spear/include/plat/clk.h |   32 +++++
 3 files changed, 228 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-spear/clk-aux-synth.c

diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4e6d65d..7e0f480 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,4 +6,4 @@
 obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o
-obj-$(CONFIG_COMMON_CLK)	+= clk-vco-pll.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-aux-synth.o clk-vco-pll.o
diff --git a/arch/arm/plat-spear/clk-aux-synth.c b/arch/arm/plat-spear/clk-aux-synth.c
new file mode 100644
index 0000000..69045a6
--- /dev/null
+++ b/arch/arm/plat-spear/clk-aux-synth.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Auxiliary Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-aux-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <plat/clk.h>
+
+/*
+ * DOC: Auxiliary Synthesizer clock
+ *
+ * Aux synth gives rate for different values of eq, x and y
+ *
+ * Fout from synthesizer can be given from two equations:
+ * Fout1 = (Fin * X/Y)/2		EQ1
+ * Fout2 = Fin * X/Y			EQ2
+ */
+
+#define AUX_EQ_SEL_SHIFT	30
+#define AUX_EQ_SEL_MASK		1
+#define AUX_EQ1_SEL		0
+#define AUX_EQ2_SEL		1
+#define AUX_XSCALE_SHIFT	16
+#define AUX_XSCALE_MASK		0xFFF
+#define AUX_YSCALE_SHIFT	0
+#define AUX_YSCALE_MASK		0xFFF
+
+#define AUX_SYNT_ENB		31
+
+#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
+
+static struct aux_clk_masks default_aux_masks = {
+	.eq_sel_mask = AUX_EQ_SEL_MASK,
+	.eq_sel_shift = AUX_EQ_SEL_SHIFT,
+	.eq1_mask = AUX_EQ1_SEL,
+	.eq2_mask = AUX_EQ2_SEL,
+	.xscale_sel_mask = AUX_XSCALE_MASK,
+	.xscale_sel_shift = AUX_XSCALE_SHIFT,
+	.yscale_sel_mask = AUX_YSCALE_MASK,
+	.yscale_sel_shift = AUX_YSCALE_SHIFT,
+	.enable_bit = AUX_SYNT_ENB,
+};
+
+static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
+		int index)
+{
+	struct clk_aux *aux = to_clk_aux(hw);
+	struct aux_rate_tbl *rtbl = aux->rtbl;
+	u8 eq = rtbl[index].eq ? 1 : 2;
+
+	return (((prate / 10000) * rtbl[index].xscale) /
+			(rtbl[index].yscale * eq)) * 10000;
+}
+
+static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_aux *aux = to_clk_aux(hw);
+	int unused;
+
+	return clk_round_rate_index(hw, drate, aux_calc_rate, aux->rtbl_cnt,
+			&unused);
+}
+
+static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_aux *aux = to_clk_aux(hw);
+	unsigned int num = 1, den = 1, val, eqn;
+	unsigned long flags = 0;
+
+	if (aux->lock)
+		spin_lock_irqsave(aux->lock, flags);
+
+	val = readl_relaxed(aux->reg);
+
+	if (aux->lock)
+		spin_unlock_irqrestore(aux->lock, flags);
+
+	eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
+	if (eqn == aux->masks->eq1_mask)
+		den = 2;
+
+	/* calculate numerator */
+	num = (val >> aux->masks->xscale_sel_shift) &
+		aux->masks->xscale_sel_mask;
+
+	/* calculate denominator */
+	den *= (val >> aux->masks->yscale_sel_shift) &
+		aux->masks->yscale_sel_mask;
+
+	if (!den)
+		return 0;
+
+	return (((parent_rate / 10000) * num) / den) * 10000;
+}
+
+/* Configures new clock rate of aux */
+static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate)
+{
+	struct clk_aux *aux = to_clk_aux(hw);
+	struct aux_rate_tbl *rtbl = aux->rtbl;
+	unsigned long val, flags = 0;
+	int i;
+
+	clk_round_rate_index(hw, drate, aux_calc_rate, aux->rtbl_cnt, &i);
+
+	if (aux->lock)
+		spin_lock_irqsave(aux->lock, flags);
+
+	val = readl_relaxed(aux->reg) &
+		~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
+	val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
+		aux->masks->eq_sel_shift;
+	val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
+	val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
+		aux->masks->xscale_sel_shift;
+	val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
+	val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
+		aux->masks->yscale_sel_shift;
+	writel_relaxed(val, aux->reg);
+
+	if (aux->lock)
+		spin_unlock_irqrestore(aux->lock, flags);
+
+	return 0;
+}
+
+static struct clk_ops clk_aux_ops = {
+	.recalc_rate = clk_aux_recalc_rate,
+	.round_rate = clk_aux_round_rate,
+	.set_rate = clk_aux_set_rate,
+};
+
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+		const char *parent_name, unsigned long flags, void __iomem *reg,
+		struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+		u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
+{
+	struct clk_aux *aux;
+	struct clk *clk, *tgate_clk;
+
+	if (!aux_name || !gate_name || !parent_name || !reg || !rtbl ||
+			!rtbl_cnt) {
+		pr_err("Invalid arguments passed");
+		return ERR_PTR(-EINVAL);
+	}
+
+	aux = kzalloc(sizeof(*aux), GFP_KERNEL);
+	if (!aux) {
+		pr_err("could not allocate aux clk\n");
+		return NULL;
+	}
+
+	/* struct clk_aux assignments */
+	if (!masks)
+		aux->masks = &default_aux_masks;
+
+	aux->reg = reg;
+	aux->rtbl = rtbl;
+	aux->rtbl_cnt = rtbl_cnt;
+	aux->lock = lock;
+
+	clk = clk_register(NULL, aux_name, &clk_aux_ops, &aux->hw, &parent_name,
+			1, flags);
+	if (!clk)
+		goto free_aux;
+
+	tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg,
+			aux->masks->enable_bit, 0, lock);
+	if (!tgate_clk)
+		goto free_aux;
+
+	if (gate_clk)
+		*gate_clk = tgate_clk;
+
+	return clk;
+
+free_aux:
+	kfree(aux);
+	pr_err("clk register failed\n");
+
+	return NULL;
+}
diff --git a/arch/arm/plat-spear/include/plat/clk.h b/arch/arm/plat-spear/include/plat/clk.h
index 3c93d9f..d3533e0 100644
--- a/arch/arm/plat-spear/include/plat/clk.h
+++ b/arch/arm/plat-spear/include/plat/clk.h
@@ -18,6 +18,34 @@
 #include <linux/spinlock_types.h>
 #include <linux/types.h>
 
+/* Auxiliary Synth clk */
+struct aux_clk_masks {
+	u32 eq_sel_mask;
+	u32 eq_sel_shift;
+	u32 eq1_mask;
+	u32 eq2_mask;
+	u32 xscale_sel_mask;
+	u32 xscale_sel_shift;
+	u32 yscale_sel_mask;
+	u32 yscale_sel_shift;
+	u32 enable_bit;
+};
+
+struct aux_rate_tbl {
+	u16 xscale;
+	u16 yscale;
+	u8 eq;
+};
+
+struct clk_aux {
+	struct			clk_hw hw;
+	void __iomem		*reg;
+	struct aux_clk_masks	*masks;
+	struct aux_rate_tbl	*rtbl;
+	u8			rtbl_cnt;
+	spinlock_t		*lock;
+};
+
 /* VCO-PLL clk */
 struct pll_rate_tbl {
 	u8 mode;
@@ -46,6 +74,10 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
 		int index);
 
 /* clk register routines */
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+		const char *parent_name, unsigned long flags, void __iomem *reg,
+		struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+		u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
 struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
 		const char *vco_gate_name, const char *parent_name,
 		unsigned long flags, void __iomem *mode_reg, void __iomem
-- 
1.7.9

[PATCH 09/13] SPEAr: clk: Add Auxiliary Synthesizer clock

[Sascha Hauer]

On Tue, Apr 17, 2012 at 04:45:41PM +0530, Viresh Kumar wrote:
> All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
> values of eq, x and y.
> 
> +static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
> +		unsigned long parent_rate)
> +{
> +	struct clk_aux *aux = to_clk_aux(hw);
> +	unsigned int num = 1, den = 1, val, eqn;
> +	unsigned long flags = 0;
> +
> +	if (aux->lock)
> +		spin_lock_irqsave(aux->lock, flags);
> +
> +	val = readl_relaxed(aux->reg);
> +
> +	if (aux->lock)
> +		spin_unlock_irqrestore(aux->lock, flags);
> +

A single read is atomic and needs no lock.

> +struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
> +		const char *parent_name, unsigned long flags, void __iomem *reg,
> +		struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
> +		u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
> +{
> +	struct clk_aux *aux;
> +	struct clk *clk, *tgate_clk;
> +
> +	if (!aux_name || !gate_name || !parent_name || !reg || !rtbl ||
> +			!rtbl_cnt) {
> +		pr_err("Invalid arguments passed");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	aux = kzalloc(sizeof(*aux), GFP_KERNEL);
> +	if (!aux) {
> +		pr_err("could not allocate aux clk\n");
> +		return NULL;
> +	}

This PTR_ERR stuff really is a pain in the ass, it's way too easy to get
it wrong. IS_ERR_OR_NULL might be a good idea, but IS_ERR is just
insane.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 09/13] SPEAr: clk: Add Auxiliary Synthesizer clock

[Arnd Bergmann]

On Tuesday 17 April 2012, Sascha Hauer wrote:
> > +{
> > +     struct clk_aux *aux = to_clk_aux(hw);
> > +     unsigned int num = 1, den = 1, val, eqn;
> > +     unsigned long flags = 0;
> > +
> > +     if (aux->lock)
> > +             spin_lock_irqsave(aux->lock, flags);
> > +
> > +     val = readl_relaxed(aux->reg);
> > +
> > +     if (aux->lock)
> > +             spin_unlock_irqrestore(aux->lock, flags);
> > +
> 
> A single read is atomic and needs no lock.

That depends on whether the read has any side-effects. There
is another function that does a read-modify-write on the
same register, and you might need to prevent this one from
reading the register between the other read and the following
write.

The spinlock also has the benefit of enforcing the ordering
of the read with regard to your instruction stream, otherwise
it can be delayed on out-of-order CPUs until the value
is actually used.

	Arnd

[PATCH 09/13] SPEAr: clk: Add Auxiliary Synthesizer clock

[Sascha Hauer]

On Tue, Apr 17, 2012 at 08:30:24PM +0000, Arnd Bergmann wrote:
> On Tuesday 17 April 2012, Sascha Hauer wrote:
> > > +{
> > > +     struct clk_aux *aux = to_clk_aux(hw);
> > > +     unsigned int num = 1, den = 1, val, eqn;
> > > +     unsigned long flags = 0;
> > > +
> > > +     if (aux->lock)
> > > +             spin_lock_irqsave(aux->lock, flags);
> > > +
> > > +     val = readl_relaxed(aux->reg);
> > > +
> > > +     if (aux->lock)
> > > +             spin_unlock_irqrestore(aux->lock, flags);
> > > +
> > 
> > A single read is atomic and needs no lock.
> 
> That depends on whether the read has any side-effects. There
> is another function that does a read-modify-write on the
> same register, and you might need to prevent this one from
> reading the register between the other read and the following
> write.
> 
> The spinlock also has the benefit of enforcing the ordering
> of the read with regard to your instruction stream, otherwise
> it can be delayed on out-of-order CPUs until the value
> is actually used.

Ah, I learned something. Sorry for the noise.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 10/13] SPEAr: clk: Add Fractional Synthesizer clock

[Viresh Kumar]

All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 arch/arm/plat-spear/Makefile           |    2 +-
 arch/arm/plat-spear/clk-frac-synth.c   |  156 ++++++++++++++++++++++++++++++++
 arch/arm/plat-spear/include/plat/clk.h |   16 ++++
 3 files changed, 173 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-spear/clk-frac-synth.c

diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 7e0f480..3cedb21 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,4 +6,4 @@
 obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o
-obj-$(CONFIG_COMMON_CLK)	+= clk-aux-synth.o clk-vco-pll.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-aux-synth.o clk-frac-synth.o clk-vco-pll.o
diff --git a/arch/arm/plat-spear/clk-frac-synth.c b/arch/arm/plat-spear/clk-frac-synth.c
new file mode 100644
index 0000000..7a3cfc0
--- /dev/null
+++ b/arch/arm/plat-spear/clk-frac-synth.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Fractional Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-frac-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <plat/clk.h>
+
+#define DIV_FACTOR_MASK		0x1FFFF
+
+/*
+ * DOC: Fractional Synthesizer clock
+ *
+ * Fout from synthesizer can be given from below equation:
+ *
+ * Fout= Fin/2*div (division factor)
+ * div is 17 bits:-
+ *	0-13 (fractional part)
+ *	14-16 (integer part)
+ *	div is (16-14 bits).(13-0 bits) (in binary)
+ *
+ *	Fout = Fin/(2 * div)
+ *	Fout = ((Fin / 10000)/(2 * div)) * 10000
+ *	Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
+ *	Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
+ *
+ * div << 14 simply 17 bit value written@register.
+ * Max error due to scaling down by 10000 is 10 KHz
+ */
+
+#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
+
+static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate,
+		int index)
+{
+	struct clk_frac *frac = to_clk_frac(hw);
+	struct frac_rate_tbl *rtbl = frac->rtbl;
+
+	prate /= 10000;
+	prate <<= 14;
+	prate /= (2 * rtbl[index].div);
+	prate *= 10000;
+
+	return prate;
+}
+
+static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_frac *frac = to_clk_frac(hw);
+	int unused;
+
+	return clk_round_rate_index(hw, drate, frac_calc_rate, frac->rtbl_cnt,
+			&unused);
+}
+
+static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_frac *frac = to_clk_frac(hw);
+	unsigned long flags = 0;
+	unsigned int div = 1, val;
+
+	if (frac->lock)
+		spin_lock_irqsave(frac->lock, flags);
+
+	val = readl_relaxed(frac->reg);
+
+	if (frac->lock)
+		spin_unlock_irqrestore(frac->lock, flags);
+
+	div = val & DIV_FACTOR_MASK;
+
+	if (!div)
+		return 0;
+
+	parent_rate = parent_rate / 10000;
+
+	parent_rate = (parent_rate << 14) / (2 * div);
+	return parent_rate * 10000;
+}
+
+/* Configures new clock rate of frac */
+static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate)
+{
+	struct clk_frac *frac = to_clk_frac(hw);
+	struct frac_rate_tbl *rtbl = frac->rtbl;
+	unsigned long flags = 0, val;
+	int i;
+
+	clk_round_rate_index(hw, drate, frac_calc_rate, frac->rtbl_cnt, &i);
+
+	if (frac->lock)
+		spin_lock_irqsave(frac->lock, flags);
+
+	val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK;
+	val |= rtbl[i].div & DIV_FACTOR_MASK;
+	writel_relaxed(val, frac->reg);
+
+	if (frac->lock)
+		spin_unlock_irqrestore(frac->lock, flags);
+
+	return 0;
+}
+
+struct clk_ops clk_frac_ops = {
+	.recalc_rate = clk_frac_recalc_rate,
+	.round_rate = clk_frac_round_rate,
+	.set_rate = clk_frac_set_rate,
+};
+
+struct clk *clk_register_frac(const char *name, const char *parent_name,
+		unsigned long flags, void __iomem *reg,
+		struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock)
+{
+	struct clk_frac *frac;
+	struct clk *clk;
+
+	if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+		pr_err("Invalid arguments passed");
+		return ERR_PTR(-EINVAL);
+	}
+
+	frac = kzalloc(sizeof(*frac), GFP_KERNEL);
+	if (!frac) {
+		pr_err("could not allocate frac clk\n");
+		return NULL;
+	}
+
+	/* struct clk_frac assignments */
+	frac->reg = reg;
+	frac->rtbl = rtbl;
+	frac->rtbl_cnt = rtbl_cnt;
+	frac->lock = lock;
+
+	clk = clk_register(NULL, name, &clk_frac_ops, &frac->hw, &parent_name,
+			1, flags);
+	if (clk)
+		return clk;
+
+	pr_err("clk register failed\n");
+	kfree(frac);
+
+	return NULL;
+}
diff --git a/arch/arm/plat-spear/include/plat/clk.h b/arch/arm/plat-spear/include/plat/clk.h
index d3533e0..7d03e79 100644
--- a/arch/arm/plat-spear/include/plat/clk.h
+++ b/arch/arm/plat-spear/include/plat/clk.h
@@ -46,6 +46,19 @@ struct clk_aux {
 	spinlock_t		*lock;
 };
 
+/* Fractional Synth clk */
+struct frac_rate_tbl {
+	u32 div;
+};
+
+struct clk_frac {
+	struct			clk_hw hw;
+	void __iomem		*reg;
+	struct frac_rate_tbl	*rtbl;
+	u8			rtbl_cnt;
+	spinlock_t		*lock;
+};
+
 /* VCO-PLL clk */
 struct pll_rate_tbl {
 	u8 mode;
@@ -78,6 +91,9 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
 		const char *parent_name, unsigned long flags, void __iomem *reg,
 		struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
 		u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
+struct clk *clk_register_frac(const char *name, const char *parent_name,
+		unsigned long flags, void __iomem *reg,
+		struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
 struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
 		const char *vco_gate_name, const char *parent_name,
 		unsigned long flags, void __iomem *mode_reg, void __iomem
-- 
1.7.9

[PATCH 11/13] SPEAr: clk: Add General Purpose Timer Synthesizer clock

[Viresh Kumar]

All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:

Fout= Fin/((2 ^ (N+1)) * (M+1))

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 arch/arm/plat-spear/Makefile           |    2 +-
 arch/arm/plat-spear/clk-gpt-synth.c    |  145 ++++++++++++++++++++++++++++++++
 arch/arm/plat-spear/include/plat/clk.h |   17 ++++
 3 files changed, 163 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-spear/clk-gpt-synth.c

diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 3cedb21..767c18c 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -6,4 +6,4 @@
 obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o
-obj-$(CONFIG_COMMON_CLK)	+= clk-aux-synth.o clk-frac-synth.o clk-vco-pll.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
diff --git a/arch/arm/plat-spear/clk-gpt-synth.c b/arch/arm/plat-spear/clk-gpt-synth.c
new file mode 100644
index 0000000..0bfd89f
--- /dev/null
+++ b/arch/arm/plat-spear/clk-gpt-synth.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * General Purpose Timer Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-gpt-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <plat/clk.h>
+
+#define GPT_MSCALE_MASK		0xFFF
+#define GPT_NSCALE_SHIFT	12
+#define GPT_NSCALE_MASK		0xF
+
+/*
+ * DOC: General Purpose Timer Synthesizer clock
+ *
+ * Calculates gpt synth clk rate for different values of mscale and nscale
+ *
+ * Fout= Fin/((2 ^ (N+1)) * (M+1))
+ */
+
+#define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw)
+
+static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate,
+		int index)
+{
+	struct clk_gpt *gpt = to_clk_gpt(hw);
+	struct gpt_rate_tbl *rtbl = gpt->rtbl;
+
+	prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
+
+	return prate;
+}
+
+static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_gpt *gpt = to_clk_gpt(hw);
+	int unused;
+
+	return clk_round_rate_index(hw, drate, gpt_calc_rate, gpt->rtbl_cnt,
+			&unused);
+}
+
+static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_gpt *gpt = to_clk_gpt(hw);
+	unsigned long flags = 0;
+	unsigned int div = 1, val;
+
+	if (gpt->lock)
+		spin_lock_irqsave(gpt->lock, flags);
+
+	val = readl_relaxed(gpt->reg);
+
+	if (gpt->lock)
+		spin_unlock_irqrestore(gpt->lock, flags);
+
+	div += val & GPT_MSCALE_MASK;
+	div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
+
+	if (!div)
+		return 0;
+
+	return parent_rate / div;
+}
+
+/* Configures new clock rate of gpt */
+static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate)
+{
+	struct clk_gpt *gpt = to_clk_gpt(hw);
+	struct gpt_rate_tbl *rtbl = gpt->rtbl;
+	unsigned long flags = 0, val;
+	int i;
+
+	clk_round_rate_index(hw, drate, gpt_calc_rate, gpt->rtbl_cnt, &i);
+
+	if (gpt->lock)
+		spin_lock_irqsave(gpt->lock, flags);
+
+	val = readl(gpt->reg) & ~GPT_MSCALE_MASK;
+	val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT);
+
+	val |= rtbl[i].mscale & GPT_MSCALE_MASK;
+	val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT;
+
+	writel_relaxed(val, gpt->reg);
+
+	if (gpt->lock)
+		spin_unlock_irqrestore(gpt->lock, flags);
+
+	return 0;
+}
+
+static struct clk_ops clk_gpt_ops = {
+	.recalc_rate = clk_gpt_recalc_rate,
+	.round_rate = clk_gpt_round_rate,
+	.set_rate = clk_gpt_set_rate,
+};
+
+struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
+		long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
+		rtbl_cnt, spinlock_t *lock)
+{
+	struct clk_gpt *gpt;
+	struct clk *clk;
+
+	if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+		pr_err("Invalid arguments passed");
+		return ERR_PTR(-EINVAL);
+	}
+
+	gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
+	if (!gpt) {
+		pr_err("could not allocate gpt clk\n");
+		return NULL;
+	}
+
+	/* struct clk_gpt assignments */
+	gpt->reg = reg;
+	gpt->rtbl = rtbl;
+	gpt->rtbl_cnt = rtbl_cnt;
+	gpt->lock = lock;
+
+	clk = clk_register(NULL, name, &clk_gpt_ops, &gpt->hw, &parent_name, 1,
+			flags);
+	if (clk)
+		return clk;
+
+	pr_err("clk register failed\n");
+	kfree(gpt);
+
+	return NULL;
+}
diff --git a/arch/arm/plat-spear/include/plat/clk.h b/arch/arm/plat-spear/include/plat/clk.h
index 7d03e79..7e4f979 100644
--- a/arch/arm/plat-spear/include/plat/clk.h
+++ b/arch/arm/plat-spear/include/plat/clk.h
@@ -59,6 +59,20 @@ struct clk_frac {
 	spinlock_t		*lock;
 };
 
+/* GPT clk */
+struct gpt_rate_tbl {
+	u16 mscale;
+	u16 nscale;
+};
+
+struct clk_gpt {
+	struct			clk_hw hw;
+	void __iomem		*reg;
+	struct gpt_rate_tbl	*rtbl;
+	u8			rtbl_cnt;
+	spinlock_t		*lock;
+};
+
 /* VCO-PLL clk */
 struct pll_rate_tbl {
 	u8 mode;
@@ -94,6 +108,9 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
 struct clk *clk_register_frac(const char *name, const char *parent_name,
 		unsigned long flags, void __iomem *reg,
 		struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
+struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
+		long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
+		rtbl_cnt, spinlock_t *lock);
 struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
 		const char *vco_gate_name, const char *parent_name,
 		unsigned long flags, void __iomem *mode_reg, void __iomem
-- 
1.7.9

[PATCH 13/13] SPEAr: Call clk_prepare() before calling clk_enable

[Viresh Kumar]

With common clock framework, it is must to call clk_{un}prepare() before/after
clk_{dis}enable. This patch fixes this for SPEAr timer.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
 arch/arm/plat-spear/time.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index a3164d1..4f05d26 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -218,10 +218,10 @@ void __init spear_setup_timer(resource_size_t base, int irq)
 		goto err_iomap;
 	}
 
-	ret = clk_enable(gpt_clk);
+	ret = clk_prepare_enable(gpt_clk);
 	if (ret < 0) {
-		pr_err("%s:couldn't enable gpt clock\n", __func__);
-		goto err_clk;
+		pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
+		goto err_prepare_enable_clk;
 	}
 
 	spear_clockevent_init(irq);
@@ -229,7 +229,7 @@ void __init spear_setup_timer(resource_size_t base, int irq)
 
 	return;
 
-err_clk:
+err_prepare_enable_clk:
 	clk_put(gpt_clk);
 err_iomap:
 	iounmap(gpt_base);
-- 
1.7.9

[PATCH 13/13] SPEAr: Call clk_prepare() before calling clk_enable

[Sergei Shtylyov]

Hello.

On 04/17/2012 03:15 PM, Viresh Kumar wrote:

> With common clock framework, it is must to call clk_{un}prepare() before/after

    Can't parse "it is must to call". Maybe simply "[we] must call"?

> clk_{dis}enable. This patch fixes this for SPEAr timer.

> Signed-off-by: Viresh Kumar<viresh.kumar@st.com>

WBR, Sergei

[PATCH 13/13] SPEAr: Call clk_prepare() before calling clk_enable

[Turquette, Mike]

On Tue, Apr 17, 2012 at 4:15 AM, Viresh Kumar <viresh.kumar@st.com> wrote:
> With common clock framework, it is must to call clk_{un}prepare() before/after
> clk_{dis}enable. This patch fixes this for SPEAr timer.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
> ---
> ?arch/arm/plat-spear/time.c | ? ?8 ++++----
> ?1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
> index a3164d1..4f05d26 100644
> --- a/arch/arm/plat-spear/time.c
> +++ b/arch/arm/plat-spear/time.c
> @@ -218,10 +218,10 @@ void __init spear_setup_timer(resource_size_t base, int irq)
> ? ? ? ? ? ? ? ?goto err_iomap;
> ? ? ? ?}
>
> - ? ? ? ret = clk_enable(gpt_clk);
> + ? ? ? ret = clk_prepare_enable(gpt_clk);

Where do you call clk_enable?  Further down in the code somewhere?

Also does this change break git bisect for your platform?  Maybe you
should move this change before patch 12/13 to prevent run-time
breakage?

Regards,
Mike

> ? ? ? ?if (ret < 0) {
> - ? ? ? ? ? ? ? pr_err("%s:couldn't enable gpt clock\n", __func__);
> - ? ? ? ? ? ? ? goto err_clk;
> + ? ? ? ? ? ? ? pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
> + ? ? ? ? ? ? ? goto err_prepare_enable_clk;
> ? ? ? ?}
>
> ? ? ? ?spear_clockevent_init(irq);
> @@ -229,7 +229,7 @@ void __init spear_setup_timer(resource_size_t base, int irq)
>
> ? ? ? ?return;
>
> -err_clk:
> +err_prepare_enable_clk:
> ? ? ? ?clk_put(gpt_clk);
> ?err_iomap:
> ? ? ? ?iounmap(gpt_base);
> --
> 1.7.9
>

[PATCH 13/13] SPEAr: Call clk_prepare() before calling clk_enable

[Turquette, Mike]

On Wed, Apr 18, 2012 at 6:36 PM, viresh kumar <viresh.linux@gmail.com> wrote:
>
> On Apr 19, 2012 2:47 AM, "Turquette, Mike" <mturquette@ti.com> wrote:
>>
>> On Tue, Apr 17, 2012 at 4:15 AM, Viresh Kumar <viresh.kumar@st.com> wrote:
>> > With common clock framework, it is must to call clk_{un}prepare()
>> > before/after
>> > clk_{dis}enable. This patch fixes this for SPEAr timer.
>> >
>> > Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
>> > ---
>> > ?arch/arm/plat-spear/time.c | ? ?8 ++++----
>> > ?1 files changed, 4 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
>> > index a3164d1..4f05d26 100644
>> > --- a/arch/arm/plat-spear/time.c
>> > +++ b/arch/arm/plat-spear/time.c
>> > @@ -218,10 +218,10 @@ void __init spear_setup_timer(resource_size_t
>> > base, int irq)
>> > ? ? ? ? ? ? ? ?goto err_iomap;
>> > ? ? ? ?}
>> >
>> > - ? ? ? ret = clk_enable(gpt_clk);
>> > + ? ? ? ret = clk_prepare_enable(gpt_clk);
>>
>> Where do you call clk_enable? ?Further down in the code somewhere?
>
> I called prepare_enable() here.
> Did i get your question correctly?

My mistake.  When I glanced over the code I saw "clk_prepare" and
somehow skipped the "_enable" part.

Regards,
Mike

>> Also does this change break git bisect for your platform? ?Maybe you
>> should move this change before patch 12/13 to prevent run-time
>> breakage?
>
> Correct.
>
> --
> Viresh

[PATCH 00/13] SPEAr: Move to common clock framework

[Arnd Bergmann]

On Tuesday 17 April 2012, Viresh Kumar wrote:
> SPEAr now supports common clock framework. This patchset contains changes
> related to this. It also contain few dependency commits for clock framework that
> are earlier sent separately.
> 
> @Mike: It would be easiest to get these through ARM-SoC tree. So, would need
> your Acked-by on these patches. But firstly they must get reivewed :)

We should agree on how we want to do the common clk patches for v3.5.
The two options I see are either we take all the patches that Mike
Acks into arm-soc, or Mike applies the patches in his own tree and
submits them to arm-soc. I think either way is fine for me, but
some people might feel strongly one way or another.

>  MAINTAINERS                                     |    4 +-
>  arch/arm/Kconfig                                |    1 +
>  arch/arm/mach-spear3xx/clock.c                  | 1354 +++++++++--------------
>  arch/arm/mach-spear3xx/include/mach/generic.h   |    4 +-
>  arch/arm/mach-spear3xx/include/mach/misc_regs.h |    2 +
>  arch/arm/mach-spear3xx/include/mach/spear.h     |   13 +
>  arch/arm/mach-spear3xx/spear300.c               |    1 -
>  arch/arm/mach-spear3xx/spear310.c               |    1 -
>  arch/arm/mach-spear3xx/spear320.c               |   12 +-
>  arch/arm/mach-spear3xx/spear3xx.c               |    2 +
>  arch/arm/mach-spear6xx/clock.c                  | 1015 +++++------------
>  arch/arm/mach-spear6xx/include/mach/misc_regs.h |    2 +
>  arch/arm/mach-spear6xx/spear6xx.c               |    5 +-
>  arch/arm/plat-spear/Makefile                    |    3 +-
>  arch/arm/plat-spear/clk-aux-synth.c             |  195 ++++
>  arch/arm/plat-spear/clk-frac-synth.c            |  156 +++
>  arch/arm/plat-spear/clk-gpt-synth.c             |  145 +++
>  arch/arm/plat-spear/clk-vco-pll.c               |  346 ++++++
>  arch/arm/plat-spear/clock.c                     | 1005 -----------------

I wonder: should the clock drivers remain part of the platform directory,
or get moved into a subdirectory of drivers/clk? I was assuming that 
we'd do the latter, but I haven't been following the clk discussions
that closely.

	Arnd

[PATCH 00/13] SPEAr: Move to common clock framework

[Shawn Guo]

On Tue, Apr 17, 2012 at 02:34:05PM +0000, Arnd Bergmann wrote:
> I wonder: should the clock drivers remain part of the platform directory,
> or get moved into a subdirectory of drivers/clk? I was assuming that 
> we'd do the latter, but I haven't been following the clk discussions
> that closely.
> 
Mike had some comment [1] there, and I would second that.

Regards,
Shawn

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/158320/focus=158543

[PATCH 00/13] SPEAr: Move to common clock framework

[Turquette, Mike]

On Tue, Apr 17, 2012 at 7:57 AM, Shawn Guo <shawn.guo@linaro.org> wrote:
> On Tue, Apr 17, 2012 at 02:34:05PM +0000, Arnd Bergmann wrote:
>> I wonder: should the clock drivers remain part of the platform directory,
>> or get moved into a subdirectory of drivers/clk? I was assuming that
>> we'd do the latter, but I haven't been following the clk discussions
>> that closely.
>>
> Mike had some comment [1] there, and I would second that.

Thanks for bringing up that thread Shawn.  Just to clarify, I don't
oppose platform clock code living in drivers/clk/.  If it can be done
easily then I'm all for it.

I do oppose any _requirement_ for clock code to live there.  That
would be unreasonable for complex hardware.

For anyone planning on pushing their platform clock code into
drivers/clk/ I would encourage them to think long and hard on the best
ways to make that code useful to others.

Regards,
Mike

> Regards,
> Shawn
>
> [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/158320/focus=158543

[PATCH 00/13] SPEAr: Move to common clock framework

[Turquette, Mike]

On Tue, Apr 17, 2012 at 7:34 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday 17 April 2012, Viresh Kumar wrote:
>> SPEAr now supports common clock framework. This patchset contains changes
>> related to this. It also contain few dependency commits for clock framework that
>> are earlier sent separately.
>>
>> @Mike: It would be easiest to get these through ARM-SoC tree. So, would need
>> your Acked-by on these patches. But firstly they must get reivewed :)
>
> We should agree on how we want to do the common clk patches for v3.5.
> The two options I see are either we take all the patches that Mike
> Acks into arm-soc, or Mike applies the patches in his own tree and
> submits them to arm-soc. I think either way is fine for me, but
> some people might feel strongly one way or another.

I would prefer the latter (I maintain a branch and submit it).  Is
arm-soc still the right place for common clk patches in 3.5 and
beyond?  I don't mind hosting a branch for inclusion into linux-next
and sending a pull request to Linus.  There is nothing ARM-specific
about the common framework.

Regards,
Mike

[PATCH 00/13] SPEAr: Move to common clock framework

[Sascha Hauer]

On Wed, Apr 18, 2012 at 01:45:42PM -0700, Turquette, Mike wrote:
> On Tue, Apr 17, 2012 at 7:34 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Tuesday 17 April 2012, Viresh Kumar wrote:
> >> SPEAr now supports common clock framework. This patchset contains changes
> >> related to this. It also contain few dependency commits for clock framework that
> >> are earlier sent separately.
> >>
> >> @Mike: It would be easiest to get these through ARM-SoC tree. So, would need
> >> your Acked-by on these patches. But firstly they must get reivewed :)
> >
> > We should agree on how we want to do the common clk patches for v3.5.
> > The two options I see are either we take all the patches that Mike
> > Acks into arm-soc, or Mike applies the patches in his own tree and
> > submits them to arm-soc. I think either way is fine for me, but
> > some people might feel strongly one way or another.
> 
> I would prefer the latter (I maintain a branch and submit it).  Is
> arm-soc still the right place for common clk patches in 3.5 and
> beyond?  I don't mind hosting a branch for inclusion into linux-next
> and sending a pull request to Linus.  There is nothing ARM-specific
> about the common framework.

Either way is fine with me, but it's really important that all the
floating clock framework patches begin to materialize in a visible
branch.

Sascha

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[PATCH 00/13] SPEAr: Move to common clock framework

[Turquette, Mike]

On Wed, Apr 18, 2012 at 2:13 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Wed, Apr 18, 2012 at 01:45:42PM -0700, Turquette, Mike wrote:
>> On Tue, Apr 17, 2012 at 7:34 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>> > On Tuesday 17 April 2012, Viresh Kumar wrote:
>> >> SPEAr now supports common clock framework. This patchset contains changes
>> >> related to this. It also contain few dependency commits for clock framework that
>> >> are earlier sent separately.
>> >>
>> >> @Mike: It would be easiest to get these through ARM-SoC tree. So, would need
>> >> your Acked-by on these patches. But firstly they must get reivewed :)
>> >
>> > We should agree on how we want to do the common clk patches for v3.5.
>> > The two options I see are either we take all the patches that Mike
>> > Acks into arm-soc, or Mike applies the patches in his own tree and
>> > submits them to arm-soc. I think either way is fine for me, but
>> > some people might feel strongly one way or another.
>>
>> I would prefer the latter (I maintain a branch and submit it). ?Is
>> arm-soc still the right place for common clk patches in 3.5 and
>> beyond? ?I don't mind hosting a branch for inclusion into linux-next
>> and sending a pull request to Linus. ?There is nothing ARM-specific
>> about the common framework.
>
> Either way is fine with me, but it's really important that all the
> floating clock framework patches begin to materialize in a visible
> branch.

Agreed.  I've been busy the last several days with some tasks besides
common clk maintenance, but I'm going through all the patches now and
will have a -next branch up soon on git.linaro.org.

Regards,
Mike

[PATCH 00/13] SPEAr: Move to common clock framework

[Turquette, Mike]

On Wed, Apr 18, 2012 at 2:22 PM, Turquette, Mike <mturquette@ti.com> wrote:
> On Wed, Apr 18, 2012 at 2:13 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> On Wed, Apr 18, 2012 at 01:45:42PM -0700, Turquette, Mike wrote:
>>> On Tue, Apr 17, 2012 at 7:34 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>>> > On Tuesday 17 April 2012, Viresh Kumar wrote:
>>> >> SPEAr now supports common clock framework. This patchset contains changes
>>> >> related to this. It also contain few dependency commits for clock framework that
>>> >> are earlier sent separately.
>>> >>
>>> >> @Mike: It would be easiest to get these through ARM-SoC tree. So, would need
>>> >> your Acked-by on these patches. But firstly they must get reivewed :)
>>> >
>>> > We should agree on how we want to do the common clk patches for v3.5.
>>> > The two options I see are either we take all the patches that Mike
>>> > Acks into arm-soc, or Mike applies the patches in his own tree and
>>> > submits them to arm-soc. I think either way is fine for me, but
>>> > some people might feel strongly one way or another.
>>>
>>> I would prefer the latter (I maintain a branch and submit it). ?Is
>>> arm-soc still the right place for common clk patches in 3.5 and
>>> beyond? ?I don't mind hosting a branch for inclusion into linux-next
>>> and sending a pull request to Linus. ?There is nothing ARM-specific
>>> about the common framework.
>>
>> Either way is fine with me, but it's really important that all the
>> floating clock framework patches begin to materialize in a visible
>> branch.
>
> Agreed. ?I've been busy the last several days with some tasks besides
> common clk maintenance, but I'm going through all the patches now and
> will have a -next branch up soon on git.linaro.org.

Viresh,

I've taken patches 02 - 06 into my -next branch.  Patch 01 isn't for
me really, and I've not yet tested patch 07 (I'll take it everything
looks good).  The rest of your series (08 - 13) should probably go
through Arnd.

Thanks,
Mike

[PATCH 00/13] SPEAr: Move to common clock framework

[Turquette, Mike]

On Wed, Apr 18, 2012 at 5:12 PM, viresh kumar <viresh.linux@gmail.com> wrote:
>
> On Apr 19, 2012 2:55 AM, "Turquette, Mike" <mturquette@ti.com> wrote:
>
>>
>> I've taken patches 02 - 06 into my -next branch. ?Patch 01 isn't for
>> me really, and I've not yet tested patch 07 (I'll take it everything
>> looks good). ?The rest of your series (08 - 13) should probably go
>> through Arnd.
>
> Yes you are correct. Even to get spear clk? patches through arnd,
> I would need fixed-factor clk's patch of Sascha to
> go through your tree. What are your plans
> for that patch.

It is on the review list :-)

Regards,
Mike

> Viresh

[PATCH 00/13] SPEAr: Move to common clock framework

[Arnd Bergmann]

On Wednesday 18 April 2012, Turquette, Mike wrote:
> I've taken patches 02 - 06 into my -next branch.  Patch 01 isn't for
> me really, and I've not yet tested patch 07 (I'll take it everything
> looks good).  The rest of your series (08 - 13) should probably go
> through Arnd.

My preference would be to have the whole series go through your tree
and move the implementation of the spear clock code to drivers/clk
in the process. This will reduce interdependencies between the spear
clock branch and other branches that have spear patches.

I also think it's a good idea if you submit the clk patches to Linus
directly for the next merge window, but it's ok to use arm-soc if
that makes you feel more confident about it.

	Arnd

[PATCH 00/13] SPEAr: Move to common clock framework

[Viresh Kumar]

On 4/19/2012 2:27 PM, Arnd Bergmann wrote:
> My preference would be to have the whole series go through your tree
> and move the implementation of the spear clock code to drivers/clk
> in the process. This will reduce interdependencies between the spear
> clock branch and other branches that have spear patches.

Atleast for now, SPEAr clock patches have dependency on earlier SPEAr patches
for which i have already sent you pull request.

So, this time atleast, these may go through your tree only.

You are talking about moving all clk files to drivers/clk or part of them
(plat/clk-*.c or mach/clock.c)

Also, i don't know what's the best way, but arch/arm/*spear* looks to be the
better place for SPEAr clock stuff. As it shares lot of registers/macros
with non-clock stuff. If we keep them in drivers/clk we have to include
<mach/...> files.

-- 
viresh

[PATCH 00/13] SPEAr: Move to common clock framework

[Arnd Bergmann]

On Thursday 19 April 2012, Viresh Kumar wrote:
> On 4/19/2012 2:27 PM, Arnd Bergmann wrote:
> > My preference would be to have the whole series go through your tree
> > and move the implementation of the spear clock code to drivers/clk
> > in the process. This will reduce interdependencies between the spear
> > clock branch and other branches that have spear patches.
> 
> Atleast for now, SPEAr clock patches have dependency on earlier SPEAr patches
> for which i have already sent you pull request.

Ok, I see. This could also be resolved by making the clock branch a
superset of stuff that is in arm-soc, so that Mike would just have
to wait for all the dependencies from arm-soc to go upstream before
he asks Linus to pull the clock specific changes.

> So, this time atleast, these may go through your tree only.
> 
> You are talking about moving all clk files to drivers/clk or part of them
> (plat/clk-*.c or mach/clock.c)

I mean all of them.

> Also, i don't know what's the best way, but arch/arm/*spear* looks to be the
> better place for SPEAr clock stuff. As it shares lot of registers/macros
> with non-clock stuff. If we keep them in drivers/clk we have to include
> <mach/...> files.

There is a general tendencies to move stuff out of arch/arm into subsystem
specific directories. We've already done this for drivers/gpio,
drivers/pinctrl and some others, and I would like to see the same get done
for irqchip and clock. The main reason is so that we have all drivers for
the subsystem in one place, where a reader can compare them and they
are put into the subsystem maintainers's responsibility rather than the
platform maintainer. Obviously you still want both the subsystem and the
platform maintainer to review any patches to those files, but in my
experience this is done more consistently by sorting the files by
subsystem.

	Arnd

[PATCH 00/13] SPEAr: Move to common clock framework

[Turquette, Mike]

On Thu, Apr 19, 2012 at 1:57 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 18 April 2012, Turquette, Mike wrote:
>> I've taken patches 02 - 06 into my -next branch. ?Patch 01 isn't for
>> me really, and I've not yet tested patch 07 (I'll take it everything
>> looks good). ?The rest of your series (08 - 13) should probably go
>> through Arnd.
>
> My preference would be to have the whole series go through your tree
> and move the implementation of the spear clock code to drivers/clk
> in the process. This will reduce interdependencies between the spear
> clock branch and other branches that have spear patches.

If Viresh moves his code to drivers/clk/ then I'll take it.

> I also think it's a good idea if you submit the clk patches to Linus
> directly for the next merge window, but it's ok to use arm-soc if
> that makes you feel more confident about it.

As I said in my previous mail, I'd prefer to send to Linus directly.
Sounds like we're in agreement.

Regards,
Mike