All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry
Date: Thu,  4 Jun 2020 18:21:12 -0700	[thread overview]
Message-ID: <04e964562dcef49f0f54f28f8ea2cfa386fba8f3.1591319882.git.alistair@alistair23.me> (raw)
In-Reply-To: <cover.1591319882.git.alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c |  8 +-------
 target/riscv/op_helper.c  |  8 ++------
 target/riscv/translate.c  | 10 ----------
 4 files changed, 4 insertions(+), 23 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 028e268faa..6b97c27711 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -430,6 +430,7 @@
 #define HSTATUS_VTSR         0x00400000
 #define HSTATUS_HU           0x00000200
 #define HSTATUS_GVA          0x00000040
+#define HSTATUS_SPVP         0x00000100
 
 #define HSTATUS32_WPRI       0xFF8FF87E
 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4ea39d5641..c4085e5870 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -916,9 +916,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
             } else if (riscv_cpu_virt_enabled(env)) {
                 /* Trap into HS mode, from virt */
                 riscv_cpu_swap_hypervisor_regs(env);
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
-                                         get_field(env->hstatus, HSTATUS_SPV));
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
                                          get_field(env->mstatus, SSTATUS_SPP));
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                          riscv_cpu_virt_enabled(env));
@@ -929,10 +927,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
-                                         get_field(env->hstatus, HSTATUS_SPV));
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
-                                         get_field(env->mstatus, SSTATUS_SPP));
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                          riscv_cpu_virt_enabled(env));
 
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e0053699cc..efc2d854eb 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
         prev_priv = get_field(mstatus, MSTATUS_SPP);
         prev_virt = get_field(hstatus, HSTATUS_SPV);
 
-        hstatus = set_field(hstatus, HSTATUS_SPV,
-                                 get_field(hstatus, HSTATUS_SP2V));
-        mstatus = set_field(mstatus, MSTATUS_SPP,
-                            get_field(hstatus, HSTATUS_SP2P));
-        hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
-        hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
+        hstatus = set_field(hstatus, HSTATUS_SPV, 0);
+        mstatus = set_field(mstatus, MSTATUS_SPP, 0);
         mstatus = set_field(mstatus, SSTATUS_SIE,
                             get_field(mstatus, SSTATUS_SPIE));
         mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ce71ca7a92..1d973b62e9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -754,16 +754,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #if !defined(CONFIG_USER_ONLY)
     if (riscv_has_ext(env, RVH)) {
         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
-        if (env->priv_ver == PRV_M &&
-            get_field(env->mstatus, MSTATUS_MPRV) &&
-            MSTATUS_MPV_ISSET(env)) {
-            ctx->virt_enabled = true;
-        } else if (env->priv == PRV_S &&
-                   !riscv_cpu_virt_enabled(env) &&
-                   get_field(env->hstatus, HSTATUS_SPRV) &&
-                   get_field(env->hstatus, HSTATUS_SPV)) {
-            ctx->virt_enabled = true;
-        }
     } else {
         ctx->virt_enabled = false;
     }
-- 
2.26.2



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com, anup.pate@wdc.com
Subject: [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry
Date: Thu,  4 Jun 2020 18:21:12 -0700	[thread overview]
Message-ID: <04e964562dcef49f0f54f28f8ea2cfa386fba8f3.1591319882.git.alistair@alistair23.me> (raw)
In-Reply-To: <cover.1591319882.git.alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c |  8 +-------
 target/riscv/op_helper.c  |  8 ++------
 target/riscv/translate.c  | 10 ----------
 4 files changed, 4 insertions(+), 23 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 028e268faa..6b97c27711 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -430,6 +430,7 @@
 #define HSTATUS_VTSR         0x00400000
 #define HSTATUS_HU           0x00000200
 #define HSTATUS_GVA          0x00000040
+#define HSTATUS_SPVP         0x00000100
 
 #define HSTATUS32_WPRI       0xFF8FF87E
 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4ea39d5641..c4085e5870 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -916,9 +916,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
             } else if (riscv_cpu_virt_enabled(env)) {
                 /* Trap into HS mode, from virt */
                 riscv_cpu_swap_hypervisor_regs(env);
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
-                                         get_field(env->hstatus, HSTATUS_SPV));
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
+                env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
                                          get_field(env->mstatus, SSTATUS_SPP));
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                          riscv_cpu_virt_enabled(env));
@@ -929,10 +927,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
                 /* Trap into HS mode */
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
-                                         get_field(env->hstatus, HSTATUS_SPV));
-                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
-                                         get_field(env->mstatus, SSTATUS_SPP));
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                          riscv_cpu_virt_enabled(env));
 
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e0053699cc..efc2d854eb 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
         prev_priv = get_field(mstatus, MSTATUS_SPP);
         prev_virt = get_field(hstatus, HSTATUS_SPV);
 
-        hstatus = set_field(hstatus, HSTATUS_SPV,
-                                 get_field(hstatus, HSTATUS_SP2V));
-        mstatus = set_field(mstatus, MSTATUS_SPP,
-                            get_field(hstatus, HSTATUS_SP2P));
-        hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
-        hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
+        hstatus = set_field(hstatus, HSTATUS_SPV, 0);
+        mstatus = set_field(mstatus, MSTATUS_SPP, 0);
         mstatus = set_field(mstatus, SSTATUS_SIE,
                             get_field(mstatus, SSTATUS_SPIE));
         mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ce71ca7a92..1d973b62e9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -754,16 +754,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #if !defined(CONFIG_USER_ONLY)
     if (riscv_has_ext(env, RVH)) {
         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
-        if (env->priv_ver == PRV_M &&
-            get_field(env->mstatus, MSTATUS_MPRV) &&
-            MSTATUS_MPV_ISSET(env)) {
-            ctx->virt_enabled = true;
-        } else if (env->priv == PRV_S &&
-                   !riscv_cpu_virt_enabled(env) &&
-                   get_field(env->hstatus, HSTATUS_SPRV) &&
-                   get_field(env->hstatus, HSTATUS_SPV)) {
-            ctx->virt_enabled = true;
-        }
     } else {
         ctx->virt_enabled = false;
     }
-- 
2.26.2



  parent reply	other threads:[~2020-06-05  1:33 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05  1:20 [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1 Alistair Francis
2020-06-05  1:20 ` Alistair Francis
2020-06-05  1:20 ` [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:49   ` Richard Henderson
2020-06-05 17:49     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:50   ` Richard Henderson
2020-06-05 17:50     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:52   ` Richard Henderson
2020-06-05 17:52     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 04/17] target/riscv: Implement checks for hfence Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:54   ` Richard Henderson
2020-06-05 17:54     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05  1:20 ` [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 07/17] target/riscv: Do two-stage lookups on " Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 10/17] target/riscv: Fix the interrupt cause code Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` Alistair Francis [this message]
2020-06-05  1:21   ` [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-06-05  1:21 ` [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 13/17] target/riscv: Only support a single VSXL length Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 14/17] target/riscv: Only support little endian guests Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-06-05  1:21   ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=04e964562dcef49f0f54f28f8ea2cfa386fba8f3.1591319882.git.alistair@alistair23.me \
    --to=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=anup.pate@wdc.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.