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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v2 04/17] target/riscv: Implement checks for hfence
Date: Thu,  4 Jun 2020 18:20:53 -0700	[thread overview]
Message-ID: <c78f245c8d1629f1bce1387ba623a0215767f804.1591319882.git.alistair@alistair23.me> (raw)
In-Reply-To: <cover.1591319882.git.alistair@alistair23.me>

Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  5 ++++
 target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++--------------------
 target/riscv/op_helper.c                | 13 ++++++++++
 3 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index debb22a480..b36be978d5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,3 +76,8 @@ DEF_HELPER_2(mret, tl, env, tl)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
+
+/* Hypervisor functions */
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(hyp_tlb_flush, void, env)
+#endif
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index 2c0359819d..263b652d90 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -18,40 +18,20 @@
 
 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
 {
+    REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
-        has_ext(ctx, RVH)) {
-        /* Hpervisor extensions exist */
-        /*
-         * if (env->priv == PRV_M ||
-         *   (env->priv == PRV_S &&
-         *    !riscv_cpu_virt_enabled(env) &&
-         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
-         */
-            gen_helper_tlb_flush(cpu_env);
-            return true;
-        /* } */
-    }
+    gen_helper_hyp_tlb_flush(cpu_env);
+    return true;
 #endif
     return false;
 }
 
 static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
 {
+    REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
-        has_ext(ctx, RVH)) {
-        /* Hpervisor extensions exist */
-        /*
-         * if (env->priv == PRV_M ||
-         *   (env->priv == PRV_S &&
-         *    !riscv_cpu_virt_enabled(env) &&
-         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
-         */
-            gen_helper_tlb_flush(cpu_env);
-            return true;
-        /* } */
-    }
+    gen_helper_hyp_tlb_flush(cpu_env);
+    return true;
 #endif
     return false;
 }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b0c49efc4a..7cccd42a1e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -194,4 +194,17 @@ void helper_tlb_flush(CPURISCVState *env)
     }
 }
 
+void helper_hyp_tlb_flush(CPURISCVState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    if (env->priv == PRV_M ||
+        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
+        tlb_flush(cs);
+        return;
+    }
+
+    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
 #endif /* !CONFIG_USER_ONLY */
-- 
2.26.2



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com, anup.pate@wdc.com
Subject: [PATCH v2 04/17] target/riscv: Implement checks for hfence
Date: Thu,  4 Jun 2020 18:20:53 -0700	[thread overview]
Message-ID: <c78f245c8d1629f1bce1387ba623a0215767f804.1591319882.git.alistair@alistair23.me> (raw)
In-Reply-To: <cover.1591319882.git.alistair@alistair23.me>

Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  5 ++++
 target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++--------------------
 target/riscv/op_helper.c                | 13 ++++++++++
 3 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index debb22a480..b36be978d5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,3 +76,8 @@ DEF_HELPER_2(mret, tl, env, tl)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
+
+/* Hypervisor functions */
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(hyp_tlb_flush, void, env)
+#endif
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index 2c0359819d..263b652d90 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -18,40 +18,20 @@
 
 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
 {
+    REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
-        has_ext(ctx, RVH)) {
-        /* Hpervisor extensions exist */
-        /*
-         * if (env->priv == PRV_M ||
-         *   (env->priv == PRV_S &&
-         *    !riscv_cpu_virt_enabled(env) &&
-         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
-         */
-            gen_helper_tlb_flush(cpu_env);
-            return true;
-        /* } */
-    }
+    gen_helper_hyp_tlb_flush(cpu_env);
+    return true;
 #endif
     return false;
 }
 
 static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
 {
+    REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
-        has_ext(ctx, RVH)) {
-        /* Hpervisor extensions exist */
-        /*
-         * if (env->priv == PRV_M ||
-         *   (env->priv == PRV_S &&
-         *    !riscv_cpu_virt_enabled(env) &&
-         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
-         */
-            gen_helper_tlb_flush(cpu_env);
-            return true;
-        /* } */
-    }
+    gen_helper_hyp_tlb_flush(cpu_env);
+    return true;
 #endif
     return false;
 }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b0c49efc4a..7cccd42a1e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -194,4 +194,17 @@ void helper_tlb_flush(CPURISCVState *env)
     }
 }
 
+void helper_hyp_tlb_flush(CPURISCVState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    if (env->priv == PRV_M ||
+        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
+        tlb_flush(cs);
+        return;
+    }
+
+    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
 #endif /* !CONFIG_USER_ONLY */
-- 
2.26.2



  parent reply	other threads:[~2020-06-05  1:30 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05  1:20 [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1 Alistair Francis
2020-06-05  1:20 ` Alistair Francis
2020-06-05  1:20 ` [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:49   ` Richard Henderson
2020-06-05 17:49     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:50   ` Richard Henderson
2020-06-05 17:50     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:52   ` Richard Henderson
2020-06-05 17:52     ` Richard Henderson
2020-06-05  1:20 ` Alistair Francis [this message]
2020-06-05  1:20   ` [PATCH v2 04/17] target/riscv: Implement checks for hfence Alistair Francis
2020-06-05 17:54   ` Richard Henderson
2020-06-05 17:54     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05  1:20 ` [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 07/17] target/riscv: Do two-stage lookups on " Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 10/17] target/riscv: Fix the interrupt cause code Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 13/17] target/riscv: Only support a single VSXL length Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 14/17] target/riscv: Only support little endian guests Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-06-05  1:21   ` Alistair Francis

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