All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs
Date: Thu,  4 Jun 2020 18:21:24 -0700	[thread overview]
Message-ID: <5dbe9e7536efbd41f775fc3c189c49b39b83f724.1591319882.git.alistair@alistair23.me> (raw)
In-Reply-To: <cover.1591319882.git.alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/csr.c      | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8a145e0a32..690f327828 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -182,9 +182,12 @@
 #define CSR_HIDELEG         0x603
 #define CSR_HIE             0x604
 #define CSR_HCOUNTEREN      0x606
+#define CSR_HGEIE           0x607
 #define CSR_HTVAL           0x643
+#define CSR_HVIP            0x645
 #define CSR_HIP             0x644
 #define CSR_HTINST          0x64A
+#define CSR_HGEIP           0xE12
 #define CSR_HGATP           0x680
 #define CSR_HTIMEDELTA      0x605
 #define CSR_HTIMEDELTAH     0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5b64539efb..9990a0dd09 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -815,12 +815,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                   target_ulong new_value, target_ulong write_mask)
+{
+    int ret = rmw_mip(env, 0, ret_value, new_value,
+                      write_mask & hip_writable_mask);
+
+    *ret_value &= hip_writable_mask;
+
+    return ret;
+}
+
 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
 
+    *ret_value &= hip_writable_mask;
+
     return ret;
 }
 
@@ -848,6 +861,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->htval;
@@ -871,6 +896,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->hgatp;
@@ -1268,11 +1305,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HSTATUS] =             { hmode,   read_hstatus,     write_hstatus    },
     [CSR_HEDELEG] =             { hmode,   read_hedeleg,     write_hedeleg    },
     [CSR_HIDELEG] =             { hmode,   read_hideleg,     write_hideleg    },
+    [CSR_HVIP] =                { hmode,   NULL,     NULL,     rmw_hvip       },
     [CSR_HIP] =                 { hmode,   NULL,     NULL,     rmw_hip        },
     [CSR_HIE] =                 { hmode,   read_hie,         write_hie        },
     [CSR_HCOUNTEREN] =          { hmode,   read_hcounteren,  write_hcounteren },
+    [CSR_HGEIE] =               { hmode,   read_hgeie,       write_hgeie      },
     [CSR_HTVAL] =               { hmode,   read_htval,       write_htval      },
     [CSR_HTINST] =              { hmode,   read_htinst,      write_htinst     },
+    [CSR_HGEIP] =               { hmode,   read_hgeip,       write_hgeip      },
     [CSR_HGATP] =               { hmode,   read_hgatp,       write_hgatp      },
     [CSR_HTIMEDELTA] =          { hmode,   read_htimedelta,  write_htimedelta },
 #if defined(TARGET_RISCV32)
-- 
2.26.2



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com, anup.pate@wdc.com
Subject: [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs
Date: Thu,  4 Jun 2020 18:21:24 -0700	[thread overview]
Message-ID: <5dbe9e7536efbd41f775fc3c189c49b39b83f724.1591319882.git.alistair@alistair23.me> (raw)
In-Reply-To: <cover.1591319882.git.alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/csr.c      | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8a145e0a32..690f327828 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -182,9 +182,12 @@
 #define CSR_HIDELEG         0x603
 #define CSR_HIE             0x604
 #define CSR_HCOUNTEREN      0x606
+#define CSR_HGEIE           0x607
 #define CSR_HTVAL           0x643
+#define CSR_HVIP            0x645
 #define CSR_HIP             0x644
 #define CSR_HTINST          0x64A
+#define CSR_HGEIP           0xE12
 #define CSR_HGATP           0x680
 #define CSR_HTIMEDELTA      0x605
 #define CSR_HTIMEDELTAH     0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5b64539efb..9990a0dd09 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -815,12 +815,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                   target_ulong new_value, target_ulong write_mask)
+{
+    int ret = rmw_mip(env, 0, ret_value, new_value,
+                      write_mask & hip_writable_mask);
+
+    *ret_value &= hip_writable_mask;
+
+    return ret;
+}
+
 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
 
+    *ret_value &= hip_writable_mask;
+
     return ret;
 }
 
@@ -848,6 +861,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->htval;
@@ -871,6 +896,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->hgatp;
@@ -1268,11 +1305,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HSTATUS] =             { hmode,   read_hstatus,     write_hstatus    },
     [CSR_HEDELEG] =             { hmode,   read_hedeleg,     write_hedeleg    },
     [CSR_HIDELEG] =             { hmode,   read_hideleg,     write_hideleg    },
+    [CSR_HVIP] =                { hmode,   NULL,     NULL,     rmw_hvip       },
     [CSR_HIP] =                 { hmode,   NULL,     NULL,     rmw_hip        },
     [CSR_HIE] =                 { hmode,   read_hie,         write_hie        },
     [CSR_HCOUNTEREN] =          { hmode,   read_hcounteren,  write_hcounteren },
+    [CSR_HGEIE] =               { hmode,   read_hgeie,       write_hgeie      },
     [CSR_HTVAL] =               { hmode,   read_htval,       write_htval      },
     [CSR_HTINST] =              { hmode,   read_htinst,      write_htinst     },
+    [CSR_HGEIP] =               { hmode,   read_hgeip,       write_hgeip      },
     [CSR_HGATP] =               { hmode,   read_hgatp,       write_hgatp      },
     [CSR_HTIMEDELTA] =          { hmode,   read_htimedelta,  write_htimedelta },
 #if defined(TARGET_RISCV32)
-- 
2.26.2



  parent reply	other threads:[~2020-06-05  1:37 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05  1:20 [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1 Alistair Francis
2020-06-05  1:20 ` Alistair Francis
2020-06-05  1:20 ` [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:49   ` Richard Henderson
2020-06-05 17:49     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:50   ` Richard Henderson
2020-06-05 17:50     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:52   ` Richard Henderson
2020-06-05 17:52     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 04/17] target/riscv: Implement checks for hfence Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05 17:54   ` Richard Henderson
2020-06-05 17:54     ` Richard Henderson
2020-06-05  1:20 ` [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05  1:20 ` [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis
2020-06-05  1:20   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 07/17] target/riscv: Do two-stage lookups on " Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 10/17] target/riscv: Fix the interrupt cause code Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 13/17] target/riscv: Only support a single VSXL length Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 14/17] target/riscv: Only support little endian guests Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` Alistair Francis [this message]
2020-06-05  1:21   ` [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-06-05  1:21 ` [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-06-05  1:21   ` Alistair Francis
2020-06-05  1:21 ` [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-06-05  1:21   ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5dbe9e7536efbd41f775fc3c189c49b39b83f724.1591319882.git.alistair@alistair23.me \
    --to=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=anup.pate@wdc.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.