Re: [RFC PATCH 00/13] Support UXL field in mstatus

[LIU Zhiwei <zhiwei_liu@c-sky.com>]

On 2021/8/6 下午6:05, Alistair Francis wrote:
> On Thu, Aug 5, 2021 at 5:15 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>
>> On 2021/8/5 下午2:01, Alistair Francis wrote:
>>> On Thu, Aug 5, 2021 at 12:55 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>>> This patch set implements UXL field in mstatus register. Programmer can change
>>>> UXLEN by writting to this field. So that you can run a 32 bit program
>>>> on a 64 bit CPU.
>>> Awesome! Do you have any steps for building a rootFS to test this?
>> Not yet.  It depends on Linux support which  will not start until
>> October.  Maybe as a rough test,
>> we can run the 32 glibc test cases on qemu-riscv64 with an option
>> uxl32=true(not implement yet).
> Hmmm... That's a pain. We really need some way to test this (and
> ensure no future breakages occur). But I see the problem of no
> software support until this exists.
>
> It sounds like you or a colleague is planning on adding Linux support.
> Maybe we will have to wait until that at least exists before this can
> go upstream. We could at least review this before hand though

Enough for me. Thanks. I will also think more about Richard's advice, 
maybe we can merge 32bit cpu and UXL32 into one in the future.

Zhiwei

> , so
> thanks for sending the series.
>
> A 32-bit glibc test on qemu-riscv64 would probably also be enough, at
> least as a start.
>
> Alistair
>
>> Zhiwei
>>
>>> Alistair
>>>
>>>> This patch set depends on one patch set by Richard Henderson
>>>> https://lists.gnu.org/archive/html/qemu-riscv/2021-07/msg00059.html.
>>>>
>>>> LIU Zhiwei (13):
>>>>     target/riscv: Add UXL to tb flags
>>>>     target/riscv: Support UXL32 for branch instructions
>>>>     target/riscv: Support UXL32 on 64-bit cpu for load/store
>>>>     target/riscv: Support UXL32 for slit/sltiu
>>>>     target/riscv: Support UXL32 for shift instruction
>>>>     target/riscv: Fix div instructions
>>>>     target/riscv: Support UXL32 for RVM
>>>>     target/riscv: Support UXL32 for vector instructions
>>>>     target/riscv: Support UXL32 for atomic instructions
>>>>     target/riscv: Support UXL32 for float instructions
>>>>     target/riscv: Fix srow
>>>>     target/riscv: Support UXL32 for RVB
>>>>     target/riscv: Changing the width of U-mode CSR
>>>>
>>>>    target/riscv/cpu.h                      |  18 +++
>>>>    target/riscv/csr.c                      |  42 +++++-
>>>>    target/riscv/insn_trans/trans_rva.c.inc |  36 ++++-
>>>>    target/riscv/insn_trans/trans_rvb.c.inc |  51 +++++--
>>>>    target/riscv/insn_trans/trans_rvd.c.inc |   4 +-
>>>>    target/riscv/insn_trans/trans_rvf.c.inc |   4 +-
>>>>    target/riscv/insn_trans/trans_rvi.c.inc |  62 ++++++--
>>>>    target/riscv/insn_trans/trans_rvm.c.inc |  24 ++-
>>>>    target/riscv/insn_trans/trans_rvv.c.inc |  44 +++---
>>>>    target/riscv/translate.c                | 186 ++++++++++++++++++++----
>>>>    target/riscv/vector_helper.c            |  54 +++++--
>>>>    11 files changed, 414 insertions(+), 111 deletions(-)
>>>>
>>>> --
>>>> 2.17.1
>>>>
>>>>