From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [RFC PATCH 00/13] Support UXL field in mstatus
Date: Thu, 5 Aug 2021 16:10:35 +0800 [thread overview]
Message-ID: <ff34c24d-540e-f286-d28e-898c726ca94d@c-sky.com> (raw)
In-Reply-To: <CAEUhbmU0TVvMvUi52kBYNJR0zjpoBmR6+3-PjOUu2r+6HL5qaA@mail.gmail.com>
On 2021/8/5 下午3:20, Bin Meng wrote:
> On Thu, Aug 5, 2021 at 3:16 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>
>> On 2021/8/5 下午2:01, Alistair Francis wrote:
>>> On Thu, Aug 5, 2021 at 12:55 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>>> This patch set implements UXL field in mstatus register. Programmer can change
>>>> UXLEN by writting to this field. So that you can run a 32 bit program
>>>> on a 64 bit CPU.
>>> Awesome! Do you have any steps for building a rootFS to test this?
>> Not yet. It depends on Linux support which will not start until
>> October. Maybe as a rough test,
>> we can run the 32 glibc test cases on qemu-riscv64 with an option
>> uxl32=true(not implement yet).
> That's my understanding as well. Currently there is no software stack
> that supports mode switch, e.g.: OpenSBI boots in 64-bit but loading a
> 32-bit payload to execute.
>
> Do you plan to support SXL as well?
Sorry, SXL is not planned. If I have enough time later, I will have
a try.
Zhiwei
>
> Regards,
> Bin
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <alistair23@gmail.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [RFC PATCH 00/13] Support UXL field in mstatus
Date: Thu, 5 Aug 2021 16:10:35 +0800 [thread overview]
Message-ID: <ff34c24d-540e-f286-d28e-898c726ca94d@c-sky.com> (raw)
In-Reply-To: <CAEUhbmU0TVvMvUi52kBYNJR0zjpoBmR6+3-PjOUu2r+6HL5qaA@mail.gmail.com>
On 2021/8/5 下午3:20, Bin Meng wrote:
> On Thu, Aug 5, 2021 at 3:16 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>
>> On 2021/8/5 下午2:01, Alistair Francis wrote:
>>> On Thu, Aug 5, 2021 at 12:55 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>>> This patch set implements UXL field in mstatus register. Programmer can change
>>>> UXLEN by writting to this field. So that you can run a 32 bit program
>>>> on a 64 bit CPU.
>>> Awesome! Do you have any steps for building a rootFS to test this?
>> Not yet. It depends on Linux support which will not start until
>> October. Maybe as a rough test,
>> we can run the 32 glibc test cases on qemu-riscv64 with an option
>> uxl32=true(not implement yet).
> That's my understanding as well. Currently there is no software stack
> that supports mode switch, e.g.: OpenSBI boots in 64-bit but loading a
> 32-bit payload to execute.
>
> Do you plan to support SXL as well?
Sorry, SXL is not planned. If I have enough time later, I will have
a try.
Zhiwei
>
> Regards,
> Bin
next prev parent reply other threads:[~2021-08-05 8:14 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 2:52 [RFC PATCH 00/13] Support UXL field in mstatus LIU Zhiwei
2021-08-05 2:52 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 6:00 ` Alistair Francis
2021-08-05 6:00 ` Alistair Francis
2021-08-05 19:01 ` Richard Henderson
2021-08-05 19:01 ` Richard Henderson
2021-08-06 2:49 ` LIU Zhiwei
2021-08-06 2:49 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 19:06 ` Richard Henderson
2021-08-05 19:06 ` Richard Henderson
2021-08-09 1:45 ` LIU Zhiwei
2021-08-09 1:45 ` LIU Zhiwei
2021-08-09 19:34 ` Richard Henderson
2021-08-09 19:34 ` Richard Henderson
2021-08-11 14:57 ` LIU Zhiwei
2021-08-11 14:57 ` LIU Zhiwei
2021-08-11 17:56 ` Richard Henderson
2021-08-11 17:56 ` Richard Henderson
2021-08-11 22:40 ` LIU Zhiwei
2021-08-11 22:40 ` LIU Zhiwei
2021-08-12 4:42 ` Richard Henderson
2021-08-12 4:42 ` Richard Henderson
2021-08-12 5:03 ` LIU Zhiwei
2021-08-12 5:03 ` LIU Zhiwei
2021-08-12 6:12 ` Richard Henderson
2021-08-12 6:12 ` Richard Henderson
2021-08-12 7:20 ` LIU Zhiwei
2021-08-12 7:20 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 19:08 ` Richard Henderson
2021-08-05 19:08 ` Richard Henderson
2021-08-09 1:50 ` LIU Zhiwei
2021-08-09 1:50 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 19:09 ` Richard Henderson
2021-08-05 19:09 ` Richard Henderson
2021-08-09 7:28 ` LIU Zhiwei
2021-08-09 7:28 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 22:17 ` Richard Henderson
2021-08-05 22:17 ` Richard Henderson
2021-08-09 7:51 ` LIU Zhiwei
2021-08-09 7:51 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 06/13] target/riscv: Fix div instructions LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 22:18 ` Richard Henderson
2021-08-05 22:18 ` Richard Henderson
2021-08-09 7:53 ` LIU Zhiwei
2021-08-09 7:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 11/13] target/riscv: Fix srow LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR LIU Zhiwei
2021-08-05 2:53 ` LIU Zhiwei
2021-08-05 6:01 ` [RFC PATCH 00/13] Support UXL field in mstatus Alistair Francis
2021-08-05 6:01 ` Alistair Francis
2021-08-05 7:14 ` LIU Zhiwei
2021-08-05 7:14 ` LIU Zhiwei
2021-08-05 7:20 ` Bin Meng
2021-08-05 7:20 ` Bin Meng
2021-08-05 8:10 ` LIU Zhiwei [this message]
2021-08-05 8:10 ` LIU Zhiwei
2021-08-06 10:05 ` Alistair Francis
2021-08-06 10:05 ` Alistair Francis
2021-08-09 1:25 ` LIU Zhiwei
2021-08-09 1:25 ` LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ff34c24d-540e-f286-d28e-898c726ca94d@c-sky.com \
--to=zhiwei_liu@c-sky.com \
--cc=Alistair.Francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bin.meng@windriver.com \
--cc=bmeng.cn@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.